1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __QCOM_TLMM_VAR_H__ 31 #define __QCOM_TLMM_VAR_H__ 32 33 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) 34 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) 35 #define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) 36 37 /* 38 * register space access macros 39 */ 40 #define GPIO_WRITE(sc, reg, val) do { \ 41 bus_write_4(sc->gpio_mem_res, (reg), (val)); \ 42 } while (0) 43 44 #define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg)) 45 46 #define GPIO_SET_BITS(sc, reg, bits) \ 47 GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits)) 48 49 #define GPIO_CLEAR_BITS(sc, reg, bits) \ 50 GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits)) 51 52 53 enum prop_id { 54 PIN_ID_BIAS_DISABLE = 0, 55 PIN_ID_BIAS_HIGH_IMPEDANCE, 56 PIN_ID_BIAS_BUS_HOLD, 57 PIN_ID_BIAS_PULL_UP, 58 PIN_ID_BIAS_PULL_DOWN, 59 PIN_ID_BIAS_PULL_PIN_DEFAULT, 60 PIN_ID_DRIVE_PUSH_PULL, 61 PIN_ID_DRIVE_OPEN_DRAIN, 62 PIN_ID_DRIVE_OPEN_SOURCE, 63 PIN_ID_DRIVE_STRENGTH, 64 PIN_ID_INPUT_ENABLE, 65 PIN_ID_INPUT_DISABLE, 66 PIN_ID_INPUT_SCHMITT_ENABLE, 67 PIN_ID_INPUT_SCHMITT_DISABLE, 68 PIN_ID_INPUT_DEBOUNCE, 69 PIN_ID_POWER_SOURCE, 70 PIN_ID_SLEW_RATE, 71 PIN_ID_LOW_POWER_MODE_ENABLE, 72 PIN_ID_LOW_POWER_MODE_DISABLE, 73 PIN_ID_OUTPUT_LOW, 74 PIN_ID_OUTPUT_HIGH, 75 PIN_ID_VM_ENABLE, 76 PIN_ID_VM_DISABLE, 77 PROP_ID_MAX_ID 78 }; 79 80 struct qcom_tlmm_prop_name { 81 const char *name; 82 enum prop_id id; 83 int have_value; 84 }; 85 86 /* 87 * Pull-up / pull-down configuration. 88 */ 89 typedef enum { 90 QCOM_TLMM_PIN_PUPD_CONFIG_DISABLE = 0, 91 QCOM_TLMM_PIN_PUPD_CONFIG_PULL_DOWN = 1, 92 QCOM_TLMM_PIN_PUPD_CONFIG_PULL_UP = 2, 93 QCOM_TLMM_PIN_PUPD_CONFIG_BUS_HOLD = 3, 94 } qcom_tlmm_pin_pupd_config_t; 95 96 97 /* 98 * Pull-up / pull-down resistor configuration. 99 */ 100 typedef enum { 101 QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_10K = 0, 102 QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_1K5 = 1, 103 QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_35K = 2, 104 QCOM_TLMM_PIN_RESISTOR_PUPD_CONFIG_20K = 3, 105 } qcom_tlmm_pin_resistor_pupd_config_t; 106 107 /* 108 * configuration for one pin group. 109 */ 110 struct qcom_tlmm_pinctrl_cfg { 111 char *function; 112 int params[PROP_ID_MAX_ID]; 113 }; 114 115 #define GDEF(_id, ...) \ 116 { \ 117 .id = _id, \ 118 .name = "gpio" #_id, \ 119 .functions = {"gpio", __VA_ARGS__} \ 120 } 121 122 struct qcom_tlmm_gpio_mux { 123 int id; 124 char *name; 125 char *functions[16]; /* XXX */ 126 }; 127 128 #define SDEF(n, r, ps, hs...) \ 129 { \ 130 .name = n, \ 131 .reg = r, \ 132 .pull_shift = ps, \ 133 .hdrv_shift = hs, \ 134 } 135 136 137 struct qcom_tlmm_spec_pin { 138 char *name; 139 uint32_t reg; 140 uint32_t pull_shift; 141 uint32_t hdrv_shift; 142 }; 143 144 struct qcom_tlmm_softc { 145 device_t dev; 146 device_t busdev; 147 struct mtx gpio_mtx; 148 struct resource *gpio_mem_res; 149 int gpio_mem_rid; 150 struct resource *gpio_irq_res; 151 int gpio_irq_rid; 152 void *gpio_ih; 153 int gpio_npins; 154 struct gpio_pin *gpio_pins; 155 uint32_t sc_debug; 156 157 const struct qcom_tlmm_gpio_mux *gpio_muxes; 158 const struct qcom_tlmm_spec_pin *spec_pins; 159 }; 160 161 /* 162 * qcom_tlmm_pinmux.c 163 */ 164 extern int qcom_tlmm_pinctrl_configure(device_t dev, phandle_t cfgxref); 165 166 #endif /* __QCOM_TLMM_PINMUX_VAR_H__ */ 167