xref: /freebsd/sys/dev/qcom_tcsr/qcom_tcsr.c (revision fdafd315ad0d0f28a11b9fb4476a9ab059c62b92)
1d11f81afSAdrian Chadd /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3d11f81afSAdrian Chadd  *
4d11f81afSAdrian Chadd  * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
5d11f81afSAdrian Chadd  *
6d11f81afSAdrian Chadd  * Redistribution and use in source and binary forms, with or without
7d11f81afSAdrian Chadd  * modification, are permitted provided that the following conditions
8d11f81afSAdrian Chadd  * are met:
9d11f81afSAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
10d11f81afSAdrian Chadd  *    notice unmodified, this list of conditions, and the following
11d11f81afSAdrian Chadd  *    disclaimer.
12d11f81afSAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
13d11f81afSAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
14d11f81afSAdrian Chadd  *    documentation and/or other materials provided with the distribution.
15d11f81afSAdrian Chadd  *
16d11f81afSAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17d11f81afSAdrian Chadd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18d11f81afSAdrian Chadd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19d11f81afSAdrian Chadd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20d11f81afSAdrian Chadd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21d11f81afSAdrian Chadd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22d11f81afSAdrian Chadd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23d11f81afSAdrian Chadd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24d11f81afSAdrian Chadd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25d11f81afSAdrian Chadd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26d11f81afSAdrian Chadd  * SUCH DAMAGE.
27d11f81afSAdrian Chadd  */
28d11f81afSAdrian Chadd 
29d11f81afSAdrian Chadd #include <sys/param.h>
30d11f81afSAdrian Chadd #include <sys/systm.h>
31d11f81afSAdrian Chadd 
32d11f81afSAdrian Chadd #include <sys/bus.h>
33d11f81afSAdrian Chadd #include <sys/interrupt.h>
34d11f81afSAdrian Chadd #include <sys/malloc.h>
35d11f81afSAdrian Chadd #include <sys/lock.h>
36d11f81afSAdrian Chadd #include <sys/mutex.h>
37d11f81afSAdrian Chadd #include <sys/kernel.h>
38d11f81afSAdrian Chadd #include <sys/module.h>
39d11f81afSAdrian Chadd #include <sys/rman.h>
40d11f81afSAdrian Chadd #include <sys/gpio.h>
41d11f81afSAdrian Chadd 
42d11f81afSAdrian Chadd #include <vm/vm.h>
43d11f81afSAdrian Chadd #include <vm/pmap.h>
44d11f81afSAdrian Chadd #include <vm/vm_extern.h>
45d11f81afSAdrian Chadd 
46d11f81afSAdrian Chadd #include <machine/bus.h>
47d11f81afSAdrian Chadd #include <machine/cpu.h>
48d11f81afSAdrian Chadd 
49d11f81afSAdrian Chadd #include <dev/fdt/fdt_common.h>
50d11f81afSAdrian Chadd #include <dev/fdt/fdt_pinctrl.h>
51d11f81afSAdrian Chadd 
52d11f81afSAdrian Chadd #include <dev/gpio/gpiobusvar.h>
53d11f81afSAdrian Chadd #include <dev/ofw/ofw_bus.h>
54d11f81afSAdrian Chadd #include <dev/ofw/ofw_bus_subr.h>
55d11f81afSAdrian Chadd 
56d11f81afSAdrian Chadd #include <dev/qcom_tcsr/qcom_tcsr_var.h>
57d11f81afSAdrian Chadd #include <dev/qcom_tcsr/qcom_tcsr_reg.h>
58d11f81afSAdrian Chadd 
59d11f81afSAdrian Chadd /*
60d11f81afSAdrian Chadd  * The linux-msm branches that support IPQ4018 use "ipq,tcsr".
61d11f81afSAdrian Chadd  * The openwrt addons use qcom,tcsr.  So for now support both.
62d11f81afSAdrian Chadd  *
63d11f81afSAdrian Chadd  * Also, it's not quite clear yet (since this is the first port!)
64d11f81afSAdrian Chadd  * whether these options and registers are specific to the QCA IPQ401x
65d11f81afSAdrian Chadd  * part or show up in different linux branches as different registers
66d11f81afSAdrian Chadd  * but with the same driver/naming here.  Let's hope that doesn't
67d11f81afSAdrian Chadd  * happen.
68d11f81afSAdrian Chadd  */
69d11f81afSAdrian Chadd static struct ofw_compat_data compat_data[] = {
70d11f81afSAdrian Chadd 	{ "qcom,tcsr",			1 },
71d11f81afSAdrian Chadd 	{ "ipq,tcsr",			1 },
72d11f81afSAdrian Chadd 	{ NULL,				0 }
73d11f81afSAdrian Chadd };
74d11f81afSAdrian Chadd 
75d11f81afSAdrian Chadd static int
qcom_tcsr_probe(device_t dev)76d11f81afSAdrian Chadd qcom_tcsr_probe(device_t dev)
77d11f81afSAdrian Chadd {
78d11f81afSAdrian Chadd 
79d11f81afSAdrian Chadd 	if (!ofw_bus_status_okay(dev))
80d11f81afSAdrian Chadd 		return (ENXIO);
81d11f81afSAdrian Chadd 
82d11f81afSAdrian Chadd 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
83d11f81afSAdrian Chadd 		return (ENXIO);
84d11f81afSAdrian Chadd 
85d11f81afSAdrian Chadd 	device_set_desc(dev, "Qualcomm Core Top Control and Status Driver");
86d11f81afSAdrian Chadd 	return (BUS_PROBE_DEFAULT);
87d11f81afSAdrian Chadd }
88d11f81afSAdrian Chadd 
89d11f81afSAdrian Chadd static int
qcom_tcsr_attach(device_t dev)90d11f81afSAdrian Chadd qcom_tcsr_attach(device_t dev)
91d11f81afSAdrian Chadd {
92d11f81afSAdrian Chadd 	struct qcom_tcsr_softc *sc = device_get_softc(dev);
93d11f81afSAdrian Chadd 	int rid, ret;
94d11f81afSAdrian Chadd 	uint32_t val;
95d11f81afSAdrian Chadd 
96d11f81afSAdrian Chadd 	sc->sc_dev = dev;
97d11f81afSAdrian Chadd 
98d11f81afSAdrian Chadd 	/*
99d11f81afSAdrian Chadd 	 * Hardware version is stored in the ofw_compat_data table.
100d11f81afSAdrian Chadd 	 */
101d11f81afSAdrian Chadd 	sc->hw_version =
102d11f81afSAdrian Chadd 	    ofw_bus_search_compatible(dev, compat_data)->ocd_data;
103d11f81afSAdrian Chadd 
104d11f81afSAdrian Chadd 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
105d11f81afSAdrian Chadd 
106d11f81afSAdrian Chadd 	rid = 0;
107d11f81afSAdrian Chadd 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
108d11f81afSAdrian Chadd 	    RF_ACTIVE);
109d11f81afSAdrian Chadd 	if (!sc->sc_mem_res) {
110d11f81afSAdrian Chadd 		device_printf(dev, "ERROR: Could not map memory\n");
111d11f81afSAdrian Chadd 		ret = ENXIO;
112d11f81afSAdrian Chadd 		goto error;
113d11f81afSAdrian Chadd 	}
114d11f81afSAdrian Chadd 
115d11f81afSAdrian Chadd 	/*
116d11f81afSAdrian Chadd 	 * Parse out the open firmware entries to see which particular
117d11f81afSAdrian Chadd 	 * configurations we need to set here.
118d11f81afSAdrian Chadd 	 */
119d11f81afSAdrian Chadd 
120d11f81afSAdrian Chadd 	/*
121d11f81afSAdrian Chadd 	 * USB control select.
122d11f81afSAdrian Chadd 	 *
123d11f81afSAdrian Chadd 	 * For linux-msm on the IPQ401x, it actually calls into the SCM
124d11f81afSAdrian Chadd 	 * to make the change.  OpenWRT just does a register write.
125d11f81afSAdrian Chadd 	 * We'll do the register write for now.
126d11f81afSAdrian Chadd 	 */
127d11f81afSAdrian Chadd 	if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-ctrl-select",
128d11f81afSAdrian Chadd 	    &val, sizeof(val)) > 0) {
129d11f81afSAdrian Chadd 		if (bootverbose)
130d11f81afSAdrian Chadd 			device_printf(sc->sc_dev,
131d11f81afSAdrian Chadd 			    "USB control select (val 0x%x)\n",
132d11f81afSAdrian Chadd 			    val);
133d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_PORT_SEL, val);
134d11f81afSAdrian Chadd 	}
135d11f81afSAdrian Chadd 
136d11f81afSAdrian Chadd 	/*
137d11f81afSAdrian Chadd 	 * USB high speed phy mode select.
138d11f81afSAdrian Chadd 	 */
139d11f81afSAdrian Chadd 	if (OF_getencprop(ofw_bus_get_node(dev), "qcom,usb-hsphy-mode-select",
140d11f81afSAdrian Chadd 	    &val, sizeof(val)) > 0) {
141d11f81afSAdrian Chadd 		if (bootverbose)
142d11f81afSAdrian Chadd 			device_printf(sc->sc_dev,
143d11f81afSAdrian Chadd 			    "USB high speed PHY mode select (val 0x%x)\n",
144d11f81afSAdrian Chadd 			    val);
145d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_USB_HSPHY_CONFIG, val);
146d11f81afSAdrian Chadd 	}
147d11f81afSAdrian Chadd 
148d11f81afSAdrian Chadd 	/*
149d11f81afSAdrian Chadd 	 * Ethernet switch subsystem interface type select.
150d11f81afSAdrian Chadd 	 */
151d11f81afSAdrian Chadd 	if (OF_getencprop(ofw_bus_get_node(dev), "qcom,ess-interface-select",
152d11f81afSAdrian Chadd 	    &val, sizeof(val)) > 0) {
153d11f81afSAdrian Chadd 		uint32_t reg;
154d11f81afSAdrian Chadd 
155d11f81afSAdrian Chadd 		if (bootverbose)
156d11f81afSAdrian Chadd 			device_printf(sc->sc_dev,
157d11f81afSAdrian Chadd 			    "ESS external interface select (val 0x%x)\n",
158d11f81afSAdrian Chadd 			    val);
159d11f81afSAdrian Chadd 		reg = QCOM_TCSR_READ_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET);
160d11f81afSAdrian Chadd 		reg &= ~QCOM_TCSR_ESS_INTERFACE_SEL_MASK;
161d11f81afSAdrian Chadd 		reg |= (val & QCOM_TCSR_ESS_INTERFACE_SEL_MASK);
162d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET, reg);
163d11f81afSAdrian Chadd 	}
164d11f81afSAdrian Chadd 
165d11f81afSAdrian Chadd 	/*
166d11f81afSAdrian Chadd 	 * WiFi GLB select.
167d11f81afSAdrian Chadd 	 */
168d11f81afSAdrian Chadd 	if (OF_getencprop(ofw_bus_get_node(dev), "qcom,wifi_glb_cfg",
169d11f81afSAdrian Chadd 	    &val, sizeof(val)) > 0) {
170d11f81afSAdrian Chadd 		if (bootverbose)
171d11f81afSAdrian Chadd 			device_printf(sc->sc_dev,
172d11f81afSAdrian Chadd 			    "WIFI GLB select (val 0x%x)\n",
173d11f81afSAdrian Chadd 			    val);
174d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI0_GLB_CFG_OFFSET, val);
175d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_WIFI1_GLB_CFG_OFFSET, val);
176d11f81afSAdrian Chadd 	}
177d11f81afSAdrian Chadd 
178d11f81afSAdrian Chadd 	/*
179d11f81afSAdrian Chadd 	 * WiFi NOC interconnect memory type.
180d11f81afSAdrian Chadd 	 */
181d11f81afSAdrian Chadd 	if (OF_getencprop(ofw_bus_get_node(dev),
182d11f81afSAdrian Chadd 	    "qcom,wifi_noc_memtype_m0_m2",
183d11f81afSAdrian Chadd 	    &val, sizeof(val)) > 0) {
184d11f81afSAdrian Chadd 		if (bootverbose)
185d11f81afSAdrian Chadd 			device_printf(sc->sc_dev,
186d11f81afSAdrian Chadd 			    "WiFi NOC memory type (val 0x%x)\n",
187d11f81afSAdrian Chadd 			    val);
188d11f81afSAdrian Chadd 		QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_PNOC_SNOC_MEMTYPE_M0_M2, val);
189d11f81afSAdrian Chadd 	}
190d11f81afSAdrian Chadd 
191d11f81afSAdrian Chadd 	return (0);
192d11f81afSAdrian Chadd 
193d11f81afSAdrian Chadd error:
194d11f81afSAdrian Chadd 	if (sc->sc_mem_res)
195d11f81afSAdrian Chadd 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
196d11f81afSAdrian Chadd 	mtx_destroy(&sc->sc_mtx);
197d11f81afSAdrian Chadd 	return (ret);
198d11f81afSAdrian Chadd }
199d11f81afSAdrian Chadd 
200d11f81afSAdrian Chadd static int
qcom_tcsr_detach(device_t dev)201d11f81afSAdrian Chadd qcom_tcsr_detach(device_t dev)
202d11f81afSAdrian Chadd {
203d11f81afSAdrian Chadd 	struct qcom_tcsr_softc *sc = device_get_softc(dev);
204d11f81afSAdrian Chadd 
205d11f81afSAdrian Chadd 	if (sc->sc_mem_res)
206d11f81afSAdrian Chadd 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
207d11f81afSAdrian Chadd 
208d11f81afSAdrian Chadd 	mtx_destroy(&sc->sc_mtx);
209d11f81afSAdrian Chadd 
210d11f81afSAdrian Chadd 	return (0);
211d11f81afSAdrian Chadd }
212d11f81afSAdrian Chadd 
213d11f81afSAdrian Chadd static device_method_t qcom_tcsr_methods[] = {
214d11f81afSAdrian Chadd 	/* Device interface */
215d11f81afSAdrian Chadd 	DEVMETHOD(device_probe,		qcom_tcsr_probe),
216d11f81afSAdrian Chadd 	DEVMETHOD(device_attach,	qcom_tcsr_attach),
217d11f81afSAdrian Chadd 	DEVMETHOD(device_detach,	qcom_tcsr_detach),
218d11f81afSAdrian Chadd 
219d11f81afSAdrian Chadd 	DEVMETHOD_END
220d11f81afSAdrian Chadd };
221d11f81afSAdrian Chadd 
222d11f81afSAdrian Chadd static driver_t qcom_tcsr_driver = {
223d11f81afSAdrian Chadd 	"qcom_tcsr",
224d11f81afSAdrian Chadd 	qcom_tcsr_methods,
225d11f81afSAdrian Chadd 	sizeof(struct qcom_tcsr_softc),
226d11f81afSAdrian Chadd };
227d11f81afSAdrian Chadd 
228d11f81afSAdrian Chadd /*
229d11f81afSAdrian Chadd  * This has to be run early, before the rest of the hardware is potentially
230d11f81afSAdrian Chadd  * probed/attached.
231d11f81afSAdrian Chadd  */
23253e1cbefSJohn Baldwin EARLY_DRIVER_MODULE(qcom_tcsr, simplebus, qcom_tcsr_driver, 0, 0,
233d11f81afSAdrian Chadd     BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
234d11f81afSAdrian Chadd SIMPLEBUS_PNP_INFO(compat_data);
235