1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 32 #include <sys/bus.h> 33 #include <sys/interrupt.h> 34 #include <sys/malloc.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/gpio.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 #include <vm/vm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/fdt/fdt_pinctrl.h> 51 52 #include <dev/gpio/gpiobusvar.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <dev/clk/clk.h> 57 #include <dev/hwreset/hwreset.h> 58 59 #include <dev/spibus/spi.h> 60 #include <dev/spibus/spibusvar.h> 61 #include "spibus_if.h" 62 63 #include <dev/qcom_qup/qcom_spi_var.h> 64 #include <dev/qcom_qup/qcom_qup_reg.h> 65 #include <dev/qcom_qup/qcom_spi_reg.h> 66 #include <dev/qcom_qup/qcom_spi_debug.h> 67 68 static struct ofw_compat_data compat_data[] = { 69 { "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 }, 70 { "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 }, 71 { "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 }, 72 { NULL, 0 } 73 }; 74 75 /* 76 * Flip the CS GPIO line either active or inactive. 77 * 78 * Actually listen to the CS polarity. 79 */ 80 static void 81 qcom_spi_set_chipsel(struct qcom_spi_softc *sc, int cs, bool active) 82 { 83 bool pinactive; 84 bool invert = !! (cs & SPIBUS_CS_HIGH); 85 86 cs = cs & ~SPIBUS_CS_HIGH; 87 88 if (sc->cs_pins[cs] == NULL) { 89 device_printf(sc->sc_dev, 90 "%s: cs=%u, active=%u, invert=%u, no gpio?\n", 91 __func__, cs, active, invert); 92 return; 93 } 94 95 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_CHIPSELECT, 96 "%s: cs=%u active=%u\n", __func__, cs, active); 97 98 /* 99 * Default rule here is CS is active low. 100 */ 101 if (active) 102 pinactive = false; 103 else 104 pinactive = true; 105 106 /* 107 * Invert the CS line if required. 108 */ 109 if (invert) 110 pinactive = !! pinactive; 111 112 gpio_pin_set_active(sc->cs_pins[cs], pinactive); 113 gpio_pin_is_active(sc->cs_pins[cs], &pinactive); 114 } 115 116 static void 117 qcom_spi_intr(void *arg) 118 { 119 struct qcom_spi_softc *sc = arg; 120 int ret; 121 122 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, "%s: called\n", __func__); 123 124 125 QCOM_SPI_LOCK(sc); 126 ret = qcom_spi_hw_interrupt_handle(sc); 127 if (ret != 0) { 128 device_printf(sc->sc_dev, 129 "ERROR: failed to read intr status\n"); 130 goto done; 131 } 132 133 /* 134 * Handle spurious interrupts outside of an actual 135 * transfer. 136 */ 137 if (sc->transfer.active == false) { 138 device_printf(sc->sc_dev, 139 "ERROR: spurious interrupt\n"); 140 qcom_spi_hw_ack_opmode(sc); 141 goto done; 142 } 143 144 /* Now, handle interrupts */ 145 if (sc->intr.error) { 146 sc->intr.error = false; 147 device_printf(sc->sc_dev, "ERROR: intr\n"); 148 } 149 150 if (sc->intr.do_rx) { 151 sc->intr.do_rx = false; 152 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 153 "%s: PIO_READ\n", __func__); 154 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 155 ret = qcom_spi_hw_read_pio_fifo(sc); 156 else 157 ret = qcom_spi_hw_read_pio_block(sc); 158 if (ret != 0) { 159 device_printf(sc->sc_dev, 160 "ERROR: qcom_spi_hw_read failed (%u)\n", ret); 161 goto done; 162 } 163 } 164 if (sc->intr.do_tx) { 165 sc->intr.do_tx = false; 166 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 167 "%s: PIO_WRITE\n", __func__); 168 /* 169 * For FIFO operations we do not do a write here, we did 170 * it at the beginning of the transfer. 171 * 172 * For BLOCK operations yes, we call the routine. 173 */ 174 175 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 176 ret = qcom_spi_hw_ack_write_pio_fifo(sc); 177 else 178 ret = qcom_spi_hw_write_pio_block(sc); 179 if (ret != 0) { 180 device_printf(sc->sc_dev, 181 "ERROR: qcom_spi_hw_write failed (%u)\n", ret); 182 goto done; 183 } 184 } 185 186 /* 187 * Do this last. We may actually have completed the 188 * transfer in the PIO receive path above and it will 189 * set the done flag here. 190 */ 191 if (sc->intr.done) { 192 sc->intr.done = false; 193 sc->transfer.done = true; 194 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 195 "%s: transfer done\n", __func__); 196 wakeup(sc); 197 } 198 199 done: 200 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 201 "%s: done\n", __func__); 202 QCOM_SPI_UNLOCK(sc); 203 } 204 205 static int 206 qcom_spi_probe(device_t dev) 207 { 208 209 if (!ofw_bus_status_okay(dev)) 210 return (ENXIO); 211 212 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 213 return (ENXIO); 214 215 device_set_desc(dev, "Qualcomm SPI Interface"); 216 return (BUS_PROBE_DEFAULT); 217 } 218 219 /* 220 * Allocate GPIOs if provided in the SPI controller block. 221 * 222 * Some devices will use GPIO lines for chip select. 223 * It's also quite annoying because some devices will want to use 224 * the hardware provided CS gating for say, the first chipselect block, 225 * and then use GPIOs for the later ones. 226 * 227 * So here we just assume for now that SPI index 0 uses the hardware 228 * lines, and >0 use GPIO lines. Revisit this if better hardware 229 * shows up. 230 * 231 * And finally, iterating over the cs-gpios list to allocate GPIOs 232 * doesn't actually tell us what the polarity is. For that we need 233 * to actually iterate over the list of child nodes and check what 234 * their properties are (and look for "spi-cs-high".) 235 */ 236 static void 237 qcom_spi_attach_gpios(struct qcom_spi_softc *sc) 238 { 239 phandle_t node; 240 int idx, err; 241 242 /* Allocate gpio pins for configured chip selects. */ 243 node = ofw_bus_get_node(sc->sc_dev); 244 for (idx = 0; idx < nitems(sc->cs_pins); idx++) { 245 err = gpio_pin_get_by_ofw_propidx(sc->sc_dev, node, 246 "cs-gpios", idx, &sc->cs_pins[idx]); 247 if (err == 0) { 248 err = gpio_pin_setflags(sc->cs_pins[idx], 249 GPIO_PIN_OUTPUT); 250 if (err != 0) { 251 device_printf(sc->sc_dev, 252 "error configuring gpio for" 253 " cs %u (%d)\n", idx, err); 254 } 255 /* 256 * We can't set this HIGH right now because 257 * we don't know if it needs to be set to 258 * high for inactive or low for inactive 259 * based on the child SPI device flags. 260 */ 261 #if 0 262 gpio_pin_set_active(sc->cs_pins[idx], 1); 263 gpio_pin_is_active(sc->cs_pins[idx], &tmp); 264 #endif 265 } else { 266 device_printf(sc->sc_dev, 267 "cannot configure gpio for chip select %u\n", idx); 268 sc->cs_pins[idx] = NULL; 269 } 270 } 271 } 272 273 static void 274 qcom_spi_sysctl_attach(struct qcom_spi_softc *sc) 275 { 276 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 277 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 278 279 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 280 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 281 "control debugging printfs"); 282 } 283 284 static int 285 qcom_spi_attach(device_t dev) 286 { 287 struct qcom_spi_softc *sc = device_get_softc(dev); 288 int rid, ret, i, val; 289 290 sc->sc_dev = dev; 291 292 /* 293 * Hardware version is stored in the ofw_compat_data table. 294 */ 295 sc->hw_version = 296 ofw_bus_search_compatible(dev, compat_data)->ocd_data; 297 298 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 299 300 rid = 0; 301 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 302 RF_ACTIVE); 303 if (!sc->sc_mem_res) { 304 device_printf(dev, "ERROR: Could not map memory\n"); 305 ret = ENXIO; 306 goto error; 307 } 308 309 rid = 0; 310 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 311 RF_ACTIVE | RF_SHAREABLE); 312 if (!sc->sc_irq_res) { 313 device_printf(dev, "ERROR: Could not map interrupt\n"); 314 ret = ENXIO; 315 goto error; 316 } 317 318 ret = bus_setup_intr(dev, sc->sc_irq_res, 319 INTR_TYPE_MISC | INTR_MPSAFE, 320 NULL, qcom_spi_intr, sc, &sc->sc_irq_h); 321 if (ret != 0) { 322 device_printf(dev, "ERROR: could not configure interrupt " 323 "(%d)\n", 324 ret); 325 goto error; 326 } 327 328 qcom_spi_attach_gpios(sc); 329 330 ret = clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core); 331 if (ret != 0) { 332 device_printf(dev, "ERROR: could not get %s clock (%d)\n", 333 "core", ret); 334 goto error; 335 } 336 ret = clk_get_by_ofw_name(dev, 0, "iface", &sc->clk_iface); 337 if (ret != 0) { 338 device_printf(dev, "ERROR: could not get %s clock (%d)\n", 339 "iface", ret); 340 goto error; 341 } 342 343 /* Bring up initial clocks if they're off */ 344 ret = clk_enable(sc->clk_core); 345 if (ret != 0) { 346 device_printf(dev, "ERROR: couldn't enable core clock (%u)\n", 347 ret); 348 goto error; 349 } 350 ret = clk_enable(sc->clk_iface); 351 if (ret != 0) { 352 device_printf(dev, "ERROR: couldn't enable iface clock (%u)\n", 353 ret); 354 goto error; 355 } 356 357 /* 358 * Read optional spi-max-frequency 359 */ 360 if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency", 361 &val, sizeof(val)) > 0) 362 sc->config.max_frequency = val; 363 else 364 sc->config.max_frequency = SPI_MAX_RATE; 365 366 /* 367 * Read optional cs-select 368 */ 369 if (OF_getencprop(ofw_bus_get_node(dev), "cs-select", 370 &val, sizeof(val)) > 0) 371 sc->config.cs_select = val; 372 else 373 sc->config.cs_select = 0; 374 375 /* 376 * Read optional num-cs 377 */ 378 if (OF_getencprop(ofw_bus_get_node(dev), "num-cs", 379 &val, sizeof(val)) > 0) 380 sc->config.num_cs = val; 381 else 382 sc->config.num_cs = SPI_NUM_CHIPSELECTS; 383 384 ret = fdt_pinctrl_configure_by_name(dev, "default"); 385 if (ret != 0) { 386 device_printf(dev, 387 "ERROR: could not configure default pinmux\n"); 388 goto error; 389 } 390 391 ret = qcom_spi_hw_read_controller_transfer_sizes(sc); 392 if (ret != 0) { 393 device_printf(dev, "ERROR: Could not read transfer config\n"); 394 goto error; 395 } 396 397 398 device_printf(dev, "BLOCK: input=%u bytes, output=%u bytes\n", 399 sc->config.input_block_size, 400 sc->config.output_block_size); 401 device_printf(dev, "FIFO: input=%u bytes, output=%u bytes\n", 402 sc->config.input_fifo_size, 403 sc->config.output_fifo_size); 404 405 /* QUP config */ 406 QCOM_SPI_LOCK(sc); 407 ret = qcom_spi_hw_qup_init_locked(sc); 408 if (ret != 0) { 409 device_printf(dev, "ERROR: QUP init failed (%d)\n", ret); 410 QCOM_SPI_UNLOCK(sc); 411 goto error; 412 } 413 414 /* Initial SPI config */ 415 ret = qcom_spi_hw_spi_init_locked(sc); 416 if (ret != 0) { 417 device_printf(dev, "ERROR: SPI init failed (%d)\n", ret); 418 QCOM_SPI_UNLOCK(sc); 419 goto error; 420 } 421 QCOM_SPI_UNLOCK(sc); 422 423 sc->spibus = device_add_child(dev, "spibus", -1); 424 425 /* We're done, so shut down the interface clock for now */ 426 device_printf(dev, "DONE: shutting down interface clock for now\n"); 427 clk_disable(sc->clk_iface); 428 429 /* Register for debug sysctl */ 430 qcom_spi_sysctl_attach(sc); 431 432 bus_attach_children(dev); 433 return (0); 434 error: 435 if (sc->sc_irq_h) 436 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 437 if (sc->sc_mem_res) 438 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 439 if (sc->sc_irq_res) 440 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 441 if (sc->clk_core) { 442 clk_disable(sc->clk_core); 443 clk_release(sc->clk_core); 444 } 445 if (sc->clk_iface) { 446 clk_disable(sc->clk_iface); 447 clk_release(sc->clk_iface); 448 } 449 for (i = 0; i < CS_MAX; i++) { 450 if (sc->cs_pins[i] != NULL) 451 gpio_pin_release(sc->cs_pins[i]); 452 } 453 mtx_destroy(&sc->sc_mtx); 454 return (ret); 455 } 456 457 /* 458 * Do a PIO transfer. 459 * 460 * Note that right now the TX/RX lens need to match, I'm not doing 461 * dummy reads / dummy writes as required if they're not the same 462 * size. The QUP hardware supports doing multi-phase transactions 463 * where the FIFO isn't engaged for transmit or receive, but it's 464 * not yet being done here. 465 */ 466 static int 467 qcom_spi_transfer_pio_block(struct qcom_spi_softc *sc, int mode, 468 char *tx_buf, int tx_len, char *rx_buf, int rx_len) 469 { 470 int ret = 0; 471 472 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, "%s: start\n", 473 __func__); 474 475 if (rx_len != tx_len) { 476 device_printf(sc->sc_dev, 477 "ERROR: tx/rx len doesn't match (%d/%d)\n", 478 tx_len, rx_len); 479 return (ENXIO); 480 } 481 482 QCOM_SPI_ASSERT_LOCKED(sc); 483 484 /* 485 * Make initial choices for transfer configuration. 486 */ 487 ret = qcom_spi_hw_setup_transfer_selection(sc, tx_len); 488 if (ret != 0) { 489 device_printf(sc->sc_dev, 490 "ERROR: failed to setup transfer selection (%d)\n", 491 ret); 492 return (ret); 493 } 494 495 /* Now set suitable buffer/lengths */ 496 sc->transfer.tx_buf = tx_buf; 497 sc->transfer.tx_len = tx_len; 498 sc->transfer.rx_buf = rx_buf; 499 sc->transfer.rx_len = rx_len; 500 sc->transfer.done = false; 501 sc->transfer.active = false; 502 503 /* 504 * Loop until the full transfer set is done. 505 * 506 * qcom_spi_hw_setup_current_transfer() will take care of 507 * setting a maximum transfer size for the hardware and choose 508 * a suitable operating mode. 509 */ 510 while (sc->transfer.tx_offset < sc->transfer.tx_len) { 511 /* 512 * Set transfer to false early; this covers 513 * it also finishing a sub-transfer and we're 514 * about the put the block into RESET state before 515 * starting a new transfer. 516 */ 517 sc->transfer.active = false; 518 519 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 520 "%s: tx=%d of %d bytes, rx=%d of %d bytes\n", 521 __func__, 522 sc->transfer.tx_offset, sc->transfer.tx_len, 523 sc->transfer.rx_offset, sc->transfer.rx_len); 524 525 /* 526 * Set state to RESET before doing anything. 527 * 528 * Otherwise the second sub-transfer that we queue up 529 * will generate interrupts immediately when we start 530 * configuring it here and it'll start underflowing. 531 */ 532 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 533 if (ret != 0) { 534 device_printf(sc->sc_dev, 535 "ERROR: can't transition to RESET (%u)\n", ret); 536 goto done; 537 } 538 /* blank interrupt state; we'll do a RESET below */ 539 bzero(&sc->intr, sizeof(sc->intr)); 540 sc->transfer.done = false; 541 542 /* 543 * Configure what the transfer configuration for this 544 * sub-transfer will be. 545 */ 546 ret = qcom_spi_hw_setup_current_transfer(sc); 547 if (ret != 0) { 548 device_printf(sc->sc_dev, 549 "ERROR: failed to setup sub transfer (%d)\n", 550 ret); 551 goto done; 552 } 553 554 /* 555 * For now since we're configuring up PIO, we only setup 556 * the PIO transfer size. 557 */ 558 ret = qcom_spi_hw_setup_pio_transfer_cnt(sc); 559 if (ret != 0) { 560 device_printf(sc->sc_dev, 561 "ERROR: qcom_spi_hw_setup_pio_transfer_cnt failed" 562 " (%u)\n", ret); 563 goto done; 564 } 565 566 #if 0 567 /* 568 * This is what we'd do to setup the block transfer sizes. 569 */ 570 ret = qcom_spi_hw_setup_block_transfer_cnt(sc); 571 if (ret != 0) { 572 device_printf(sc->sc_dev, 573 "ERROR: qcom_spi_hw_setup_block_transfer_cnt failed" 574 " (%u)\n", ret); 575 goto done; 576 } 577 #endif 578 579 ret = qcom_spi_hw_setup_io_modes(sc); 580 if (ret != 0) { 581 device_printf(sc->sc_dev, 582 "ERROR: qcom_spi_hw_setup_io_modes failed" 583 " (%u)\n", ret); 584 goto done; 585 } 586 587 ret = qcom_spi_hw_setup_spi_io_clock_polarity(sc, 588 !! (mode & SPIBUS_MODE_CPOL)); 589 if (ret != 0) { 590 device_printf(sc->sc_dev, 591 "ERROR: qcom_spi_hw_setup_spi_io_clock_polarity" 592 " failed (%u)\n", ret); 593 goto done; 594 } 595 596 ret = qcom_spi_hw_setup_spi_config(sc, sc->state.frequency, 597 !! (mode & SPIBUS_MODE_CPHA)); 598 if (ret != 0) { 599 device_printf(sc->sc_dev, 600 "ERROR: qcom_spi_hw_setup_spi_config failed" 601 " (%u)\n", ret); 602 goto done; 603 } 604 605 ret = qcom_spi_hw_setup_qup_config(sc, !! (tx_len > 0), 606 !! (rx_len > 0)); 607 if (ret != 0) { 608 device_printf(sc->sc_dev, 609 "ERROR: qcom_spi_hw_setup_qup_config failed" 610 " (%u)\n", ret); 611 goto done; 612 } 613 614 ret = qcom_spi_hw_setup_operational_mask(sc); 615 if (ret != 0) { 616 device_printf(sc->sc_dev, 617 "ERROR: qcom_spi_hw_setup_operational_mask failed" 618 " (%u)\n", ret); 619 goto done; 620 } 621 622 /* 623 * Setup is done; reset the controller and start the PIO 624 * write. 625 */ 626 627 /* 628 * Set state to RUN; we may start getting interrupts that 629 * are valid and we need to handle. 630 */ 631 sc->transfer.active = true; 632 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN); 633 if (ret != 0) { 634 device_printf(sc->sc_dev, 635 "ERROR: can't transition to RUN (%u)\n", ret); 636 goto done; 637 } 638 639 /* 640 * Set state to PAUSE 641 */ 642 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_PAUSE); 643 if (ret != 0) { 644 device_printf(sc->sc_dev, 645 "ERROR: can't transition to PAUSE (%u)\n", ret); 646 goto done; 647 } 648 649 /* 650 * If FIFO mode, write data now. Else, we'll get an 651 * interrupt when it's time to populate more data 652 * in BLOCK mode. 653 */ 654 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 655 ret = qcom_spi_hw_write_pio_fifo(sc); 656 else 657 ret = qcom_spi_hw_write_pio_block(sc); 658 if (ret != 0) { 659 device_printf(sc->sc_dev, 660 "ERROR: qcom_spi_hw_write failed (%u)\n", ret); 661 goto done; 662 } 663 664 /* 665 * Set state to RUN 666 */ 667 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN); 668 if (ret != 0) { 669 device_printf(sc->sc_dev, 670 "ERROR: can't transition to RUN (%u)\n", ret); 671 goto done; 672 } 673 674 /* 675 * Wait for an interrupt notification (which will 676 * continue to drive the state machine for this 677 * sub-transfer) or timeout. 678 */ 679 ret = 0; 680 while (ret == 0 && sc->transfer.done == false) { 681 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 682 "%s: waiting\n", __func__); 683 ret = msleep(sc, &sc->sc_mtx, 0, "qcom_spi", 0); 684 } 685 } 686 done: 687 /* 688 * Complete; put controller into reset. 689 * 690 * Don't worry about return value here; if we errored out above then 691 * we want to communicate that value to the caller. 692 */ 693 (void) qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 694 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 695 "%s: completed\n", __func__); 696 697 /* 698 * Blank the transfer state so we don't use an old transfer 699 * state in a subsequent interrupt. 700 */ 701 (void) qcom_spi_hw_complete_transfer(sc); 702 sc->transfer.active = false; 703 704 return (ret); 705 } 706 707 static int 708 qcom_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 709 { 710 struct qcom_spi_softc *sc = device_get_softc(dev); 711 uint32_t cs_val, mode_val, clock_val; 712 uint32_t ret = 0; 713 714 spibus_get_cs(child, &cs_val); 715 spibus_get_clock(child, &clock_val); 716 spibus_get_mode(child, &mode_val); 717 718 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 719 "%s: called; child cs=0x%08x, clock=%u, mode=0x%08x, " 720 "cmd=%u/%u bytes; data=%u/%u bytes\n", 721 __func__, 722 cs_val, 723 clock_val, 724 mode_val, 725 cmd->tx_cmd_sz, cmd->rx_cmd_sz, 726 cmd->tx_data_sz, cmd->rx_data_sz); 727 728 QCOM_SPI_LOCK(sc); 729 730 /* 731 * wait until the controller isn't busy 732 */ 733 while (sc->sc_busy == true) 734 mtx_sleep(sc, &sc->sc_mtx, 0, "qcom_spi_wait", 0); 735 736 /* 737 * it's ours now! 738 */ 739 sc->sc_busy = true; 740 741 sc->state.cs_high = !! (cs_val & SPIBUS_CS_HIGH); 742 sc->state.frequency = clock_val; 743 744 /* 745 * We can't set the clock frequency and enable it 746 * with the driver lock held, as the SPI lock is non-sleepable 747 * and the clock framework is sleepable. 748 * 749 * No other transaction is going on right now, so we can 750 * unlock here and do the clock related work. 751 */ 752 QCOM_SPI_UNLOCK(sc); 753 754 /* 755 * Set the clock frequency 756 */ 757 ret = clk_set_freq(sc->clk_iface, sc->state.frequency, 0); 758 if (ret != 0) { 759 device_printf(sc->sc_dev, 760 "ERROR: failed to set frequency to %u\n", 761 sc->state.frequency); 762 goto done2; 763 } 764 clk_enable(sc->clk_iface); 765 766 QCOM_SPI_LOCK(sc); 767 768 /* 769 * Set state to RESET 770 */ 771 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 772 if (ret != 0) { 773 device_printf(sc->sc_dev, 774 "ERROR: can't transition to RESET (%u)\n", ret); 775 goto done; 776 } 777 778 /* Assert hardware CS if set, else GPIO */ 779 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL) 780 qcom_spi_hw_spi_cs_force(sc, cs_val & SPIBUS_CS_HIGH, true); 781 else 782 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, true); 783 784 /* 785 * cmd buffer transfer 786 */ 787 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_cmd, 788 cmd->tx_cmd_sz, cmd->rx_cmd, cmd->rx_cmd_sz); 789 if (ret != 0) { 790 device_printf(sc->sc_dev, 791 "ERROR: failed to transfer cmd payload (%u)\n", ret); 792 goto done; 793 } 794 795 /* 796 * data buffer transfer 797 */ 798 if (cmd->tx_data_sz > 0) { 799 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_data, 800 cmd->tx_data_sz, cmd->rx_data, cmd->rx_data_sz); 801 if (ret != 0) { 802 device_printf(sc->sc_dev, 803 "ERROR: failed to transfer data payload (%u)\n", 804 ret); 805 goto done; 806 } 807 } 808 809 done: 810 /* De-assert GPIO/CS */ 811 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL) 812 qcom_spi_hw_spi_cs_force(sc, cs_val & ~SPIBUS_CS_HIGH, false); 813 else 814 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, false); 815 816 /* 817 * Similarly to when we enabled the clock, we can't hold it here 818 * across a clk API as that's a sleep lock and we're non-sleepable. 819 * So instead we unlock/relock here, but we still hold the busy flag. 820 */ 821 822 QCOM_SPI_UNLOCK(sc); 823 clk_disable(sc->clk_iface); 824 QCOM_SPI_LOCK(sc); 825 done2: 826 /* 827 * We're done; so mark the bus as not busy and wakeup 828 * the next caller. 829 */ 830 sc->sc_busy = false; 831 wakeup_one(sc); 832 QCOM_SPI_UNLOCK(sc); 833 return (ret); 834 } 835 836 static int 837 qcom_spi_detach(device_t dev) 838 { 839 struct qcom_spi_softc *sc = device_get_softc(dev); 840 int i; 841 842 bus_generic_detach(sc->sc_dev); 843 if (sc->spibus != NULL) 844 device_delete_child(dev, sc->spibus); 845 846 if (sc->sc_irq_h) 847 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 848 849 if (sc->clk_iface) { 850 clk_disable(sc->clk_iface); 851 clk_release(sc->clk_iface); 852 } 853 if (sc->clk_core) { 854 clk_disable(sc->clk_core); 855 clk_release(sc->clk_core); 856 } 857 858 for (i = 0; i < CS_MAX; i++) { 859 if (sc->cs_pins[i] != NULL) 860 gpio_pin_release(sc->cs_pins[i]); 861 } 862 863 if (sc->sc_mem_res) 864 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 865 if (sc->sc_irq_res) 866 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 867 868 mtx_destroy(&sc->sc_mtx); 869 870 return (0); 871 } 872 873 static phandle_t 874 qcom_spi_get_node(device_t bus, device_t dev) 875 { 876 877 return ofw_bus_get_node(bus); 878 } 879 880 881 static device_method_t qcom_spi_methods[] = { 882 /* Device interface */ 883 DEVMETHOD(device_probe, qcom_spi_probe), 884 DEVMETHOD(device_attach, qcom_spi_attach), 885 DEVMETHOD(device_detach, qcom_spi_detach), 886 /* TODO: suspend */ 887 /* TODO: resume */ 888 889 DEVMETHOD(spibus_transfer, qcom_spi_transfer), 890 891 /* ofw_bus_if */ 892 DEVMETHOD(ofw_bus_get_node, qcom_spi_get_node), 893 894 DEVMETHOD_END 895 }; 896 897 static driver_t qcom_spi_driver = { 898 "qcom_spi", 899 qcom_spi_methods, 900 sizeof(struct qcom_spi_softc), 901 }; 902 903 DRIVER_MODULE(qcom_spi, simplebus, qcom_spi_driver, 0, 0); 904 DRIVER_MODULE(ofw_spibus, qcom_spi, ofw_spibus_driver, 0, 0); 905 MODULE_DEPEND(qcom_spi, ofw_spibus, 1, 1, 1); 906 SIMPLEBUS_PNP_INFO(compat_data); 907