xref: /freebsd/sys/dev/qcom_mdio/qcom_mdio_ipq4018_reg.h (revision 29332c0dcee1e80c9fb871e06c3160bd5deb1b44)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef	__QCOM_MDIO_IPQ4018_REG_H__
30 #define	__QCOM_MDIO_IPQ4018_REG_H__
31 
32 #define	QCOM_IPQ4018_MDIO_REG_ADDR			0x44
33 #define	QCOM_IPQ4018_MDIO_REG_WRITE			0x48
34 #define	QCOM_IPQ4018_MDIO_REG_READ			0x4c
35 #define	QCOM_IPQ4018_MDIO_REG_CMD			0x50
36 #define		QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_BUSY	(1U << 16)
37 #define		QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_START	(1U << 8)
38 #define		QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_READ	0
39 #define		QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_CODE_WRITE	1
40 
41 #define	QCOM_IPQ4018_MDIO_SLEEP_COUNT			100
42 #define	QCOM_IPQ4018_MDIO_SLEEP				10 /* uSec */
43 
44 #endif	/* __QCOM_MDIO_IPQ4018_REG_H__ */
45