1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef __QCOM_GCC_VAR_H__ 29 #define __QCOM_GCC_VAR_H__ 30 31 typedef enum { 32 QCOM_GCC_CHIPSET_NONE = 0, 33 QCOM_GCC_CHIPSET_IPQ4018 = 1, 34 } qcom_gcc_chipset_t; 35 36 struct qcom_gcc_reset_entry { 37 uint32_t reg; 38 uint32_t bit; 39 }; 40 41 struct qcom_gcc_hw_callbacks { 42 /* Reset block */ 43 int (*hw_reset_assert)(device_t, intptr_t, bool); 44 int (*hw_reset_is_asserted)(device_t, intptr_t, bool *); 45 46 /* Clock block */ 47 }; 48 49 struct qcom_gcc_softc { 50 device_t dev; 51 int reg_rid; 52 struct resource *reg; 53 struct mtx mtx; 54 struct clkdom *clkdom; 55 qcom_gcc_chipset_t sc_chipset; 56 struct qcom_gcc_hw_callbacks sc_cb; 57 }; 58 59 /* 60 * reset block 61 */ 62 extern int qcom_gcc_hwreset_assert(device_t dev, intptr_t id, 63 bool reset); 64 extern int qcom_gcc_hwreset_is_asserted(device_t dev, intptr_t id, 65 bool *reset); 66 67 /* 68 * clock block 69 */ 70 extern int qcom_gcc_clock_read(device_t dev, bus_addr_t addr, 71 uint32_t *val); 72 extern int qcom_gcc_clock_write(device_t dev, bus_addr_t addr, 73 uint32_t val); 74 extern int qcom_gcc_clock_modify(device_t dev, bus_addr_t addr, 75 uint32_t clear_mask, uint32_t set_mask); 76 extern void qcom_gcc_clock_setup(struct qcom_gcc_softc *sc); 77 extern void qcom_gcc_clock_lock(device_t dev); 78 extern void qcom_gcc_clock_unlock(device_t dev); 79 80 #endif /* __QCOM_GCC_VAR_H__ */ 81