1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2025, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Driver for Qualcomm clock/reset trees */ 29 30 #include <sys/param.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/module.h> 34 #include <sys/sglist.h> 35 #include <sys/random.h> 36 #include <sys/stdatomic.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <sys/bus.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/hwreset/hwreset.h> 48 49 #include "clkdev_if.h" 50 #include "hwreset_if.h" 51 52 #include "qcom_gcc_var.h" 53 #include "qcom_gcc_ipq4018.h" 54 55 static int qcom_gcc_modevent(module_t, int, void *); 56 57 static int qcom_gcc_probe(device_t); 58 static int qcom_gcc_attach(device_t); 59 static int qcom_gcc_detach(device_t); 60 61 struct qcom_gcc_chipset_list_entry { 62 const char *ofw; 63 const char *desc; 64 qcom_gcc_chipset_t chipset; 65 }; 66 67 static struct qcom_gcc_chipset_list_entry qcom_gcc_chipset_list[] = { 68 { "qcom,gcc-ipq4019", "Qualcomm IPQ4018 Clock/Reset Controller", 69 QCOM_GCC_CHIPSET_IPQ4018 }, 70 { NULL, NULL, 0 }, 71 }; 72 73 static int 74 qcom_gcc_modevent(module_t mod, int type, void *unused) 75 { 76 int error; 77 78 switch (type) { 79 case MOD_LOAD: 80 case MOD_QUIESCE: 81 case MOD_UNLOAD: 82 case MOD_SHUTDOWN: 83 error = 0; 84 break; 85 default: 86 error = EOPNOTSUPP; 87 break; 88 } 89 90 return (error); 91 } 92 93 static int 94 qcom_gcc_probe(device_t dev) 95 { 96 struct qcom_gcc_softc *sc; 97 int i; 98 99 sc = device_get_softc(dev); 100 101 if (! ofw_bus_status_okay(dev)) 102 return (ENXIO); 103 104 for (i = 0; qcom_gcc_chipset_list[i].ofw != NULL; i++) { 105 const struct qcom_gcc_chipset_list_entry *ce; 106 107 ce = &qcom_gcc_chipset_list[i]; 108 if (ofw_bus_is_compatible(dev, ce->ofw) == 0) 109 continue; 110 device_set_desc(dev, ce->desc); 111 sc->sc_chipset = ce->chipset; 112 return (0); 113 } 114 115 return (ENXIO); 116 } 117 118 static int 119 qcom_gcc_attach(device_t dev) 120 { 121 struct qcom_gcc_softc *sc; 122 size_t mem_sz; 123 124 sc = device_get_softc(dev); 125 126 /* Found a compatible device! */ 127 sc->dev = dev; 128 129 /* 130 * Setup the hardware callbacks, before any further initialisation 131 * is performed. 132 */ 133 switch (sc->sc_chipset) { 134 case QCOM_GCC_CHIPSET_IPQ4018: 135 qcom_gcc_ipq4018_hwreset_init(sc); 136 mem_sz = 0x60000; 137 break; 138 case QCOM_GCC_CHIPSET_NONE: 139 device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); 140 return (ENXIO); 141 } 142 143 sc->reg_rid = 0; 144 145 sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, 146 &sc->reg_rid, mem_sz, RF_ACTIVE); 147 if (sc->reg == NULL) { 148 device_printf(dev, "Couldn't allocate memory resource!\n"); 149 return (ENXIO); 150 } 151 152 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 153 154 /* 155 * Register as a reset provider. 156 */ 157 hwreset_register_ofw_provider(dev); 158 159 /* 160 * Setup and register as a clock provider. 161 */ 162 switch (sc->sc_chipset) { 163 case QCOM_GCC_CHIPSET_IPQ4018: 164 qcom_gcc_ipq4018_clock_setup(sc); 165 break; 166 case QCOM_GCC_CHIPSET_NONE: 167 device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); 168 return (ENXIO); 169 } 170 171 return (0); 172 } 173 174 static int 175 qcom_gcc_detach(device_t dev) 176 { 177 struct qcom_gcc_softc *sc; 178 179 sc = device_get_softc(dev); 180 181 /* 182 * TBD - deregistering reset/clock resources. 183 */ 184 185 if (sc->reg != NULL) { 186 bus_release_resource(sc->dev, SYS_RES_MEMORY, 187 sc->reg_rid, sc->reg); 188 } 189 return (0); 190 } 191 192 static device_method_t qcom_gcc_methods[] = { 193 /* Device methods. */ 194 DEVMETHOD(device_probe, qcom_gcc_probe), 195 DEVMETHOD(device_attach, qcom_gcc_attach), 196 DEVMETHOD(device_detach, qcom_gcc_detach), 197 198 /* Reset interface */ 199 DEVMETHOD(hwreset_assert, qcom_gcc_hwreset_assert), 200 DEVMETHOD(hwreset_is_asserted, qcom_gcc_hwreset_is_asserted), 201 202 /* Clock interface */ 203 DEVMETHOD(clkdev_read_4, qcom_gcc_clock_read), 204 DEVMETHOD(clkdev_write_4, qcom_gcc_clock_write), 205 DEVMETHOD(clkdev_modify_4, qcom_gcc_clock_modify), 206 DEVMETHOD(clkdev_device_lock, qcom_gcc_clock_lock), 207 DEVMETHOD(clkdev_device_unlock, qcom_gcc_clock_unlock), 208 209 DEVMETHOD_END 210 }; 211 212 static driver_t qcom_gcc_driver = { 213 "qcom_gcc", 214 qcom_gcc_methods, 215 sizeof(struct qcom_gcc_softc) 216 }; 217 218 EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 219 qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 220 EARLY_DRIVER_MODULE(qcom_gcc, ofwbus, qcom_gcc_driver, 221 qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 222 MODULE_VERSION(qcom_gcc, 1); 223