xref: /freebsd/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c (revision 069ac18495ad8fde2748bc94b0f80a50250bb01d)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice unmodified, this list of conditions, and the following
11  *    disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 /* Driver for Qualcomm IPQ4018 clock and reset device */
29 
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/malloc.h>
33 #include <sys/module.h>
34 #include <sys/sglist.h>
35 #include <sys/random.h>
36 #include <sys/stdatomic.h>
37 #include <sys/mutex.h>
38 
39 #include <machine/bus.h>
40 #include <machine/resource.h>
41 #include <sys/bus.h>
42 
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 
47 #include <dev/extres/hwreset/hwreset.h>
48 
49 #include "hwreset_if.h"
50 
51 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
52 
53 #include "qcom_gcc_ipq4018_var.h"
54 
55 
56 static const struct qcom_gcc_ipq4018_reset_entry gcc_ipq4019_reset_list[] = {
57 	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
58 	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
59 	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
60 	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
61 	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
62 	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
63 	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
64 	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
65 	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
66 	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
67 	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
68 	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
69 	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
70 	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
71 	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
72 	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
73 	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
74 	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
75 	[PCIE_AHB_ARES] = { 0x1d010, 10 },
76 	[PCIE_PWR_ARES] = { 0x1d010, 9 },
77 	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
78 	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
79 	[PCIE_PHY_ARES] = { 0x1d010, 6 },
80 	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
81 	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
82 	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
83 	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
84 	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
85 	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
86 	[ESS_RESET] = { 0x12008, 0},
87 	[GCC_BLSP1_BCR] = {0x01000, 0},
88 	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
89 	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
90 	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
91 	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
92 	[GCC_BIMC_BCR] = {0x04000, 0},
93 	[GCC_TLMM_BCR] = {0x05000, 0},
94 	[GCC_IMEM_BCR] = {0x0E000, 0},
95 	[GCC_ESS_BCR] = {0x12008, 0},
96 	[GCC_PRNG_BCR] = {0x13000, 0},
97 	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
98 	[GCC_CRYPTO_BCR] = {0x16000, 0},
99 	[GCC_SDCC1_BCR] = {0x18000, 0},
100 	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
101 	[GCC_AUDIO_BCR] = {0x1B008, 0},
102 	[GCC_QPIC_BCR] = {0x1C000, 0},
103 	[GCC_PCIE_BCR] = {0x1D000, 0},
104 	[GCC_USB2_BCR] = {0x1E008, 0},
105 	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
106 	[GCC_USB3_BCR] = {0x1E024, 0},
107 	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
108 	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
109 	[GCC_PCNOC_BCR] = {0x2102C, 0},
110 	[GCC_DCD_BCR] = {0x21038, 0},
111 	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
112 	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
113 	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
114 	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
115 	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
116 	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
117 	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
118 	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
119 	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
120 	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
121 	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
122 	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
123 	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
124 	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
125 	[GCC_TCSR_BCR] = {0x22000, 0},
126 	[GCC_MPM_BCR] = {0x24000, 0},
127 	[GCC_SPDM_BCR] = {0x25000, 0},
128 };
129 
130 int
131 qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset)
132 {
133 	struct qcom_gcc_ipq4018_softc *sc;
134 	uint32_t reg;
135 
136 	sc = device_get_softc(dev);
137 
138 	if (id > nitems(gcc_ipq4019_reset_list)) {
139 		device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
140 		return (EINVAL);
141 	}
142 
143 	mtx_lock(&sc->mtx);
144 	reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
145 	if (reset)
146 		reg |= (1U << gcc_ipq4019_reset_list[id].bit);
147 	else
148 		reg &= ~(1U << gcc_ipq4019_reset_list[id].bit);
149 	bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);
150 	mtx_unlock(&sc->mtx);
151 	return (0);
152 }
153 
154 int
155 qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)
156 {
157 	struct qcom_gcc_ipq4018_softc *sc;
158 	uint32_t reg;
159 
160 	sc = device_get_softc(dev);
161 
162 	if (id > nitems(gcc_ipq4019_reset_list)) {
163 		device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
164 		return (EINVAL);
165 	}
166 	mtx_lock(&sc->mtx);
167 	reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
168 	if (reg & ((1U << gcc_ipq4019_reset_list[id].bit)))
169 		*reset = true;
170 	else
171 		*reset = false;
172 	mtx_unlock(&sc->mtx);
173 
174 	device_printf(dev, "called; id=%d\n", id);
175 	return (0);
176 }
177 
178