1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Driver for Qualcomm IPQ4018 clock and reset device */ 29 30 #include <sys/param.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/module.h> 34 #include <sys/sglist.h> 35 #include <sys/random.h> 36 #include <sys/stdatomic.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <sys/bus.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/clk/clk_div.h> 48 #include <dev/clk/clk_fixed.h> 49 #include <dev/clk/clk_mux.h> 50 #include <dev/clk/clk_link.h> 51 52 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 53 54 #include <dev/qcom_clk/qcom_clk_freqtbl.h> 55 #include <dev/qcom_clk/qcom_clk_fepll.h> 56 #include <dev/qcom_clk/qcom_clk_fdiv.h> 57 #include <dev/qcom_clk/qcom_clk_apssdiv.h> 58 #include <dev/qcom_clk/qcom_clk_rcg2.h> 59 #include <dev/qcom_clk/qcom_clk_branch2.h> 60 #include <dev/qcom_clk/qcom_clk_ro_div.h> 61 62 #include "qcom_gcc_ipq4018_var.h" 63 64 65 /* Fixed rate clock. */ 66 #define F_RATE(_id, cname, _freq) \ 67 { \ 68 .clkdef.id = _id, \ 69 .clkdef.name = cname, \ 70 .clkdef.parent_names = NULL, \ 71 .clkdef.parent_cnt = 0, \ 72 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 73 .freq = _freq, \ 74 } 75 76 /* Linked clock. */ 77 #define F_LINK(_id, _cname) \ 78 { \ 79 .clkdef.id = _id, \ 80 .clkdef.name = _cname, \ 81 .clkdef.parent_names = NULL, \ 82 .clkdef.parent_cnt = 0, \ 83 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 84 } 85 86 87 /* FEPLL clock */ 88 #define F_FEPLL(_id, _cname, _parent, _reg, _fs, _fw, _rs, _rw) \ 89 { \ 90 .clkdef.id = _id, \ 91 .clkdef.name = _cname, \ 92 .clkdef.parent_names = (const char *[]){_parent}, \ 93 .clkdef.parent_cnt = 1, \ 94 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 95 .offset = _reg, \ 96 .fdbkdiv_shift = _fs, \ 97 .fdbkdiv_width = _fw, \ 98 .refclkdiv_shift = _rs, \ 99 .refclkdiv_width = _rw, \ 100 } 101 102 /* Fixed divisor clock */ 103 #define F_FDIV(_id, _cname, _parent, _divisor) \ 104 { \ 105 .clkdef.id = _id, \ 106 .clkdef.name = _cname, \ 107 .clkdef.parent_names = (const char *[]){_parent}, \ 108 .clkdef.parent_cnt = 1, \ 109 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 110 .divisor = _divisor, \ 111 } 112 113 /* APSS DIV clock */ 114 #define F_APSSDIV(_id, _cname, _parent, _doffset, _dshift, _dwidth, \ 115 _eoffset, _eshift, _freqtbl) \ 116 { \ 117 .clkdef.id = _id, \ 118 .clkdef.name = _cname, \ 119 .clkdef.parent_names = (const char *[]){_parent}, \ 120 .clkdef.parent_cnt = 1, \ 121 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 122 .div_offset = _doffset, \ 123 .div_width = _dwidth, \ 124 .div_shift = _dshift, \ 125 .enable_offset = _eoffset, \ 126 .enable_shift = _eshift, \ 127 .freq_tbl = _freqtbl, \ 128 } 129 130 /* read-only div table */ 131 #define F_RO_DIV(_id, _cname, _parent, _offset, _shift, _width, _tbl) \ 132 { \ 133 .clkdef.id = _id, \ 134 .clkdef.name = _cname, \ 135 .clkdef.parent_names = (const char *[]){_parent}, \ 136 .clkdef.parent_cnt = 1, \ 137 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 138 .offset = _offset, \ 139 .width = _width, \ 140 .shift = _shift, \ 141 .div_tbl = _tbl, \ 142 } 143 144 /* RCG2 clock */ 145 #define F_RCG2(_id, _cname, _parents, _rcgr, _hid_width, _mnd_width, \ 146 _safe_src_idx, _safe_pre_parent_idx, _cfg_offset, _flags, \ 147 _freq_tbl) \ 148 { \ 149 .clkdef.id = _id, \ 150 .clkdef.name = _cname, \ 151 .clkdef.parent_names = _parents, \ 152 .clkdef.parent_cnt = nitems(_parents), \ 153 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 154 .cmd_rcgr = _rcgr, \ 155 .hid_width = _hid_width, \ 156 .mnd_width = _mnd_width, \ 157 .safe_src_idx = _safe_src_idx, \ 158 .flags= _flags, \ 159 .safe_pre_parent_idx = _safe_pre_parent_idx, \ 160 .freq_tbl = _freq_tbl, \ 161 } 162 163 /* branch2 gate nodes */ 164 #define F_BRANCH2(_id, _cname, _parent, _eo, _es, _hr, _hs, _haltreg, \ 165 _type, _voted, _flags) \ 166 { \ 167 .clkdef.id = _id, \ 168 .clkdef.name = _cname, \ 169 .clkdef.parent_names = (const char *[]){_parent}, \ 170 .clkdef.parent_cnt = 1, \ 171 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 172 .enable_offset = _eo, \ 173 .enable_shift = _es, \ 174 .hwcg_reg = _hr, \ 175 .hwcg_bit = _hs, \ 176 .halt_reg = _haltreg, \ 177 .halt_check_type = _type, \ 178 .halt_check_voted = _voted, \ 179 .flags = _flags, \ 180 } 181 182 /* 183 * Fixed "gcc_fepll_vco" PLL derived sources: 184 * 185 * P_FEPLL125 - 125MHz 186 * P_FEPLL125DLY - 125MHz 187 * P_FEPLL200 - 200MHz 188 * "fepll500" - 500MHz 189 * 190 * Fixed "gcc_apps_ddrpll_vco" PLL derived sources: 191 * 192 * P_DDRPLL - 192MHz 193 */ 194 static struct qcom_clk_fdiv_def fdiv_tbl[] = { 195 F_FDIV(GCC_FEPLL125_CLK, "fepll125", "gcc_fepll_vco", 32), 196 F_FDIV(GCC_FEPLL125DLY_CLK, "fepll125dly", "gcc_fepll_vco", 32), 197 F_FDIV(GCC_FEPLL200_CLK, "fepll200", "gcc_fepll_vco", 20), 198 F_FDIV(GCC_FEPLL500_CLK, "fepll500", "gcc_fepll_vco", 8), 199 F_FDIV(GCC_SDCC_PLLDIV_CLK, "ddrpllsdcc", "gcc_apps_ddrpll_vco", 28), 200 }; 201 202 /* 203 * FEPLL - 48MHz (xo) input, 4GHz output 204 * DDRPLL - 48MHz (xo) input, 5.376GHz output 205 */ 206 static struct qcom_clk_fepll_def fepll_tbl[] = { 207 F_FEPLL(GCC_FEPLL_VCO, "gcc_fepll_vco", "xo", 0x2f020, 16, 8, 24, 5), 208 F_FEPLL(GCC_APSS_DDRPLL_VCO, "gcc_apps_ddrpll_vco", "xo", 0x2e020, 209 16, 8, 24, 5), 210 }; 211 212 /* 213 * Frequency table for the APSS PLL/DIV path for the CPU frequency. 214 * 215 * Note - the APSS DIV code only needs the frequency and pre-divisor, 216 * not the other fields. 217 */ 218 static struct qcom_clk_freq_tbl apss_freq_tbl[] = { 219 { 384000000, "gcc_apps_ddrpll_vco", 0xd, 0, 0 }, 220 { 413000000, "gcc_apps_ddrpll_vco", 0xc, 0, 0 }, 221 { 448000000, "gcc_apps_ddrpll_vco", 0xb, 0, 0 }, 222 { 488000000, "gcc_apps_ddrpll_vco", 0xa, 0, 0 }, 223 { 512000000, "gcc_apps_ddrpll_vco", 0x9, 0, 0 }, 224 { 537000000, "gcc_apps_ddrpll_vco", 0x8, 0, 0 }, 225 { 565000000, "gcc_apps_ddrpll_vco", 0x7, 0, 0 }, 226 { 597000000, "gcc_apps_ddrpll_vco", 0x6, 0, 0 }, 227 { 632000000, "gcc_apps_ddrpll_vco", 0x5, 0, 0 }, 228 { 672000000, "gcc_apps_ddrpll_vco", 0x4, 0, 0 }, 229 { 716000000, "gcc_apps_ddrpll_vco", 0x3, 0, 0 }, 230 { 768000000, "gcc_apps_ddrpll_vco", 0x2, 0, 0 }, 231 { 823000000, "gcc_apps_ddrpll_vco", 0x1, 0, 0 }, 232 { 896000000, "gcc_apps_ddrpll_vco", 0x0, 0, 0 }, 233 { 0, } 234 }; 235 236 /* 237 * APSS div/gate 238 */ 239 static struct qcom_clk_apssdiv_def apssdiv_tbl[] = { 240 F_APSSDIV(GCC_APSS_CPU_PLLDIV_CLK, "ddrpllapss", 241 "gcc_apps_ddrpll_vco", 0x2e020, 242 4, 4, 0x2e000, 0, &apss_freq_tbl[0]), 243 }; 244 245 /* 246 * Parent clocks for the apps_clk_src clock. 247 */ 248 static const char * apps_clk_src_parents[] = { 249 "xo", "ddrpllapss", "fepll500", "fepll200" 250 }; 251 252 /* 253 * Parents lists for a variety of blocks. 254 */ 255 static const char * gcc_xo_200_parents[] = { 256 "xo", "fepll200" 257 }; 258 static const char * gcc_xo_200_500_parents[] = { 259 "xo", "fepll200", "fepll500" 260 }; 261 static const char * gcc_xo_200_spi_parents[] = { 262 "xo", NULL, "fepll200" 263 }; 264 static const char * gcc_xo_sdcc1_500_parents[] = { 265 "xo", "ddrpllsdcc", "fepll500" 266 }; 267 268 static const char * gcc_xo_125_dly_parents[] = { 269 "xo", "fepll125dly" 270 }; 271 272 static const char * gcc_xo_wcss2g_parents[] = { 273 "xo", "fepllwcss2g" 274 }; 275 276 static const char * gcc_xo_wcss5g_parents[] = { 277 "xo", "fepllwcss5g" 278 }; 279 280 static struct qcom_clk_freq_tbl apps_clk_src_freq_tbl[] = { 281 { 48000000, "xo", 1, 0, 0 }, 282 { 200000000, "fepll200", 1, 0, 0 }, 283 { 384000000, "ddrpllapss", 1, 0, 0 }, 284 { 413000000, "ddrpllapss", 1, 0, 0 }, 285 { 448000000, "ddrpllapss", 1, 0, 0 }, 286 { 488000000, "ddrpllapss", 1, 0, 0 }, 287 { 500000000, "fepll500", 1, 0, 0 }, 288 { 512000000, "ddrpllapss", 1, 0, 0 }, 289 { 537000000, "ddrpllapss", 1, 0, 0 }, 290 { 565000000, "ddrpllapss", 1, 0, 0 }, 291 { 597000000, "ddrpllapss", 1, 0, 0 }, 292 { 632000000, "ddrpllapss", 1, 0, 0 }, 293 { 672000000, "ddrpllapss", 1, 0, 0 }, 294 { 716000000, "ddrpllapss", 1, 0, 0 }, 295 { 0,} 296 297 }; 298 299 static struct qcom_clk_freq_tbl audio_clk_src_freq_tbl[] = { 300 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 301 { 200000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 302 { 0,} 303 }; 304 305 static struct qcom_clk_freq_tbl blsp1_qup1_i2c_apps_clk_src_freq_tbl[] = { 306 { 19050000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(10.5), 1, 1 }, 307 { 0,} 308 }; 309 310 static struct qcom_clk_freq_tbl blsp1_qup1_spi_apps_clk_src_freq_tbl[] = { 311 { 960000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(12), 1, 4 }, 312 { 4800000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 10 }, 313 { 9600000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 5 }, 314 { 15000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 3 }, 315 { 19200000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 2, 5 }, 316 { 24000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 2 }, 317 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 318 { 0,} 319 }; 320 321 static struct qcom_clk_freq_tbl gcc_pcnoc_ahb_clk_src_freq_tbl[] = { 322 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 323 { 100000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(2), 0, 0 }, 324 { 0, } 325 }; 326 327 static struct qcom_clk_freq_tbl blsp1_uart1_apps_clk_src_freq_tbl[] = { 328 { 1843200, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 144, 15625 }, 329 { 3686400, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 288, 15625 }, 330 { 7372800, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 576, 15625 }, 331 { 14745600, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1152, 15625 }, 332 { 16000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 2, 25 }, 333 { 24000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 2 }, 334 { 32000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 4, 25 }, 335 { 40000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 5 }, 336 { 46400000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 29, 125 }, 337 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 338 { 0, } 339 }; 340 341 static struct qcom_clk_freq_tbl gp1_clk_src_freq_tbl[] = { 342 { 1250000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 16, 0 }, 343 { 2500000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 8, 0 }, 344 { 5000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 4, 0 }, 345 { 0, } 346 }; 347 348 static struct qcom_clk_freq_tbl sdcc1_apps_clk_src_freq_tbl[] = { 349 { 144000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 3, 240 }, 350 { 400000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 0 }, 351 { 20000000, "fepll500", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 25 }, 352 { 25000000, "fepll500", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 20 }, 353 { 50000000, "fepll500", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 10 }, 354 { 100000000, "fepll500", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 1, 5 }, 355 { 192000000, "ddrpllsdcc", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 356 { 0, } 357 }; 358 359 static struct qcom_clk_freq_tbl apps_ahb_clk_src_freq_tbl[] = { 360 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 361 { 100000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(2), 0, 0 }, 362 { 0, } 363 }; 364 365 static struct qcom_clk_freq_tbl usb30_mock_utmi_clk_src_freq_tbl[] = { 366 { 2000000, "fepll200", QCOM_CLK_FREQTBL_PREDIV_RCG2(10), 0, 0 }, 367 { 0, } 368 }; 369 370 static struct qcom_clk_freq_tbl fephy_125m_dly_clk_src_freq_tbl[] = { 371 { 125000000, "fepll125dly", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 372 { 0, } 373 }; 374 375 static struct qcom_clk_freq_tbl wcss2g_clk_src_freq_tbl[] = { 376 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 377 { 250000000, "fepllwcss2g", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 378 { 0, } 379 }; 380 381 static struct qcom_clk_freq_tbl wcss5g_clk_src_freq_tbl[] = { 382 { 48000000, "xo", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 383 { 250000000, "fepllwcss5g", QCOM_CLK_FREQTBL_PREDIV_RCG2(1), 0, 0 }, 384 { 0, } 385 }; 386 387 /* 388 * Divisor table for the 2g/5g wifi clock divisors. 389 */ 390 static struct qcom_clk_ro_div_tbl fepllwcss_clk_div_tbl[] = { 391 { 0, 15 }, 392 { 1, 16 }, 393 { 2, 18 }, 394 { 3, 20 }, 395 { 0, 0 } 396 }; 397 398 /* 399 * Read-only divisor table clocks. 400 */ 401 static struct qcom_clk_ro_div_def ro_div_tbl[] = { 402 F_RO_DIV(GCC_FEPLL_WCSS2G_CLK, "fepllwcss2g", "gcc_fepll_vco", 403 0x2f020, 8, 2, &fepllwcss_clk_div_tbl[0]), 404 F_RO_DIV(GCC_FEPLL_WCSS5G_CLK, "fepllwcss5g", "gcc_fepll_vco", 405 0x2f020, 12, 2, &fepllwcss_clk_div_tbl[0]), 406 }; 407 408 /* 409 * RCG2 clocks 410 */ 411 static struct qcom_clk_rcg2_def rcg2_tbl[] = { 412 F_RCG2(AUDIO_CLK_SRC, "audio_clk_src", gcc_xo_200_parents, 413 0x1b000, 5, 0, -1, -1, 0, 0, &audio_clk_src_freq_tbl[0]), 414 F_RCG2(BLSP1_QUP1_I2C_APPS_CLK_SRC, "blsp1_qup1_i2c_apps_clk_src", 415 gcc_xo_200_parents, 0x200c, 5, 0, -1, -1, 0, 0, 416 &blsp1_qup1_i2c_apps_clk_src_freq_tbl[0]), 417 F_RCG2(BLSP1_QUP2_I2C_APPS_CLK_SRC, "blsp1_qup2_i2c_apps_clk_src", 418 gcc_xo_200_parents, 0x3000, 5, 0, -1, -1, 0, 0, 419 &blsp1_qup1_i2c_apps_clk_src_freq_tbl[0]), 420 F_RCG2(BLSP1_QUP1_SPI_APPS_CLK_SRC, "blsp1_qup1_spi_apps_clk_src", 421 gcc_xo_200_spi_parents, 0x2024, 5, 8, -1, -1, 0, 0, 422 &blsp1_qup1_spi_apps_clk_src_freq_tbl[0]), 423 F_RCG2(BLSP1_QUP2_SPI_APPS_CLK_SRC, "blsp1_qup2_spi_apps_clk_src", 424 gcc_xo_200_spi_parents, 0x3014, 5, 8, -1, -1, 0, 0, 425 &blsp1_qup1_spi_apps_clk_src_freq_tbl[0]), 426 F_RCG2(BLSP1_UART1_APPS_CLK_SRC, "blsp1_uart1_apps_clk_src", 427 gcc_xo_200_spi_parents, 0x2044, 5, 16, -1, -1, 0, 0, 428 &blsp1_uart1_apps_clk_src_freq_tbl[0]), 429 F_RCG2(BLSP1_UART2_APPS_CLK_SRC, "blsp1_uart2_apps_clk_src", 430 gcc_xo_200_spi_parents, 0x3034, 5, 16, -1, -1, 0, 0, 431 &blsp1_uart1_apps_clk_src_freq_tbl[0]), 432 F_RCG2(GP1_CLK_SRC, "gp1_clk_src", gcc_xo_200_parents, 0x8004, 433 5, 8, -1, -1, 0, 0, 434 &gp1_clk_src_freq_tbl[0]), 435 F_RCG2(GP2_CLK_SRC, "gp2_clk_src", gcc_xo_200_parents, 0x9004, 436 5, 8, -1, -1, 0, 0, 437 &gp1_clk_src_freq_tbl[0]), 438 F_RCG2(GP3_CLK_SRC, "gp3_clk_src", gcc_xo_200_parents, 0xa004, 439 5, 8, -1, -1, 0, 0, 440 &gp1_clk_src_freq_tbl[0]), 441 F_RCG2(SDCC1_APPS_CLK_SRC, "sdcc1_apps_clk_src", 442 gcc_xo_sdcc1_500_parents, 0x18004, 5, 0, -1, -1, 0, 0, 443 &sdcc1_apps_clk_src_freq_tbl[0]), 444 F_RCG2(GCC_APPS_CLK_SRC, "apps_clk_src", apps_clk_src_parents, 445 0x1900c, 5, 0, -1, 2, 0, 446 QCOM_CLK_RCG2_FLAGS_SET_RATE_PARENT, 447 &apps_clk_src_freq_tbl[0]), 448 F_RCG2(GCC_APPS_AHB_CLK_SRC, "apps_ahb_clk_src", 449 gcc_xo_200_500_parents, 0x19014, 5, 0, -1, -1, 0, 450 0, &apps_ahb_clk_src_freq_tbl[0]), 451 F_RCG2(GCC_USB3_MOCK_UTMI_CLK_SRC, "usb30_mock_utmi_clk_src", 452 gcc_xo_200_parents, 0x1e000, 5, 0, -1, -1, 0, 0, 453 &usb30_mock_utmi_clk_src_freq_tbl[0]), 454 F_RCG2(FEPHY_125M_DLY_CLK_SRC, "fephy_125m_dly_clk_src", 455 gcc_xo_125_dly_parents, 0x12000, 5, 0, -1, -1, 0, 0, 456 &fephy_125m_dly_clk_src_freq_tbl[0]), 457 F_RCG2(WCSS2G_CLK_SRC, "wcss2g_clk_src", gcc_xo_wcss2g_parents, 458 0x1f000, 5, 0, -1, -1, 0, 0, 459 &wcss2g_clk_src_freq_tbl[0]), 460 F_RCG2(WCSS5G_CLK_SRC, "wcss5g_clk_src", gcc_xo_wcss5g_parents, 461 0x20000, 5, 0, -1, -1, 0, 0, 462 &wcss5g_clk_src_freq_tbl[0]), 463 F_RCG2(GCC_PCNOC_AHB_CLK_SRC, "gcc_pcnoc_ahb_clk_src", 464 gcc_xo_200_500_parents, 0x21024, 5, 0, -1, -1, 0, 0, 465 &gcc_pcnoc_ahb_clk_src_freq_tbl[0]), 466 }; 467 468 /* 469 * branch2 clocks 470 */ 471 static struct qcom_clk_branch2_def branch2_tbl[] = { 472 F_BRANCH2(GCC_AUDIO_AHB_CLK, "gcc_audio_ahb_clk", "pcnoc_clk_src", 473 0x1b010, 0, 0, 0, 0x1b010, QCOM_CLK_BRANCH2_BRANCH_HALT, 474 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 475 F_BRANCH2(GCC_AUDIO_PWM_CLK, "gcc_audio_pwm_clk", "audio_clk_src", 476 0x1b00c, 0, 0, 0, 0x1b00c, QCOM_CLK_BRANCH2_BRANCH_HALT, 477 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 478 F_BRANCH2(GCC_BLSP1_QUP1_I2C_APPS_CLK, "gcc_blsp1_qup1_i2c_apps_clk", 479 "blsp1_qup1_i2c_apps_clk_src", 480 0x2008, 0, 0, 0, 0x2008, QCOM_CLK_BRANCH2_BRANCH_HALT, 481 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 482 F_BRANCH2(GCC_BLSP1_QUP2_I2C_APPS_CLK, "gcc_blsp1_qup2_i2c_apps_clk", 483 "blsp1_qup2_i2c_apps_clk_src", 484 0x3010, 0, 0, 0, 0x3010, QCOM_CLK_BRANCH2_BRANCH_HALT, 485 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 486 F_BRANCH2(GCC_BLSP1_QUP1_SPI_APPS_CLK, "gcc_blsp1_qup1_spi_apps_clk", 487 "blsp1_qup1_spi_apps_clk_src", 488 0x2004, 0, 0, 0, 0x2004, QCOM_CLK_BRANCH2_BRANCH_HALT, 489 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 490 F_BRANCH2(GCC_BLSP1_QUP2_SPI_APPS_CLK, "gcc_blsp1_qup2_spi_apps_clk", 491 "blsp1_qup2_spi_apps_clk_src", 492 0x300c, 0, 0, 0, 0x300c, QCOM_CLK_BRANCH2_BRANCH_HALT, 493 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 494 F_BRANCH2(GCC_BLSP1_UART1_APPS_CLK, "gcc_blsp1_uart1_apps_clk", 495 "blsp1_uart1_apps_clk_src", 496 0x203c, 0, 0, 0, 0x203c, QCOM_CLK_BRANCH2_BRANCH_HALT, 497 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 498 F_BRANCH2(GCC_BLSP1_UART2_APPS_CLK, "gcc_blsp1_uart2_apps_clk", 499 "blsp1_uart2_apps_clk_src", 500 0x302c, 0, 0, 0, 0x302c, QCOM_CLK_BRANCH2_BRANCH_HALT, 501 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 502 F_BRANCH2(GCC_GP1_CLK, "gcc_gp1_clk", "gp1_clk_src", 503 0x8000, 0, 0, 0, 0x8000, QCOM_CLK_BRANCH2_BRANCH_HALT, 504 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 505 F_BRANCH2(GCC_GP2_CLK, "gcc_gp2_clk", "gp2_clk_src", 506 0x9000, 0, 0, 0, 0x9000, QCOM_CLK_BRANCH2_BRANCH_HALT, 507 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 508 F_BRANCH2(GCC_GP3_CLK, "gcc_gp3_clk", "gp3_clk_src", 509 0xa000, 0, 0, 0, 0xa000, QCOM_CLK_BRANCH2_BRANCH_HALT, 510 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 511 /* BRANCH_HALT_VOTED; note the different enable/halt */ 512 F_BRANCH2(GCC_APPS_AHB_CLK_SRC, "gcc_apss_ahb_clk", 513 "apps_ahb_clk_src", 514 0x6000, 14, 0, 0, 0x19004, QCOM_CLK_BRANCH2_BRANCH_HALT, 515 true, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 516 F_BRANCH2(GCC_BLSP1_AHB_CLK, "gcc_blsp1_ahb_clk", 517 "pcnoc_clk_src", 518 0x6000, 10, 0, 0, 0x1008, QCOM_CLK_BRANCH2_BRANCH_HALT, 519 true, 0), /* BRANCH_HALT_VOTED */ 520 F_BRANCH2(GCC_DCD_XO_CLK, "gcc_dcd_xo_clk", "xo", 521 0x2103c, 0, 0, 0, 0x2103c, QCOM_CLK_BRANCH2_BRANCH_HALT, 522 false, 0), 523 F_BRANCH2(GCC_BOOT_ROM_AHB_CLK, "gcc_boot_rom_ahb_clk", 524 "pcnoc_clk_src", 0x1300c, 0, 0, 0, 0x1300c, 525 QCOM_CLK_BRANCH2_BRANCH_HALT, 526 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 527 F_BRANCH2(GCC_CRYPTO_AHB_CLK, "gcc_crypto_ahb_clk", 528 "pcnoc_clk_src", 0x6000, 0, 0, 0, 0x16024, 529 QCOM_CLK_BRANCH2_BRANCH_HALT, 530 true, 0), /* BRANCH_HALT_VOTED */ 531 F_BRANCH2(GCC_CRYPTO_AXI_CLK, "gcc_crypto_axi_clk", 532 "fepll125", 0x6000, 1, 0, 0, 0x16020, 533 QCOM_CLK_BRANCH2_BRANCH_HALT, 534 true, 0), /* BRANCH_HALT_VOTED */ 535 F_BRANCH2(GCC_CRYPTO_CLK, "gcc_crypto_clk", "fepll125", 536 0x6000, 2, 0, 0, 0x1601c, QCOM_CLK_BRANCH2_BRANCH_HALT, 537 true, 0), /* BRANCH_HALT_VOTED */ 538 F_BRANCH2(GCC_ESS_CLK, "gcc_ess_clk", "fephy_125m_dly_clk_src", 539 0x12010, 0, 0, 0, 0x12010, QCOM_CLK_BRANCH2_BRANCH_HALT, 540 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 541 /* BRANCH_HALT_VOTED */ 542 F_BRANCH2(GCC_IMEM_AXI_CLK, "gcc_imem_axi_clk", "fepll200", 543 0x6000, 17, 0, 0, 0xe004, QCOM_CLK_BRANCH2_BRANCH_HALT, 544 true, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 545 F_BRANCH2(GCC_IMEM_CFG_AHB_CLK, "gcc_imem_cfg_ahb_clk", 546 "pcnoc_clk_src", 547 0xe008, 0, 0, 0, 0xe008, QCOM_CLK_BRANCH2_BRANCH_HALT, 548 false, 0), 549 F_BRANCH2(GCC_PCIE_AHB_CLK, "gcc_pcie_ahb_clk", "pcnoc_clk_src", 550 0x1d00c, 0, 0, 0, 0x1d00c, QCOM_CLK_BRANCH2_BRANCH_HALT, 551 false, 0), 552 F_BRANCH2(GCC_PCIE_AXI_M_CLK, "gcc_pcie_axi_m_clk", "fepll200", 553 0x1d004, 0, 0, 0, 0x1d004, QCOM_CLK_BRANCH2_BRANCH_HALT, 554 false, 0), 555 F_BRANCH2(GCC_PCIE_AXI_S_CLK, "gcc_pcie_axi_s_clk", "fepll200", 556 0x1d008, 0, 0, 0, 0x1d008, QCOM_CLK_BRANCH2_BRANCH_HALT, 557 false, 0), 558 F_BRANCH2(GCC_PRNG_AHB_CLK, "gcc_prng_ahb_clk", "pcnoc_clk_src", 559 0x6000, 8, 0, 0, 0x13004, QCOM_CLK_BRANCH2_BRANCH_HALT, 560 true, 0), /* BRANCH_HALT_VOTED */ 561 F_BRANCH2(GCC_QPIC_AHB_CLK, "gcc_qpic_ahb_clk", "pcnoc_clk_src", 562 0x1c008, 0, 0, 0, 0x1c008, QCOM_CLK_BRANCH2_BRANCH_HALT, 563 false, 0), 564 F_BRANCH2(GCC_QPIC_CLK, "gcc_qpic_clk", "pcnoc_clk_src", 565 0x1c004, 0, 0, 0, 0x1c004, QCOM_CLK_BRANCH2_BRANCH_HALT, 566 false, 0), 567 F_BRANCH2(GCC_SDCC1_AHB_CLK, "gcc_sdcc1_ahb_clk", "pcnoc_clk_src", 568 0x18010, 0, 0, 0, 0x18010, QCOM_CLK_BRANCH2_BRANCH_HALT, 569 false, 0), 570 F_BRANCH2(GCC_SDCC1_APPS_CLK, "gcc_sdcc1_apps_clk", 571 "sdcc1_apps_clk_src", 0x1800c, 0, 0, 0, 0x1800c, 572 QCOM_CLK_BRANCH2_BRANCH_HALT, 573 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 574 F_BRANCH2(GCC_TLMM_AHB_CLK, "gcc_tlmm_ahb_clk", "pcnoc_clk_src", 575 0x6000, 5, 0, 0, 0x5004, QCOM_CLK_BRANCH2_BRANCH_HALT, 576 true, 0), /* BRANCH_HALT_VOTED */ 577 F_BRANCH2(GCC_USB2_MASTER_CLK, "gcc_usb2_master_clk", "pcnoc_clk_src", 578 0x1e00c, 0, 0, 0, 0x1e00c, QCOM_CLK_BRANCH2_BRANCH_HALT, 579 false, 0), 580 F_BRANCH2(GCC_USB2_SLEEP_CLK, "gcc_usb2_sleep_clk", 581 "gcc_sleep_clk_src", 0x1e010, 0, 0, 0, 0x1e010, 582 QCOM_CLK_BRANCH2_BRANCH_HALT, 583 false, 0), 584 F_BRANCH2(GCC_USB2_MOCK_UTMI_CLK, "gcc_usb2_mock_utmi_clk", 585 "usb30_mock_utmi_clk_src", 0x1e014, 0, 0, 0, 0x1e014, 586 QCOM_CLK_BRANCH2_BRANCH_HALT, 587 false, 0), 588 F_BRANCH2(GCC_USB3_MASTER_CLK, "gcc_usb3_master_clk", "fepll125", 589 0x1e028, 0, 0, 0, 0x1e028, QCOM_CLK_BRANCH2_BRANCH_HALT, 590 false, 0), 591 F_BRANCH2(GCC_USB3_SLEEP_CLK, "gcc_usb3_sleep_clk", "gcc_sleep_clk_src", 592 0x1e02c, 0, 0, 0, 0x1e02c, QCOM_CLK_BRANCH2_BRANCH_HALT, 593 false, 0), 594 F_BRANCH2(GCC_USB3_MOCK_UTMI_CLK, "gcc_usb3_mock_utmi_clk", 595 "usb30_mock_utmi_clk_src", 596 0x1e030, 0, 0, 0, 0x1e030, QCOM_CLK_BRANCH2_BRANCH_HALT, 597 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 598 /* Note - yes, these two have the same registers in linux */ 599 F_BRANCH2(GCC_WCSS2G_CLK, "gcc_wcss2g_clk", "wcss2g_clk_src", 600 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, 601 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 602 F_BRANCH2(GCC_WCSS2G_REF_CLK, "gcc_wcss2g_ref_clk", "xo", 603 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, 604 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 605 F_BRANCH2(GCC_WCSS2G_RTC_CLK, "gcc_wcss2g_rtc_clk", "gcc_sleep_clk_src", 606 0x1f010, 0, 0, 0, 0x1f010, QCOM_CLK_BRANCH2_BRANCH_HALT, 607 false, 0), 608 609 /* Note - yes, these two have the same registers in linux */ 610 F_BRANCH2(GCC_WCSS5G_CLK, "gcc_wcss5g_clk", "wcss5g_clk_src", 611 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, 612 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 613 F_BRANCH2(GCC_WCSS5G_REF_CLK, "gcc_wcss5g_ref_clk", "xo", 614 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, 615 false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 616 F_BRANCH2(GCC_WCSS5G_RTC_CLK, "gcc_wcss5g_rtc_clk", "gcc_sleep_clk_src", 617 0x1f010, 0, 0, 0, 0x20010, QCOM_CLK_BRANCH2_BRANCH_HALT, 618 false, 0), 619 620 F_BRANCH2(GCC_PCNOC_AHB_CLK, "pcnoc_clk_src", "gcc_pcnoc_ahb_clk_src", 621 0x21030, 0, 0, 0, 0x21030, QCOM_CLK_BRANCH2_BRANCH_HALT, false, 622 QCOM_CLK_BRANCH2_FLAGS_CRITICAL | 623 QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), 624 }; 625 626 static void 627 qcom_gcc_ipq4018_clock_init_fepll(struct qcom_gcc_ipq4018_softc *sc) 628 { 629 int i, rv; 630 631 for (i = 0; i < nitems(fepll_tbl); i++) { 632 rv = qcom_clk_fepll_register(sc->clkdom, fepll_tbl + i); 633 if (rv != 0) 634 panic("qcom_clk_fepll_register failed"); 635 } 636 } 637 638 static void 639 qcom_gcc_ipq4018_clock_init_fdiv(struct qcom_gcc_ipq4018_softc *sc) 640 { 641 int i, rv; 642 643 for (i = 0; i < nitems(fdiv_tbl); i++) { 644 rv = qcom_clk_fdiv_register(sc->clkdom, fdiv_tbl + i); 645 if (rv != 0) 646 panic("qcom_clk_fdiv_register failed"); 647 } 648 } 649 650 static void 651 qcom_gcc_ipq4018_clock_init_apssdiv(struct qcom_gcc_ipq4018_softc *sc) 652 { 653 int i, rv; 654 655 for (i = 0; i < nitems(apssdiv_tbl); i++) { 656 rv = qcom_clk_apssdiv_register(sc->clkdom, apssdiv_tbl + i); 657 if (rv != 0) 658 panic("qcom_clk_apssdiv_register failed"); 659 } 660 } 661 662 static void 663 qcom_gcc_ipq4018_clock_init_rcg2(struct qcom_gcc_ipq4018_softc *sc) 664 { 665 int i, rv; 666 667 for (i = 0; i < nitems(rcg2_tbl); i++) { 668 rv = qcom_clk_rcg2_register(sc->clkdom, rcg2_tbl + i); 669 if (rv != 0) 670 panic("qcom_clk_rcg2_register failed"); 671 } 672 } 673 674 static void 675 qcom_gcc_ipq4018_clock_init_branch2(struct qcom_gcc_ipq4018_softc *sc) 676 { 677 int i, rv; 678 679 for (i = 0; i < nitems(branch2_tbl); i++) { 680 rv = qcom_clk_branch2_register(sc->clkdom, branch2_tbl + i); 681 if (rv != 0) 682 panic("qcom_clk_branch2_register failed"); 683 } 684 } 685 686 static void 687 qcom_gcc_ipq4018_clock_init_ro_div(struct qcom_gcc_ipq4018_softc *sc) 688 { 689 int i, rv; 690 691 for (i = 0; i < nitems(ro_div_tbl); i++) { 692 rv = qcom_clk_ro_div_register(sc->clkdom, ro_div_tbl + i); 693 if (rv != 0) 694 panic("qcom_clk_ro_div_register failed"); 695 } 696 } 697 698 int 699 qcom_gcc_ipq4018_clock_read(device_t dev, bus_addr_t addr, uint32_t *val) 700 { 701 struct qcom_gcc_ipq4018_softc *sc; 702 703 sc = device_get_softc(dev); 704 *val = bus_read_4(sc->reg, addr); 705 return (0); 706 } 707 708 int 709 qcom_gcc_ipq4018_clock_write(device_t dev, bus_addr_t addr, uint32_t val) 710 { 711 struct qcom_gcc_ipq4018_softc *sc; 712 713 sc = device_get_softc(dev); 714 bus_write_4(sc->reg, addr, val); 715 return (0); 716 } 717 718 int 719 qcom_gcc_ipq4018_clock_modify(device_t dev, bus_addr_t addr, 720 uint32_t clear_mask, uint32_t set_mask) 721 { 722 struct qcom_gcc_ipq4018_softc *sc; 723 uint32_t reg; 724 725 sc = device_get_softc(dev); 726 reg = bus_read_4(sc->reg, addr); 727 reg &= clear_mask; 728 reg |= set_mask; 729 bus_write_4(sc->reg, addr, reg); 730 return (0); 731 } 732 733 void 734 qcom_gcc_ipq4018_clock_setup(struct qcom_gcc_ipq4018_softc *sc) 735 { 736 737 sc->clkdom = clkdom_create(sc->dev); 738 739 /* Setup stuff */ 740 qcom_gcc_ipq4018_clock_init_fepll(sc); 741 qcom_gcc_ipq4018_clock_init_fdiv(sc); 742 qcom_gcc_ipq4018_clock_init_apssdiv(sc); 743 qcom_gcc_ipq4018_clock_init_rcg2(sc); 744 qcom_gcc_ipq4018_clock_init_branch2(sc); 745 qcom_gcc_ipq4018_clock_init_ro_div(sc); 746 747 /* Finalise clock tree */ 748 clkdom_finit(sc->clkdom); 749 } 750 751 void 752 qcom_gcc_ipq4018_clock_lock(device_t dev) 753 { 754 struct qcom_gcc_ipq4018_softc *sc; 755 756 sc = device_get_softc(dev); 757 mtx_lock(&sc->mtx); 758 } 759 760 void 761 qcom_gcc_ipq4018_clock_unlock(device_t dev) 762 { 763 struct qcom_gcc_ipq4018_softc *sc; 764 765 sc = device_get_softc(dev); 766 mtx_unlock(&sc->mtx); 767 } 768