1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Driver for Qualcomm IPQ4018 clock and reset device */ 29 30 #include <sys/param.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/module.h> 34 #include <sys/sglist.h> 35 #include <sys/random.h> 36 #include <sys/stdatomic.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <sys/bus.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/hwreset/hwreset.h> 48 49 #include "clkdev_if.h" 50 #include "hwreset_if.h" 51 52 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 53 54 #include "qcom_gcc_ipq4018_var.h" 55 56 57 static int qcom_gcc_ipq4018_modevent(module_t, int, void *); 58 59 static int qcom_gcc_ipq4018_probe(device_t); 60 static int qcom_gcc_ipq4018_attach(device_t); 61 static int qcom_gcc_ipq4018_detach(device_t); 62 63 static int 64 qcom_gcc_ipq4018_modevent(module_t mod, int type, void *unused) 65 { 66 int error; 67 68 switch (type) { 69 case MOD_LOAD: 70 case MOD_QUIESCE: 71 case MOD_UNLOAD: 72 case MOD_SHUTDOWN: 73 error = 0; 74 break; 75 default: 76 error = EOPNOTSUPP; 77 break; 78 } 79 80 return (error); 81 } 82 83 static int 84 qcom_gcc_ipq4018_probe(device_t dev) 85 { 86 if (! ofw_bus_status_okay(dev)) 87 return (ENXIO); 88 89 if (ofw_bus_is_compatible(dev, "qcom,gcc-ipq4019") == 0) 90 return (ENXIO); 91 92 return (0); 93 } 94 95 static int 96 qcom_gcc_ipq4018_attach(device_t dev) 97 { 98 struct qcom_gcc_ipq4018_softc *sc; 99 100 sc = device_get_softc(dev); 101 102 /* Found a compatible device! */ 103 sc->dev = dev; 104 105 sc->reg_rid = 0; 106 sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, 107 &sc->reg_rid, 0x60000, RF_ACTIVE); 108 if (sc->reg == NULL) { 109 device_printf(dev, "Couldn't allocate memory resource!\n"); 110 return (ENXIO); 111 } 112 113 device_set_desc(dev, "Qualcomm IPQ4018 Clock/Reset Controller"); 114 115 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 116 117 /* 118 * Register as a reset provider. 119 */ 120 hwreset_register_ofw_provider(dev); 121 122 /* 123 * Setup and register as a clock provider. 124 */ 125 qcom_gcc_ipq4018_clock_setup(sc); 126 127 return (0); 128 } 129 130 static int 131 qcom_gcc_ipq4018_detach(device_t dev) 132 { 133 struct qcom_gcc_ipq4018_softc *sc; 134 135 sc = device_get_softc(dev); 136 137 /* 138 * TBD - deregistering reset/clock resources. 139 */ 140 141 if (sc->reg != NULL) { 142 bus_release_resource(sc->dev, SYS_RES_MEMORY, 143 sc->reg_rid, sc->reg); 144 } 145 return (0); 146 } 147 148 static device_method_t qcom_gcc_ipq4018_methods[] = { 149 /* Device methods. */ 150 DEVMETHOD(device_probe, qcom_gcc_ipq4018_probe), 151 DEVMETHOD(device_attach, qcom_gcc_ipq4018_attach), 152 DEVMETHOD(device_detach, qcom_gcc_ipq4018_detach), 153 154 /* Reset interface */ 155 DEVMETHOD(hwreset_assert, qcom_gcc_ipq4018_hwreset_assert), 156 DEVMETHOD(hwreset_is_asserted, qcom_gcc_ipq4018_hwreset_is_asserted), 157 158 /* Clock interface */ 159 DEVMETHOD(clkdev_read_4, qcom_gcc_ipq4018_clock_read), 160 DEVMETHOD(clkdev_write_4, qcom_gcc_ipq4018_clock_write), 161 DEVMETHOD(clkdev_modify_4, qcom_gcc_ipq4018_clock_modify), 162 DEVMETHOD(clkdev_device_lock, qcom_gcc_ipq4018_clock_lock), 163 DEVMETHOD(clkdev_device_unlock, qcom_gcc_ipq4018_clock_unlock), 164 165 DEVMETHOD_END 166 }; 167 168 static driver_t qcom_gcc_ipq4018_driver = { 169 "qcom_gcc", 170 qcom_gcc_ipq4018_methods, 171 sizeof(struct qcom_gcc_ipq4018_softc) 172 }; 173 174 EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, simplebus, qcom_gcc_ipq4018_driver, 175 qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 176 EARLY_DRIVER_MODULE(qcom_gcc_ipq4018, ofwbus, qcom_gcc_ipq4018_driver, 177 qcom_gcc_ipq4018_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 178 MODULE_VERSION(qcom_gcc_ipq4018, 1); 179