xref: /freebsd/sys/dev/qcom_clk/qcom_clk_fepll.c (revision edf8578117e8844e02c0121147f45e4609b30680)
1 /*-
2  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/lock.h>
31 #include <sys/mutex.h>
32 #include <sys/rman.h>
33 #include <machine/bus.h>
34 
35 #include <dev/extres/clk/clk.h>
36 #include <dev/extres/clk/clk_div.h>
37 #include <dev/extres/clk/clk_fixed.h>
38 #include <dev/extres/clk/clk_mux.h>
39 
40 #include "qcom_clk_fepll.h"
41 
42 #include "clkdev_if.h"
43 
44 #if 0
45 #define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg);
46 #else
47 #define DPRINTF(dev, msg...)
48 #endif
49 
50 /*
51  * This is the top-level PLL clock on the IPQ4018/IPQ4019.
52  * It's a fixed PLL clock that feeds a bunch of divisors into
53  * downstrem FEPLL* and DDR clocks.
54  *
55  * Now, on Linux the clock code creates multiple instances of this
56  * with an inbuilt divisor.  Here instead there'll be a single
57  * instance of the FEPLL, and then normal divisors will feed into
58  * the multiple PLL nodes.
59  */
60 
61 struct qcom_clk_fepll_sc {
62 	struct clknode	*clknode;
63 	uint32_t offset;
64 	uint32_t fdbkdiv_shift; /* FDBKDIV base */
65 	uint32_t fdbkdiv_width; /* FDBKDIV width */
66 	uint32_t refclkdiv_shift; /* REFCLKDIV base */
67 	uint32_t refclkdiv_width; /* REFCLKDIV width */
68 };
69 
70 static int
71 qcom_clk_fepll_recalc(struct clknode *clk, uint64_t *freq)
72 {
73 	struct qcom_clk_fepll_sc *sc;
74 	uint64_t vco, parent_rate;
75 	uint32_t reg, fdbkdiv, refclkdiv;
76 
77 	sc = clknode_get_softc(clk);
78 
79 	if (freq == NULL || *freq == 0) {
80 		device_printf(clknode_get_device(sc->clknode),
81 		    "%s: called; NULL or 0 frequency\n",
82 		    __func__);
83 		return (ENXIO);
84 	}
85 
86 	parent_rate = *freq;
87 
88 	CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
89 	CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg);
90 	CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
91 
92 	fdbkdiv = (reg >> sc->fdbkdiv_shift) &
93 	    ((1U << sc->fdbkdiv_width) - 1);
94 	refclkdiv = (reg >> sc->refclkdiv_shift) &
95 	    ((1U << sc->refclkdiv_width) - 1);
96 
97 	vco = parent_rate / refclkdiv;
98 	vco = vco * 2;
99 	vco = vco * fdbkdiv;
100 
101 	*freq = vco;
102 	return (0);
103 }
104 
105 static int
106 qcom_clk_fepll_init(struct clknode *clk, device_t dev)
107 {
108 
109 	/*
110 	 * There's only a single parent here for an FEPLL, so just set it
111 	 * to 0; the caller doesn't need to supply it.
112 	 */
113 	clknode_init_parent_idx(clk, 0);
114 
115 	return (0);
116 }
117 
118 static clknode_method_t qcom_clk_fepll_methods[] = {
119 	/* Device interface */
120 	CLKNODEMETHOD(clknode_init,		qcom_clk_fepll_init),
121 	CLKNODEMETHOD(clknode_recalc_freq,	qcom_clk_fepll_recalc),
122 	CLKNODEMETHOD_END
123 };
124 
125 DEFINE_CLASS_1(qcom_clk_fepll, qcom_clk_fepll_class, qcom_clk_fepll_methods,
126    sizeof(struct qcom_clk_fepll_sc), clknode_class);
127 
128 int
129 qcom_clk_fepll_register(struct clkdom *clkdom,
130     struct qcom_clk_fepll_def *clkdef)
131 {
132 	struct clknode *clk;
133 	struct qcom_clk_fepll_sc *sc;
134 
135 	clk = clknode_create(clkdom, &qcom_clk_fepll_class, &clkdef->clkdef);
136 	if (clk == NULL)
137 		return (1);
138 
139 	sc = clknode_get_softc(clk);
140 	sc->clknode = clk;
141 
142 	sc->offset = clkdef->offset;
143 	sc->fdbkdiv_shift = clkdef->fdbkdiv_shift;
144 	sc->fdbkdiv_width = clkdef->fdbkdiv_width;
145 	sc->refclkdiv_shift = clkdef->refclkdiv_shift;
146 	sc->refclkdiv_width = clkdef->refclkdiv_width;
147 
148 	clknode_register(clkdom, clk);
149 
150 	return (0);
151 }
152