1 /*- 2 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 #include <machine/bus.h> 36 37 #include <dev/extres/clk/clk.h> 38 #include <dev/extres/clk/clk_div.h> 39 #include <dev/extres/clk/clk_fixed.h> 40 #include <dev/extres/clk/clk_mux.h> 41 42 #include "qcom_clk_freqtbl.h" 43 #include "qcom_clk_apssdiv.h" 44 45 #include "clkdev_if.h" 46 47 /* 48 * This is a combination gate, divisor/PLL configuration 49 * for the APSS CPU clock. 50 */ 51 52 #if 0 53 #define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg); 54 #else 55 #define DPRINTF(dev, msg...) 56 #endif 57 58 struct qcom_clk_apssdiv_sc { 59 struct clknode *clknode; 60 uint32_t div_offset; 61 uint32_t div_width; 62 uint32_t div_shift; 63 uint32_t enable_offset; 64 uint32_t enable_shift; 65 const struct qcom_clk_freq_tbl *freq_tbl; 66 }; 67 68 static uint64_t 69 qcom_clk_apssdiv_calc_rate(struct clknode *clk, uint64_t freq, uint32_t cdiv) 70 { 71 uint32_t pre_div; 72 73 /* 74 * The divisor isn't a linear map with a linear pre-divisor. 75 */ 76 if (cdiv > 10) { 77 pre_div = (cdiv + 1) * 2; 78 } else { 79 pre_div = cdiv + 12; 80 } 81 /* 82 * Multiplier is a fixed "2" here. 83 */ 84 return (freq * 2L) / pre_div; 85 } 86 87 static int 88 qcom_clk_apssdiv_recalc(struct clknode *clk, uint64_t *freq) 89 { 90 struct qcom_clk_apssdiv_sc *sc; 91 uint32_t reg, cdiv; 92 93 sc = clknode_get_softc(clk); 94 95 if (freq == NULL || *freq == 0) { 96 printf("%s: called; NULL or 0 frequency\n", __func__); 97 return (ENXIO); 98 } 99 100 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 101 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®); 102 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 103 cdiv = (reg >> sc->div_shift) & ((1U << sc->div_width) - 1); 104 105 DPRINTF(clknode_get_device(sc->clknode), 106 "%s: called; cdiv=0x%x, freq=%llu\n", __func__, cdiv, *freq); 107 108 *freq = qcom_clk_apssdiv_calc_rate(clk, *freq, cdiv); 109 110 DPRINTF(clknode_get_device(sc->clknode), 111 "%s: called; freq is %llu\n", __func__, *freq); 112 return (0); 113 } 114 115 #if 0 116 static bool 117 qcom_clk_apssdiv_get_gate_locked(struct qcom_clk_apssdiv_sc *sc) 118 { 119 uint32_t reg; 120 121 if (sc->enable_offset == 0) 122 return (false); 123 124 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset, 125 ®); 126 127 return (!! (reg & (1U << sc->enable_shift))); 128 } 129 #endif 130 131 static int 132 qcom_clk_apssdiv_init(struct clknode *clk, device_t dev) 133 { 134 struct qcom_clk_apssdiv_sc *sc; 135 136 sc = clknode_get_softc(clk); 137 138 /* 139 * There's only a single parent here for an fixed divisor, 140 * so just set it to 0; the caller doesn't need to supply it. 141 * 142 * Note that the freqtbl entries have an upstream clock, 143 * but the APSS div/gate only has a single upstream and we 144 * don't program anything else specific in here. 145 */ 146 clknode_init_parent_idx(clk, 0); 147 148 return (0); 149 } 150 151 static int 152 qcom_clk_apssdiv_set_gate(struct clknode *clk, bool enable) 153 { 154 struct qcom_clk_apssdiv_sc *sc; 155 uint32_t reg; 156 157 sc = clknode_get_softc(clk); 158 159 if (sc->enable_offset == 0) { 160 return (ENXIO); 161 } 162 163 DPRINTF(clknode_get_device(sc->clknode), 164 "%s: called; enable=%d\n", __func__, enable); 165 166 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 167 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset, 168 ®); 169 if (enable) { 170 reg |= (1U << sc->enable_shift); 171 } else { 172 reg &= ~(1U << sc->enable_shift); 173 } 174 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->enable_offset, 175 reg); 176 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 177 178 return (0); 179 } 180 181 /* 182 * Set frequency 183 * 184 * fin - the parent frequency, if exists 185 * fout - starts as the requested frequency, ends with the configured 186 * or dry-run frequency 187 * Flags - CLK_SET_DRYRUN, CLK_SET_ROUND_UP, CLK_SET_ROUND_DOWN 188 * retval - 0, ERANGE 189 */ 190 static int 191 qcom_clk_apssdiv_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 192 int flags, int *stop) 193 { 194 const struct qcom_clk_freq_tbl *f; 195 struct qcom_clk_apssdiv_sc *sc; 196 uint64_t f_freq; 197 uint32_t reg; 198 199 sc = clknode_get_softc(clk); 200 201 /* There are no further PLLs to set in this chain */ 202 *stop = 1; 203 204 /* Search the table for a suitable frequency */ 205 f = qcom_clk_freq_tbl_lookup(sc->freq_tbl, *fout); 206 if (f == NULL) { 207 return (ERANGE); 208 } 209 210 /* 211 * Calculate what the resultant frequency would be based on the 212 * parent PLL. 213 */ 214 f_freq = qcom_clk_apssdiv_calc_rate(clk, fin, f->pre_div); 215 216 DPRINTF(clknode_get_device(sc->clknode), 217 "%s: dryrun: %d, fin=%llu fout=%llu f_freq=%llu pre_div=%u" 218 " target_freq=%llu\n", 219 __func__, 220 !! (flags & CLK_SET_DRYRUN), 221 fin, *fout, f_freq, f->pre_div, f->freq); 222 223 if (flags & CLK_SET_DRYRUN) { 224 *fout = f_freq; 225 return (0); 226 } 227 228 /* 229 * Program in the new pre-divisor. 230 */ 231 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 232 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, ®); 233 reg &= ~(((1U << sc->div_width) - 1) << sc->div_shift); 234 reg |= (f->pre_div << sc->div_shift); 235 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->div_offset, reg); 236 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 237 238 /* 239 * The linux driver notes there's no status/completion bit to poll. 240 * So sleep for a bit and hope that's enough time for it to 241 * settle. 242 */ 243 DELAY(1); 244 245 *fout = f_freq; 246 247 return (0); 248 } 249 250 static clknode_method_t qcom_clk_apssdiv_methods[] = { 251 /* Device interface */ 252 CLKNODEMETHOD(clknode_init, qcom_clk_apssdiv_init), 253 CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_apssdiv_recalc), 254 CLKNODEMETHOD(clknode_set_gate, qcom_clk_apssdiv_set_gate), 255 CLKNODEMETHOD(clknode_set_freq, qcom_clk_apssdiv_set_freq), 256 CLKNODEMETHOD_END 257 }; 258 259 DEFINE_CLASS_1(qcom_clk_apssdiv, qcom_clk_apssdiv_class, 260 qcom_clk_apssdiv_methods, sizeof(struct qcom_clk_apssdiv_sc), 261 clknode_class); 262 263 int 264 qcom_clk_apssdiv_register(struct clkdom *clkdom, 265 struct qcom_clk_apssdiv_def *clkdef) 266 { 267 struct clknode *clk; 268 struct qcom_clk_apssdiv_sc *sc; 269 270 clk = clknode_create(clkdom, &qcom_clk_apssdiv_class, &clkdef->clkdef); 271 if (clk == NULL) 272 return (1); 273 274 sc = clknode_get_softc(clk); 275 sc->clknode = clk; 276 277 sc->div_offset = clkdef->div_offset; 278 sc->div_width = clkdef->div_width; 279 sc->div_shift = clkdef->div_shift; 280 sc->freq_tbl = clkdef->freq_tbl; 281 sc->enable_offset = clkdef->enable_offset; 282 sc->enable_shift = clkdef->enable_shift; 283 284 clknode_register(clkdom, clk); 285 286 return (0); 287 } 288