1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #include "qat_freebsd.h" 4 #include "adf_cfg.h" 5 #include "adf_common_drv.h" 6 #include "adf_accel_devices.h" 7 #include "adf_c62x_hw_data.h" 8 #include "adf_fw_counters.h" 9 #include "adf_cfg_device.h" 10 #include <sys/types.h> 11 #include <sys/kernel.h> 12 #include <sys/malloc.h> 13 #include <machine/bus_dma.h> 14 #include <dev/pci/pcireg.h> 15 #include "adf_heartbeat_dbg.h" 16 #include "adf_cnvnr_freq_counters.h" 17 18 static MALLOC_DEFINE(M_QAT_C62X, "qat_c62x", "qat_c62x"); 19 20 #define ADF_SYSTEM_DEVICE(device_id) \ 21 { \ 22 PCI_VENDOR_ID_INTEL, device_id \ 23 } 24 25 static const struct pci_device_id adf_pci_tbl[] = { ADF_SYSTEM_DEVICE( 26 ADF_C62X_PCI_DEVICE_ID), 27 { 28 0, 29 } }; 30 31 static int 32 adf_probe(device_t dev) 33 { 34 const struct pci_device_id *id; 35 36 for (id = adf_pci_tbl; id->vendor != 0; id++) { 37 if (pci_get_vendor(dev) == id->vendor && 38 pci_get_device(dev) == id->device) { 39 device_set_desc(dev, 40 "Intel " ADF_C62X_DEVICE_NAME 41 " QuickAssist"); 42 return BUS_PROBE_GENERIC; 43 } 44 } 45 return ENXIO; 46 } 47 48 static void 49 adf_cleanup_accel(struct adf_accel_dev *accel_dev) 50 { 51 struct adf_accel_pci *accel_pci_dev = &accel_dev->accel_pci_dev; 52 int i; 53 54 if (accel_dev->dma_tag) 55 bus_dma_tag_destroy(accel_dev->dma_tag); 56 for (i = 0; i < ADF_PCI_MAX_BARS; i++) { 57 struct adf_bar *bar = &accel_pci_dev->pci_bars[i]; 58 59 if (bar->virt_addr) 60 bus_free_resource(accel_pci_dev->pci_dev, 61 SYS_RES_MEMORY, 62 bar->virt_addr); 63 } 64 65 if (accel_dev->hw_device) { 66 switch (pci_get_device(accel_pci_dev->pci_dev)) { 67 case ADF_C62X_PCI_DEVICE_ID: 68 adf_clean_hw_data_c62x(accel_dev->hw_device); 69 break; 70 default: 71 break; 72 } 73 free(accel_dev->hw_device, M_QAT_C62X); 74 accel_dev->hw_device = NULL; 75 } 76 adf_cfg_dev_remove(accel_dev); 77 adf_devmgr_rm_dev(accel_dev, NULL); 78 } 79 80 static int 81 adf_attach(device_t dev) 82 { 83 struct adf_accel_dev *accel_dev; 84 struct adf_accel_pci *accel_pci_dev; 85 struct adf_hw_device_data *hw_data; 86 unsigned int i, bar_nr; 87 int ret, rid; 88 struct adf_cfg_device *cfg_dev = NULL; 89 90 /* Set pci MaxPayLoad to 256. Implemented to avoid the issue of 91 * Pci-passthrough causing Maxpayload to be reset to 128 bytes 92 * when the device is reset. */ 93 if (pci_get_max_payload(dev) != 256) 94 pci_set_max_payload(dev, 256); 95 96 accel_dev = device_get_softc(dev); 97 98 INIT_LIST_HEAD(&accel_dev->crypto_list); 99 accel_pci_dev = &accel_dev->accel_pci_dev; 100 accel_pci_dev->pci_dev = dev; 101 102 if (bus_get_domain(dev, &accel_pci_dev->node) != 0) 103 accel_pci_dev->node = 0; 104 105 /* XXX: Revisit if we actually need a devmgr table at all. */ 106 107 /* Add accel device to accel table. 108 * This should be called before adf_cleanup_accel is called */ 109 if (adf_devmgr_add_dev(accel_dev, NULL)) { 110 device_printf(dev, "Failed to add new accelerator device.\n"); 111 return ENXIO; 112 } 113 114 /* Allocate and configure device configuration structure */ 115 hw_data = malloc(sizeof(*hw_data), M_QAT_C62X, M_WAITOK | M_ZERO); 116 117 accel_dev->hw_device = hw_data; 118 adf_init_hw_data_c62x(accel_dev->hw_device); 119 accel_pci_dev->revid = pci_get_revid(dev); 120 hw_data->fuses = pci_read_config(dev, ADF_DEVICE_FUSECTL_OFFSET, 4); 121 if (accel_pci_dev->revid == 0x00) { 122 device_printf(dev, "A0 stepping is not supported.\n"); 123 ret = ENODEV; 124 goto out_err; 125 } 126 127 /* Get PPAERUCM values and store */ 128 ret = adf_aer_store_ppaerucm_reg(dev, hw_data); 129 if (ret) 130 goto out_err; 131 132 /* Get Accelerators and Accelerators Engines masks */ 133 hw_data->accel_mask = hw_data->get_accel_mask(accel_dev); 134 hw_data->ae_mask = hw_data->get_ae_mask(accel_dev); 135 hw_data->admin_ae_mask = hw_data->ae_mask; 136 accel_pci_dev->sku = hw_data->get_sku(hw_data); 137 /* If the device has no acceleration engines then ignore it. */ 138 if (!hw_data->accel_mask || !hw_data->ae_mask || 139 ((~hw_data->ae_mask) & 0x01)) { 140 device_printf(dev, "No acceleration units found\n"); 141 ret = ENXIO; 142 goto out_err; 143 } 144 145 /* Create device configuration table */ 146 ret = adf_cfg_dev_add(accel_dev); 147 if (ret) 148 goto out_err; 149 150 ret = adf_clock_debugfs_add(accel_dev); 151 if (ret) 152 goto out_err; 153 154 pci_set_max_read_req(dev, 1024); 155 156 ret = bus_dma_tag_create(bus_get_dma_tag(dev), 157 1, 158 0, 159 BUS_SPACE_MAXADDR, 160 BUS_SPACE_MAXADDR, 161 NULL, 162 NULL, 163 BUS_SPACE_MAXSIZE, 164 /* BUS_SPACE_UNRESTRICTED */ 1, 165 BUS_SPACE_MAXSIZE, 166 0, 167 NULL, 168 NULL, 169 &accel_dev->dma_tag); 170 if (ret) 171 goto out_err; 172 173 if (hw_data->get_accel_cap) { 174 hw_data->accel_capabilities_mask = 175 hw_data->get_accel_cap(accel_dev); 176 } 177 178 /* Find and map all the device's BARS */ 179 i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; 180 for (bar_nr = 0; i < ADF_PCI_MAX_BARS && bar_nr < PCIR_MAX_BAR_0; 181 bar_nr++) { 182 struct adf_bar *bar; 183 184 /* 185 * XXX: This isn't quite right as it will ignore a BAR 186 * that wasn't assigned a valid resource range by the 187 * firmware. 188 */ 189 rid = PCIR_BAR(bar_nr); 190 if (bus_get_resource(dev, SYS_RES_MEMORY, rid, NULL, NULL) != 0) 191 continue; 192 bar = &accel_pci_dev->pci_bars[i++]; 193 bar->virt_addr = bus_alloc_resource_any(dev, 194 SYS_RES_MEMORY, 195 &rid, 196 RF_ACTIVE); 197 198 if (bar->virt_addr == NULL) { 199 device_printf(dev, "Failed to map BAR %d\n", bar_nr); 200 ret = ENXIO; 201 goto out_err; 202 } 203 bar->base_addr = rman_get_start(bar->virt_addr); 204 bar->size = rman_get_size(bar->virt_addr); 205 } 206 pci_enable_busmaster(dev); 207 208 if (!accel_dev->hw_device->config_device) { 209 ret = EFAULT; 210 goto out_err; 211 } 212 213 ret = accel_dev->hw_device->config_device(accel_dev); 214 if (ret) 215 goto out_err; 216 217 ret = adf_dev_init(accel_dev); 218 if (ret) 219 goto out_dev_shutdown; 220 221 ret = adf_dev_start(accel_dev); 222 if (ret) 223 goto out_dev_stop; 224 225 cfg_dev = accel_dev->cfg->dev; 226 adf_cfg_device_clear(cfg_dev, accel_dev); 227 free(cfg_dev, M_QAT); 228 accel_dev->cfg->dev = NULL; 229 return ret; 230 out_dev_stop: 231 adf_dev_stop(accel_dev); 232 out_dev_shutdown: 233 adf_dev_shutdown(accel_dev); 234 out_err: 235 adf_cleanup_accel(accel_dev); 236 return ret; 237 } 238 239 static int 240 adf_detach(device_t dev) 241 { 242 struct adf_accel_dev *accel_dev = device_get_softc(dev); 243 244 if (adf_dev_stop(accel_dev)) { 245 device_printf(dev, "Failed to stop QAT accel dev\n"); 246 return EBUSY; 247 } 248 249 adf_dev_shutdown(accel_dev); 250 251 adf_cleanup_accel(accel_dev); 252 253 return 0; 254 } 255 256 static device_method_t adf_methods[] = { DEVMETHOD(device_probe, adf_probe), 257 DEVMETHOD(device_attach, adf_attach), 258 DEVMETHOD(device_detach, adf_detach), 259 260 DEVMETHOD_END }; 261 262 static driver_t adf_driver = { "qat", 263 adf_methods, 264 sizeof(struct adf_accel_dev) }; 265 266 DRIVER_MODULE_ORDERED(qat_c62x, pci, adf_driver, NULL, NULL, SI_ORDER_THIRD); 267 MODULE_VERSION(qat_c62x, 1); 268 MODULE_DEPEND(qat_c62x, qat_common, 1, 1, 1); 269 MODULE_DEPEND(qat_c62x, qat_api, 1, 1, 1); 270 MODULE_DEPEND(qat_c62x, linuxkpi, 1, 1, 1); 271