1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #include "adf_accel_devices.h" 5 #include "adf_common_drv.h" 6 #include "adf_gen4_hw_data.h" 7 8 #define ADF_RPRESET_TIMEOUT_MS 5000 9 #define ADF_RPRESET_POLLING_INTERVAL 20 10 11 static u64 12 build_csr_ring_base_addr(bus_addr_t addr, u32 size) 13 { 14 return BUILD_RING_BASE_ADDR(addr, size); 15 } 16 17 static u32 18 read_csr_ring_head(struct resource *csr_base_addr, u32 bank, u32 ring) 19 { 20 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); 21 } 22 23 static void 24 write_csr_ring_head(struct resource *csr_base_addr, 25 u32 bank, 26 u32 ring, 27 u32 value) 28 { 29 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); 30 } 31 32 static u32 33 read_csr_ring_tail(struct resource *csr_base_addr, u32 bank, u32 ring) 34 { 35 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); 36 } 37 38 static void 39 write_csr_ring_tail(struct resource *csr_base_addr, 40 u32 bank, 41 u32 ring, 42 u32 value) 43 { 44 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); 45 } 46 47 static u32 48 read_csr_e_stat(struct resource *csr_base_addr, u32 bank) 49 { 50 return READ_CSR_E_STAT(csr_base_addr, bank); 51 } 52 53 static void 54 write_csr_ring_config(struct resource *csr_base_addr, 55 u32 bank, 56 u32 ring, 57 u32 value) 58 { 59 WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value); 60 } 61 62 static bus_addr_t 63 read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring) 64 { 65 return READ_CSR_RING_BASE(csr_base_addr, bank, ring); 66 } 67 68 static void 69 write_csr_ring_base(struct resource *csr_base_addr, 70 u32 bank, 71 u32 ring, 72 bus_addr_t addr) 73 { 74 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); 75 } 76 77 static void 78 write_csr_int_flag(struct resource *csr_base_addr, u32 bank, u32 value) 79 { 80 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); 81 } 82 83 static void 84 write_csr_int_srcsel(struct resource *csr_base_addr, u32 bank) 85 { 86 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); 87 } 88 89 static void 90 write_csr_int_col_en(struct resource *csr_base_addr, u32 bank, u32 value) 91 { 92 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); 93 } 94 95 static void 96 write_csr_int_col_ctl(struct resource *csr_base_addr, u32 bank, u32 value) 97 { 98 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); 99 } 100 101 static void 102 write_csr_int_flag_and_col(struct resource *csr_base_addr, u32 bank, u32 value) 103 { 104 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value); 105 } 106 107 static u32 108 read_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank) 109 { 110 return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank); 111 } 112 113 static void 114 write_csr_ring_srv_arb_en(struct resource *csr_base_addr, u32 bank, u32 value) 115 { 116 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value); 117 } 118 119 static u32 120 get_int_col_ctl_enable_mask(void) 121 { 122 return ADF_RING_CSR_INT_COL_CTL_ENABLE; 123 } 124 125 void 126 adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info) 127 { 128 struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops; 129 130 csr_info->arb_enable_mask = 0x1; 131 132 csr_info->csr_addr_offset = ADF_RING_CSR_ADDR_OFFSET; 133 csr_info->ring_bundle_size = ADF_RING_BUNDLE_SIZE; 134 135 csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr; 136 csr_ops->read_csr_ring_head = read_csr_ring_head; 137 csr_ops->write_csr_ring_head = write_csr_ring_head; 138 csr_ops->read_csr_ring_tail = read_csr_ring_tail; 139 csr_ops->write_csr_ring_tail = write_csr_ring_tail; 140 csr_ops->read_csr_e_stat = read_csr_e_stat; 141 csr_ops->write_csr_ring_config = write_csr_ring_config; 142 csr_ops->read_csr_ring_base = read_csr_ring_base; 143 csr_ops->write_csr_ring_base = write_csr_ring_base; 144 csr_ops->write_csr_int_flag = write_csr_int_flag; 145 csr_ops->write_csr_int_srcsel = write_csr_int_srcsel; 146 csr_ops->write_csr_int_col_en = write_csr_int_col_en; 147 csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl; 148 csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col; 149 csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en; 150 csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en; 151 csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask; 152 } 153 154 static int 155 reset_ring_pair(struct resource *csr, u32 bank_number) 156 { 157 int reset_timeout = ADF_RPRESET_TIMEOUT_MS; 158 const int timeout_step = ADF_RPRESET_POLLING_INTERVAL; 159 u32 val; 160 161 /* Write rpresetctl register bit#0 as 1 162 * As rpresetctl registers have no RW bits, no need to preserve 163 * values for other bits, just write bit#0 164 * NOTE: bit#12-bit#31 are WO, the write operation only takes 165 * effect when bit#1 is written 1 for pasid level reset 166 */ 167 ADF_CSR_WR(csr, 168 ADF_WQM_CSR_RPRESETCTL(bank_number), 169 BIT(ADF_WQM_CSR_RPRESETCTL_SHIFT)); 170 171 /* Read rpresetsts register to wait for rp reset complete */ 172 while (reset_timeout > 0) { 173 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); 174 if (val & ADF_WQM_CSR_RPRESETSTS_MASK) 175 break; 176 pause_ms("adfstop", timeout_step); 177 reset_timeout -= timeout_step; 178 } 179 if (reset_timeout <= 0) 180 return EFAULT; 181 182 /* When rp reset is done, clear rpresetsts bit0 */ 183 ADF_CSR_WR(csr, 184 ADF_WQM_CSR_RPRESETSTS(bank_number), 185 BIT(ADF_WQM_CSR_RPRESETSTS_SHIFT)); 186 return 0; 187 } 188 189 int 190 adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number) 191 { 192 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 193 u32 etr_bar_id = hw_data->get_etr_bar_id(hw_data); 194 struct resource *csr; 195 int ret; 196 197 if (bank_number >= hw_data->num_banks) 198 return -EINVAL; 199 200 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr; 201 202 ret = reset_ring_pair(csr, bank_number); 203 if (ret) 204 device_printf(GET_DEV(accel_dev), 205 "ring pair reset failure (timeout)\n"); 206 207 return ret; 208 } 209 210 static inline void 211 adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, u32 *lower) 212 { 213 *lower = lower_32_bits(value); 214 *upper = upper_32_bits(value); 215 } 216 217 int 218 adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev) 219 { 220 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 221 u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE; 222 u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE; 223 u32 ssm_wdt_pke_high = 0; 224 u32 ssm_wdt_pke_low = 0; 225 u32 ssm_wdt_high = 0; 226 u32 ssm_wdt_low = 0; 227 struct resource *pmisc_addr; 228 struct adf_bar *pmisc; 229 int pmisc_id; 230 231 pmisc_id = hw_data->get_misc_bar_id(hw_data); 232 pmisc = &GET_BARS(accel_dev)[pmisc_id]; 233 pmisc_addr = pmisc->virt_addr; 234 235 /* Convert 64bit WDT timer value into 32bit values for 236 * mmio write to 32bit CSRs. 237 */ 238 adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low); 239 adf_gen4_unpack_ssm_wdtimer(timer_val_pke, 240 &ssm_wdt_pke_high, 241 &ssm_wdt_pke_low); 242 243 /* Enable WDT for sym and dc */ 244 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low); 245 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high); 246 /* Enable WDT for pke */ 247 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low); 248 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high); 249 250 return 0; 251 } 252 253 int 254 adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev) 255 { 256 return 0; 257 } 258