1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef _ICP_QAT_HW_H_ 5 #define _ICP_QAT_HW_H_ 6 7 enum icp_qat_hw_ae_id { 8 ICP_QAT_HW_AE_0 = 0, 9 ICP_QAT_HW_AE_1 = 1, 10 ICP_QAT_HW_AE_2 = 2, 11 ICP_QAT_HW_AE_3 = 3, 12 ICP_QAT_HW_AE_4 = 4, 13 ICP_QAT_HW_AE_5 = 5, 14 ICP_QAT_HW_AE_6 = 6, 15 ICP_QAT_HW_AE_7 = 7, 16 ICP_QAT_HW_AE_8 = 8, 17 ICP_QAT_HW_AE_9 = 9, 18 ICP_QAT_HW_AE_10 = 10, 19 ICP_QAT_HW_AE_11 = 11, 20 ICP_QAT_HW_AE_DELIMITER = 12 21 }; 22 23 enum icp_qat_hw_qat_id { 24 ICP_QAT_HW_QAT_0 = 0, 25 ICP_QAT_HW_QAT_1 = 1, 26 ICP_QAT_HW_QAT_2 = 2, 27 ICP_QAT_HW_QAT_3 = 3, 28 ICP_QAT_HW_QAT_4 = 4, 29 ICP_QAT_HW_QAT_5 = 5, 30 ICP_QAT_HW_QAT_DELIMITER = 6 31 }; 32 33 enum icp_qat_hw_auth_algo { 34 ICP_QAT_HW_AUTH_ALGO_NULL = 0, 35 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, 36 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, 37 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, 38 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, 39 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, 40 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, 41 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, 42 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, 43 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, 44 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, 45 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, 46 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, 47 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, 48 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 49 ICP_QAT_HW_AUTH_RESERVED_1 = 15, 50 ICP_QAT_HW_AUTH_RESERVED_2 = 16, 51 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, 52 ICP_QAT_HW_AUTH_RESERVED_3 = 18, 53 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, 54 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20 55 }; 56 57 enum icp_qat_hw_auth_mode { 58 ICP_QAT_HW_AUTH_MODE0 = 0, 59 ICP_QAT_HW_AUTH_MODE1 = 1, 60 ICP_QAT_HW_AUTH_MODE2 = 2, 61 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 62 }; 63 64 struct icp_qat_hw_auth_config { 65 uint32_t config; 66 uint32_t reserved; 67 }; 68 enum icp_qat_slice_mask { 69 ICP_ACCEL_MASK_CIPHER_SLICE = 0x01, 70 ICP_ACCEL_MASK_AUTH_SLICE = 0x02, 71 ICP_ACCEL_MASK_PKE_SLICE = 0x04, 72 ICP_ACCEL_MASK_COMPRESS_SLICE = 0x08, 73 ICP_ACCEL_MASK_DEPRECATED = 0x10, 74 ICP_ACCEL_MASK_EIA3_SLICE = 0x20, 75 ICP_ACCEL_MASK_SHA3_SLICE = 0x40, 76 ICP_ACCEL_MASK_CRYPTO0_SLICE = 0x80, 77 ICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100, 78 ICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200, 79 ICP_ACCEL_MASK_SM3_SLICE = 0x400, 80 ICP_ACCEL_MASK_SM4_SLICE = 0x800 81 }; 82 83 enum icp_qat_capabilities_mask { 84 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0), 85 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1), 86 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2), 87 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3), 88 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4), 89 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5), 90 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6), 91 ICP_ACCEL_CAPABILITIES_RAND = BIT(7), 92 ICP_ACCEL_CAPABILITIES_ZUC = BIT(8), 93 ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9), 94 ICP_ACCEL_CAPABILITIES_KPT = BIT(10), 95 ICP_ACCEL_CAPABILITIES_RL = BIT(11), 96 ICP_ACCEL_CAPABILITIES_HKDF = BIT(12), 97 ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13), 98 ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = BIT(14), 99 ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15), 100 ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16), 101 ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17), 102 ICP_ACCEL_CAPABILITIES_SM2 = BIT(18), 103 ICP_ACCEL_CAPABILITIES_SM3 = BIT(19), 104 ICP_ACCEL_CAPABILITIES_SM4 = BIT(20), 105 ICP_ACCEL_CAPABILITIES_INLINE = BIT(21), 106 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22), 107 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23), 108 ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24), 109 ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25), 110 ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26), 111 ICP_ACCEL_CAPABILITIES_KPT2 = BIT(27), 112 }; 113 114 enum icp_qat_extended_dc_capabilities_mask { 115 ICP_ACCEL_CAPABILITIES_ADVANCED_COMPRESSION = 0x101 116 }; 117 118 #define QAT_AUTH_MODE_BITPOS 4 119 #define QAT_AUTH_MODE_MASK 0xF 120 #define QAT_AUTH_ALGO_BITPOS 0 121 #define QAT_AUTH_ALGO_MASK 0xF 122 #define QAT_AUTH_CMP_BITPOS 8 123 #define QAT_AUTH_HIGH_BIT 4 124 #define QAT_AUTH_CMP_MASK 0x7F 125 #define QAT_AUTH_SHA3_PADDING_BITPOS 16 126 #define QAT_AUTH_SHA3_PADDING_MASK 0x1 127 #define QAT_AUTH_ALGO_SHA3_BITPOS 22 128 #define QAT_AUTH_ALGO_SHA3_MASK 0x3 129 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 130 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 131 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 132 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \ 133 << QAT_AUTH_ALGO_SHA3_BITPOS) | \ 134 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \ 135 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? \ 136 1 : \ 137 0) & \ 138 QAT_AUTH_SHA3_PADDING_MASK) \ 139 << QAT_AUTH_SHA3_PADDING_BITPOS) | \ 140 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 141 142 struct icp_qat_hw_auth_counter { 143 __be32 counter; 144 uint32_t reserved; 145 }; 146 147 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 148 #define QAT_AUTH_COUNT_BITPOS 0 149 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 150 (((val)&QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 151 152 struct icp_qat_hw_auth_setup { 153 struct icp_qat_hw_auth_config auth_config; 154 struct icp_qat_hw_auth_counter auth_counter; 155 }; 156 157 #define QAT_HW_DEFAULT_ALIGNMENT 8 158 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) 159 #define ICP_QAT_HW_NULL_STATE1_SZ 32 160 #define ICP_QAT_HW_MD5_STATE1_SZ 16 161 #define ICP_QAT_HW_SHA1_STATE1_SZ 20 162 #define ICP_QAT_HW_SHA224_STATE1_SZ 32 163 #define ICP_QAT_HW_SHA256_STATE1_SZ 32 164 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 165 #define ICP_QAT_HW_SHA384_STATE1_SZ 64 166 #define ICP_QAT_HW_SHA512_STATE1_SZ 64 167 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 168 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 169 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 170 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 171 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 172 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32 173 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 174 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 175 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 176 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 177 #define ICP_QAT_HW_NULL_STATE2_SZ 32 178 #define ICP_QAT_HW_MD5_STATE2_SZ 16 179 #define ICP_QAT_HW_SHA1_STATE2_SZ 20 180 #define ICP_QAT_HW_SHA224_STATE2_SZ 32 181 #define ICP_QAT_HW_SHA256_STATE2_SZ 32 182 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 183 #define ICP_QAT_HW_SHA384_STATE2_SZ 64 184 #define ICP_QAT_HW_SHA512_STATE2_SZ 64 185 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 186 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 187 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 188 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 189 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 190 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 191 #define ICP_QAT_HW_F9_IK_SZ 16 192 #define ICP_QAT_HW_F9_FK_SZ 16 193 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ \ 194 (ICP_QAT_HW_F9_IK_SZ + ICP_QAT_HW_F9_FK_SZ) 195 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 196 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 197 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 198 #define ICP_QAT_HW_GALOIS_H_SZ 16 199 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 200 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 201 202 struct icp_qat_hw_auth_sha512 { 203 struct icp_qat_hw_auth_setup inner_setup; 204 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 205 struct icp_qat_hw_auth_setup outer_setup; 206 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 207 }; 208 209 struct icp_qat_hw_auth_algo_blk { 210 struct icp_qat_hw_auth_sha512 sha; 211 }; 212 213 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 214 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 215 216 enum icp_qat_hw_cipher_algo { 217 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, 218 ICP_QAT_HW_CIPHER_ALGO_DES = 1, 219 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, 220 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, 221 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, 222 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, 223 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, 224 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, 225 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, 226 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 227 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, 228 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11, 229 ICP_QAT_HW_CIPHER_DELIMITER = 12 230 }; 231 232 enum icp_qat_hw_cipher_mode { 233 ICP_QAT_HW_CIPHER_ECB_MODE = 0, 234 ICP_QAT_HW_CIPHER_CBC_MODE = 1, 235 ICP_QAT_HW_CIPHER_CTR_MODE = 2, 236 ICP_QAT_HW_CIPHER_F8_MODE = 3, 237 ICP_QAT_HW_CIPHER_AEAD_MODE = 4, 238 ICP_QAT_HW_CIPHER_RESERVED_MODE = 5, 239 ICP_QAT_HW_CIPHER_XTS_MODE = 6, 240 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 241 }; 242 243 struct icp_qat_hw_cipher_config { 244 uint32_t val; 245 uint32_t reserved; 246 }; 247 248 enum icp_qat_hw_cipher_dir { 249 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 250 ICP_QAT_HW_CIPHER_DECRYPT = 1, 251 }; 252 253 enum icp_qat_hw_cipher_convert { 254 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 255 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 256 }; 257 258 #define QAT_CIPHER_MODE_BITPOS 4 259 #define QAT_CIPHER_MODE_MASK 0xF 260 #define QAT_CIPHER_ALGO_BITPOS 0 261 #define QAT_CIPHER_ALGO_MASK 0xF 262 #define QAT_CIPHER_CONVERT_BITPOS 9 263 #define QAT_CIPHER_CONVERT_MASK 0x1 264 #define QAT_CIPHER_DIR_BITPOS 8 265 #define QAT_CIPHER_DIR_MASK 0x1 266 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F 267 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 268 #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF 269 #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F 270 #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 271 #define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 272 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 273 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 274 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 275 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 276 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 277 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 278 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 279 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS)) 280 #define ICP_QAT_HW_DES_BLK_SZ 8 281 #define ICP_QAT_HW_3DES_BLK_SZ 8 282 #define ICP_QAT_HW_NULL_BLK_SZ 8 283 #define ICP_QAT_HW_AES_BLK_SZ 16 284 #define ICP_QAT_HW_KASUMI_BLK_SZ 8 285 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 286 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 287 #define ICP_QAT_HW_NULL_KEY_SZ 256 288 #define ICP_QAT_HW_DES_KEY_SZ 8 289 #define ICP_QAT_HW_3DES_KEY_SZ 24 290 #define ICP_QAT_HW_AES_128_KEY_SZ 16 291 #define ICP_QAT_HW_AES_192_KEY_SZ 24 292 #define ICP_QAT_HW_AES_256_KEY_SZ 32 293 #define ICP_QAT_HW_AES_128_F8_KEY_SZ \ 294 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 295 #define ICP_QAT_HW_AES_192_F8_KEY_SZ \ 296 (ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 297 #define ICP_QAT_HW_AES_256_F8_KEY_SZ \ 298 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 299 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 300 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 301 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 302 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 303 #define ICP_QAT_HW_KASUMI_KEY_SZ 16 304 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ 305 (ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 306 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 307 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 308 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 309 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 310 #define ICP_QAT_HW_ARC4_KEY_SZ 256 311 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 312 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 313 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 314 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 315 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 316 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024 317 318 struct icp_qat_hw_cipher_aes256_f8 { 319 struct icp_qat_hw_cipher_config cipher_config; 320 uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 321 }; 322 323 struct icp_qat_hw_cipher_algo_blk { 324 struct icp_qat_hw_cipher_aes256_f8 aes; 325 } __aligned(64); 326 #endif 327