1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef __ICP_QAT_HAL_H 4 #define __ICP_QAT_HAL_H 5 #include "adf_accel_devices.h" 6 #include "icp_qat_fw_loader_handle.h" 7 8 enum hal_global_csr { 9 MISC_CONTROL = 0x04, 10 ICP_RESET = 0x0c, 11 ICP_GLOBAL_CLK_ENABLE = 0x50 12 }; 13 14 enum { MISC_CONTROL_C4XXX = 0xAA0, 15 ICP_RESET_CPP0 = 0x938, 16 ICP_RESET_CPP1 = 0x93c, 17 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964, 18 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 }; 19 20 enum hal_ae_csr { 21 USTORE_ADDRESS = 0x000, 22 USTORE_DATA_LOWER = 0x004, 23 USTORE_DATA_UPPER = 0x008, 24 ALU_OUT = 0x010, 25 CTX_ARB_CNTL = 0x014, 26 CTX_ENABLES = 0x018, 27 CC_ENABLE = 0x01c, 28 CSR_CTX_POINTER = 0x020, 29 CTX_STS_INDIRECT = 0x040, 30 ACTIVE_CTX_STATUS = 0x044, 31 CTX_SIG_EVENTS_INDIRECT = 0x048, 32 CTX_SIG_EVENTS_ACTIVE = 0x04c, 33 CTX_WAKEUP_EVENTS_INDIRECT = 0x050, 34 LM_ADDR_0_INDIRECT = 0x060, 35 LM_ADDR_1_INDIRECT = 0x068, 36 LM_ADDR_2_INDIRECT = 0x0cc, 37 LM_ADDR_3_INDIRECT = 0x0d4, 38 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, 39 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, 40 INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c, 41 INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114, 42 INDIRECT_T_INDEX = 0x0f8, 43 INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc, 44 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, 45 TIMESTAMP_LOW = 0x0c0, 46 TIMESTAMP_HIGH = 0x0c4, 47 PROFILE_COUNT = 0x144, 48 SIGNATURE_ENABLE = 0x150, 49 AE_MISC_CONTROL = 0x160, 50 LOCAL_CSR_STATUS = 0x180, 51 }; 52 53 enum fcu_csr { 54 FCU_CONTROL = 0x00, 55 FCU_STATUS = 0x04, 56 FCU_DRAM_ADDR_LO = 0x0c, 57 FCU_DRAM_ADDR_HI = 0x10, 58 FCU_RAMBASE_ADDR_HI = 0x14, 59 FCU_RAMBASE_ADDR_LO = 0x18 60 }; 61 62 enum fcu_csr_c4xxx { 63 FCU_CONTROL_C4XXX = 0x00, 64 FCU_STATUS_C4XXX = 0x04, 65 FCU_STATUS1_C4XXX = 0x0c, 66 FCU_AE_LOADED_C4XXX = 0x10, 67 FCU_DRAM_ADDR_LO_C4XXX = 0x14, 68 FCU_DRAM_ADDR_HI_C4XXX = 0x18, 69 }; 70 71 enum fcu_csr_4xxx { 72 FCU_CONTROL_4XXX = 0x00, 73 FCU_STATUS_4XXX = 0x04, 74 FCU_ME_BROADCAST_MASK_TYPE = 0x08, 75 FCU_AE_LOADED_4XXX = 0x10, 76 FCU_DRAM_ADDR_LO_4XXX = 0x14, 77 FCU_DRAM_ADDR_HI_4XXX = 0x18, 78 }; 79 80 enum fcu_cmd { 81 FCU_CTRL_CMD_NOOP = 0, 82 FCU_CTRL_CMD_AUTH = 1, 83 FCU_CTRL_CMD_LOAD = 2, 84 FCU_CTRL_CMD_START = 3 85 }; 86 87 enum fcu_sts { 88 FCU_STS_NO_STS = 0, 89 FCU_STS_VERI_DONE = 1, 90 FCU_STS_LOAD_DONE = 2, 91 FCU_STS_VERI_FAIL = 3, 92 FCU_STS_LOAD_FAIL = 4, 93 FCU_STS_BUSY = 5 94 }; 95 #define UA_ECS (0x1 << 31) 96 #define ACS_ABO_BITPOS 31 97 #define ACS_ACNO 0x7 98 #define CE_ENABLE_BITPOS 0x8 99 #define CE_LMADDR_0_GLOBAL_BITPOS 16 100 #define CE_LMADDR_1_GLOBAL_BITPOS 17 101 #define CE_LMADDR_2_GLOBAL_BITPOS 22 102 #define CE_LMADDR_3_GLOBAL_BITPOS 23 103 #define CE_T_INDEX_GLOBAL_BITPOS 21 104 #define CE_NN_MODE_BITPOS 20 105 #define CE_REG_PAR_ERR_BITPOS 25 106 #define CE_BREAKPOINT_BITPOS 27 107 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 108 #define CE_INUSE_CONTEXTS_BITPOS 31 109 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) 110 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) 111 #define XCWE_VOLUNTARY (0x1) 112 #define LCS_STATUS (0x1) 113 #define MMC_SHARE_CS_BITPOS 2 114 #define GLOBAL_CSR 0xA00 115 #define FCU_CTRL_BROADCAST_POS 0x4 116 #define FCU_CTRL_AE_POS 0x8 117 #define FCU_AUTH_STS_MASK 0x7 118 #define FCU_STS_DONE_POS 0x9 119 #define FCU_STS_AUTHFWLD_POS 0X8 120 #define FCU_LOADED_AE_POS 0x16 121 #define FW_AUTH_WAIT_PERIOD 10 122 #define FW_AUTH_MAX_RETRY 300 123 #define FW_BROADCAST_MAX_RETRY 300 124 #define FCU_OFFSET 0x8c0 125 #define FCU_OFFSET_C4XXX 0x1000 126 #define FCU_OFFSET_4XXX 0x1000 127 #define MAX_CPP_NUM 2 128 #define AE_CPP_NUM 2 129 #define AES_PER_CPP 16 130 #define SLICES_PER_CPP 6 131 #define ICP_QAT_AE_OFFSET 0x20000 132 #define ICP_QAT_AE_OFFSET_C4XXX 0x40000 133 #define ICP_QAT_AE_OFFSET_4XXX 0x600000 134 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000) 135 #define ICP_QAT_CAP_OFFSET_C4XXX 0x70000 136 #define ICP_QAT_CAP_OFFSET_4XXX 0x640000 137 #define LOCAL_TO_XFER_REG_OFFSET 0x800 138 #define ICP_QAT_EP_OFFSET 0x3a000 139 #define ICP_QAT_EP_OFFSET_C4XXX 0x60000 140 #define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */ 141 #define MEM_CFG_ERR_BIT 0x20 142 #define AE_TG_NUM_CPM2X 4 143 144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) 145 #define SET_CAP_CSR(handle, csr, val) \ 146 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val) 147 #define GET_CAP_CSR(handle, csr) \ 148 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr)) 149 #define SET_GLB_CSR(handle, csr, val) \ 150 ({ \ 151 u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev)); \ 152 (IS_QAT_GEN3_OR_GEN4(dev_id)) ? \ 153 SET_CAP_CSR((handle), (csr), (val)) : \ 154 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \ 155 }) 156 #define GET_GLB_CSR(handle, csr) \ 157 ({ \ 158 u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev)); \ 159 (IS_QAT_GEN3_OR_GEN4(dev_id)) ? \ 160 GET_CAP_CSR((handle), (csr)) : \ 161 GET_CAP_CSR((handle), (csr) + GLOBAL_CSR); \ 162 }) 163 #define SET_FCU_CSR(handle, csr, val) \ 164 ({ \ 165 typeof(handle) handle_ = (handle); \ 166 typeof(csr) csr_ = (csr); \ 167 typeof(val) val_ = (val); \ 168 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 169 SET_CAP_CSR(handle_, \ 170 ((csr_) + FCU_OFFSET_C4XXX), \ 171 (val_)) : \ 172 ((IS_QAT_GEN4( \ 173 pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 174 SET_CAP_CSR(handle_, \ 175 ((csr_) + FCU_OFFSET_4XXX), \ 176 (val_)) : \ 177 SET_CAP_CSR(handle_, ((csr_) + FCU_OFFSET), (val_))); \ 178 }) 179 #define GET_FCU_CSR(handle, csr) \ 180 ({ \ 181 typeof(handle) handle_ = (handle); \ 182 typeof(csr) csr_ = (csr); \ 183 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 184 GET_CAP_CSR(handle_, (FCU_OFFSET_C4XXX + (csr_))) : \ 185 ((IS_QAT_GEN4( \ 186 pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 187 GET_CAP_CSR(handle_, (FCU_OFFSET_4XXX + (csr_))) : \ 188 GET_CAP_CSR(handle_, (FCU_OFFSET + (csr_)))); \ 189 }) 190 #define AE_CSR(handle, ae) \ 191 ((handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12)) 192 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) 193 #define SET_AE_CSR(handle, ae, csr, val) \ 194 ADF_CSR_WR(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr), val) 195 #define GET_AE_CSR(handle, ae, csr) \ 196 ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr)) 197 #define AE_XFER(handle, ae) \ 198 ((handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12)) 199 #define AE_XFER_ADDR(handle, ae, reg) \ 200 (AE_XFER(handle, ae) + (((reg)&0xff) << 2)) 201 #define SET_AE_XFER(handle, ae, reg, val) \ 202 ADF_CSR_WR(handle->hal_misc_addr_v, AE_XFER_ADDR(handle, ae, reg), val) 203 #define SRAM_WRITE(handle, addr, val) \ 204 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val) 205 #define GET_CSR_OFFSET(device_id, cap_offset_, ae_offset_, ep_offset_) \ 206 ({ \ 207 if (IS_QAT_GEN3(device_id)) { \ 208 cap_offset_ = ICP_QAT_CAP_OFFSET_C4XXX; \ 209 ae_offset_ = ICP_QAT_AE_OFFSET_C4XXX; \ 210 ep_offset_ = ICP_QAT_EP_OFFSET_C4XXX; \ 211 } else if (IS_QAT_GEN4(device_id)) { \ 212 cap_offset_ = ICP_QAT_CAP_OFFSET_4XXX; \ 213 ae_offset_ = ICP_QAT_AE_OFFSET_4XXX; \ 214 ep_offset_ = ICP_QAT_EP_OFFSET_4XXX; \ 215 } else { \ 216 cap_offset_ = ICP_QAT_CAP_OFFSET; \ 217 ae_offset_ = ICP_QAT_AE_OFFSET; \ 218 ep_offset_ = ICP_QAT_EP_OFFSET; \ 219 } \ 220 }) 221 222 #endif 223