1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef __ICP_QAT_HAL_H 5 #define __ICP_QAT_HAL_H 6 #include "adf_accel_devices.h" 7 #include "icp_qat_fw_loader_handle.h" 8 9 enum hal_global_csr { 10 MISC_CONTROL = 0x04, 11 ICP_RESET = 0x0c, 12 ICP_GLOBAL_CLK_ENABLE = 0x50 13 }; 14 15 enum { MISC_CONTROL_C4XXX = 0xAA0, 16 ICP_RESET_CPP0 = 0x938, 17 ICP_RESET_CPP1 = 0x93c, 18 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964, 19 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 }; 20 21 enum hal_ae_csr { 22 USTORE_ADDRESS = 0x000, 23 USTORE_DATA_LOWER = 0x004, 24 USTORE_DATA_UPPER = 0x008, 25 ALU_OUT = 0x010, 26 CTX_ARB_CNTL = 0x014, 27 CTX_ENABLES = 0x018, 28 CC_ENABLE = 0x01c, 29 CSR_CTX_POINTER = 0x020, 30 CTX_STS_INDIRECT = 0x040, 31 ACTIVE_CTX_STATUS = 0x044, 32 CTX_SIG_EVENTS_INDIRECT = 0x048, 33 CTX_SIG_EVENTS_ACTIVE = 0x04c, 34 CTX_WAKEUP_EVENTS_INDIRECT = 0x050, 35 LM_ADDR_0_INDIRECT = 0x060, 36 LM_ADDR_1_INDIRECT = 0x068, 37 LM_ADDR_2_INDIRECT = 0x0cc, 38 LM_ADDR_3_INDIRECT = 0x0d4, 39 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, 40 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, 41 INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c, 42 INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114, 43 INDIRECT_T_INDEX = 0x0f8, 44 INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc, 45 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, 46 TIMESTAMP_LOW = 0x0c0, 47 TIMESTAMP_HIGH = 0x0c4, 48 PROFILE_COUNT = 0x144, 49 SIGNATURE_ENABLE = 0x150, 50 AE_MISC_CONTROL = 0x160, 51 LOCAL_CSR_STATUS = 0x180, 52 }; 53 54 enum fcu_csr { 55 FCU_CONTROL = 0x00, 56 FCU_STATUS = 0x04, 57 FCU_DRAM_ADDR_LO = 0x0c, 58 FCU_DRAM_ADDR_HI = 0x10, 59 FCU_RAMBASE_ADDR_HI = 0x14, 60 FCU_RAMBASE_ADDR_LO = 0x18 61 }; 62 63 enum fcu_csr_c4xxx { 64 FCU_CONTROL_C4XXX = 0x00, 65 FCU_STATUS_C4XXX = 0x04, 66 FCU_STATUS1_C4XXX = 0x0c, 67 FCU_AE_LOADED_C4XXX = 0x10, 68 FCU_DRAM_ADDR_LO_C4XXX = 0x14, 69 FCU_DRAM_ADDR_HI_C4XXX = 0x18, 70 }; 71 72 enum fcu_csr_4xxx { 73 FCU_CONTROL_4XXX = 0x00, 74 FCU_STATUS_4XXX = 0x04, 75 FCU_ME_BROADCAST_MASK_TYPE = 0x08, 76 FCU_AE_LOADED_4XXX = 0x10, 77 FCU_DRAM_ADDR_LO_4XXX = 0x14, 78 FCU_DRAM_ADDR_HI_4XXX = 0x18, 79 }; 80 81 enum fcu_cmd { 82 FCU_CTRL_CMD_NOOP = 0, 83 FCU_CTRL_CMD_AUTH = 1, 84 FCU_CTRL_CMD_LOAD = 2, 85 FCU_CTRL_CMD_START = 3 86 }; 87 88 enum fcu_sts { 89 FCU_STS_NO_STS = 0, 90 FCU_STS_VERI_DONE = 1, 91 FCU_STS_LOAD_DONE = 2, 92 FCU_STS_VERI_FAIL = 3, 93 FCU_STS_LOAD_FAIL = 4, 94 FCU_STS_BUSY = 5 95 }; 96 #define UA_ECS (0x1 << 31) 97 #define ACS_ABO_BITPOS 31 98 #define ACS_ACNO 0x7 99 #define CE_ENABLE_BITPOS 0x8 100 #define CE_LMADDR_0_GLOBAL_BITPOS 16 101 #define CE_LMADDR_1_GLOBAL_BITPOS 17 102 #define CE_LMADDR_2_GLOBAL_BITPOS 22 103 #define CE_LMADDR_3_GLOBAL_BITPOS 23 104 #define CE_T_INDEX_GLOBAL_BITPOS 21 105 #define CE_NN_MODE_BITPOS 20 106 #define CE_REG_PAR_ERR_BITPOS 25 107 #define CE_BREAKPOINT_BITPOS 27 108 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 109 #define CE_INUSE_CONTEXTS_BITPOS 31 110 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) 111 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) 112 #define XCWE_VOLUNTARY (0x1) 113 #define LCS_STATUS (0x1) 114 #define MMC_SHARE_CS_BITPOS 2 115 #define GLOBAL_CSR 0xA00 116 #define FCU_CTRL_BROADCAST_POS 0x4 117 #define FCU_CTRL_AE_POS 0x8 118 #define FCU_AUTH_STS_MASK 0x7 119 #define FCU_STS_DONE_POS 0x9 120 #define FCU_STS_AUTHFWLD_POS 0X8 121 #define FCU_LOADED_AE_POS 0x16 122 #define FW_AUTH_WAIT_PERIOD 10 123 #define FW_AUTH_MAX_RETRY 300 124 #define FW_BROADCAST_MAX_RETRY 300 125 #define FCU_OFFSET 0x8c0 126 #define FCU_OFFSET_C4XXX 0x1000 127 #define FCU_OFFSET_4XXX 0x1000 128 #define MAX_CPP_NUM 2 129 #define AE_CPP_NUM 2 130 #define AES_PER_CPP 16 131 #define SLICES_PER_CPP 6 132 #define ICP_QAT_AE_OFFSET 0x20000 133 #define ICP_QAT_AE_OFFSET_C4XXX 0x40000 134 #define ICP_QAT_AE_OFFSET_4XXX 0x600000 135 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000) 136 #define ICP_QAT_CAP_OFFSET_C4XXX 0x70000 137 #define ICP_QAT_CAP_OFFSET_4XXX 0x640000 138 #define LOCAL_TO_XFER_REG_OFFSET 0x800 139 #define ICP_QAT_EP_OFFSET 0x3a000 140 #define ICP_QAT_EP_OFFSET_C4XXX 0x60000 141 #define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */ 142 #define MEM_CFG_ERR_BIT 0x20 143 #define AE_TG_NUM_CPM2X 4 144 145 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) 146 #define SET_CAP_CSR(handle, csr, val) \ 147 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val) 148 #define GET_CAP_CSR(handle, csr) \ 149 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr)) 150 #define SET_GLB_CSR(handle, csr, val) \ 151 ({ \ 152 u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev)); \ 153 (IS_QAT_GEN3_OR_GEN4(dev_id)) ? \ 154 SET_CAP_CSR((handle), (csr), (val)) : \ 155 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \ 156 }) 157 #define GET_GLB_CSR(handle, csr) \ 158 ({ \ 159 u32 dev_id = pci_get_device(GET_DEV((handle)->accel_dev)); \ 160 (IS_QAT_GEN3_OR_GEN4(dev_id)) ? \ 161 GET_CAP_CSR((handle), (csr)) : \ 162 GET_CAP_CSR((handle), (csr) + GLOBAL_CSR); \ 163 }) 164 #define SET_FCU_CSR(handle, csr, val) \ 165 ({ \ 166 typeof(handle) handle_ = (handle); \ 167 typeof(csr) csr_ = (csr); \ 168 typeof(val) val_ = (val); \ 169 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 170 SET_CAP_CSR(handle_, \ 171 ((csr_) + FCU_OFFSET_C4XXX), \ 172 (val_)) : \ 173 ((IS_QAT_GEN4( \ 174 pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 175 SET_CAP_CSR(handle_, \ 176 ((csr_) + FCU_OFFSET_4XXX), \ 177 (val_)) : \ 178 SET_CAP_CSR(handle_, ((csr_) + FCU_OFFSET), (val_))); \ 179 }) 180 #define GET_FCU_CSR(handle, csr) \ 181 ({ \ 182 typeof(handle) handle_ = (handle); \ 183 typeof(csr) csr_ = (csr); \ 184 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 185 GET_CAP_CSR(handle_, (FCU_OFFSET_C4XXX + (csr_))) : \ 186 ((IS_QAT_GEN4( \ 187 pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 188 GET_CAP_CSR(handle_, (FCU_OFFSET_4XXX + (csr_))) : \ 189 GET_CAP_CSR(handle_, (FCU_OFFSET + (csr_)))); \ 190 }) 191 #define AE_CSR(handle, ae) \ 192 ((handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12)) 193 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) 194 #define SET_AE_CSR(handle, ae, csr, val) \ 195 ADF_CSR_WR(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr), val) 196 #define GET_AE_CSR(handle, ae, csr) \ 197 ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr)) 198 #define AE_XFER(handle, ae) \ 199 ((handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12)) 200 #define AE_XFER_ADDR(handle, ae, reg) \ 201 (AE_XFER(handle, ae) + (((reg)&0xff) << 2)) 202 #define SET_AE_XFER(handle, ae, reg, val) \ 203 ADF_CSR_WR(handle->hal_misc_addr_v, AE_XFER_ADDR(handle, ae, reg), val) 204 #define SRAM_WRITE(handle, addr, val) \ 205 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val) 206 #define GET_CSR_OFFSET(device_id, cap_offset_, ae_offset_, ep_offset_) \ 207 ({ \ 208 if (IS_QAT_GEN3(device_id)) { \ 209 cap_offset_ = ICP_QAT_CAP_OFFSET_C4XXX; \ 210 ae_offset_ = ICP_QAT_AE_OFFSET_C4XXX; \ 211 ep_offset_ = ICP_QAT_EP_OFFSET_C4XXX; \ 212 } else if (IS_QAT_GEN4(device_id)) { \ 213 cap_offset_ = ICP_QAT_CAP_OFFSET_4XXX; \ 214 ae_offset_ = ICP_QAT_AE_OFFSET_4XXX; \ 215 ep_offset_ = ICP_QAT_EP_OFFSET_4XXX; \ 216 } else { \ 217 cap_offset_ = ICP_QAT_CAP_OFFSET; \ 218 ae_offset_ = ICP_QAT_AE_OFFSET; \ 219 ep_offset_ = ICP_QAT_EP_OFFSET; \ 220 } \ 221 }) 222 223 #endif 224