1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef __ICP_QAT_HAL_H 5 #define __ICP_QAT_HAL_H 6 #include "adf_accel_devices.h" 7 #include "icp_qat_fw_loader_handle.h" 8 9 enum hal_global_csr { 10 MISC_CONTROL = 0x04, 11 ICP_RESET = 0x0c, 12 ICP_GLOBAL_CLK_ENABLE = 0x50 13 }; 14 15 enum { MISC_CONTROL_C4XXX = 0xAA0, 16 ICP_RESET_CPP0 = 0x938, 17 ICP_RESET_CPP1 = 0x93c, 18 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964, 19 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 }; 20 21 enum hal_ae_csr { 22 USTORE_ADDRESS = 0x000, 23 USTORE_DATA_LOWER = 0x004, 24 USTORE_DATA_UPPER = 0x008, 25 ALU_OUT = 0x010, 26 CTX_ARB_CNTL = 0x014, 27 CTX_ENABLES = 0x018, 28 CC_ENABLE = 0x01c, 29 CSR_CTX_POINTER = 0x020, 30 CTX_STS_INDIRECT = 0x040, 31 ACTIVE_CTX_STATUS = 0x044, 32 CTX_SIG_EVENTS_INDIRECT = 0x048, 33 CTX_SIG_EVENTS_ACTIVE = 0x04c, 34 CTX_WAKEUP_EVENTS_INDIRECT = 0x050, 35 LM_ADDR_0_INDIRECT = 0x060, 36 LM_ADDR_1_INDIRECT = 0x068, 37 LM_ADDR_2_INDIRECT = 0x0cc, 38 LM_ADDR_3_INDIRECT = 0x0d4, 39 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, 40 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, 41 INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c, 42 INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114, 43 INDIRECT_T_INDEX = 0x0f8, 44 INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc, 45 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, 46 TIMESTAMP_LOW = 0x0c0, 47 TIMESTAMP_HIGH = 0x0c4, 48 PROFILE_COUNT = 0x144, 49 SIGNATURE_ENABLE = 0x150, 50 AE_MISC_CONTROL = 0x160, 51 LOCAL_CSR_STATUS = 0x180, 52 }; 53 54 enum fcu_csr { 55 FCU_CONTROL = 0x0, 56 FCU_STATUS = 0x4, 57 FCU_DRAM_ADDR_LO = 0xc, 58 FCU_DRAM_ADDR_HI = 0x10, 59 FCU_RAMBASE_ADDR_HI = 0x14, 60 FCU_RAMBASE_ADDR_LO = 0x18 61 }; 62 63 enum fcu_csr_c4xxx { 64 FCU_CONTROL_C4XXX = 0x0, 65 FCU_STATUS_C4XXX = 0x4, 66 FCU_STATUS1_C4XXX = 0xc, 67 FCU_AE_LOADED_C4XXX = 0x10, 68 FCU_DRAM_ADDR_LO_C4XXX = 0x14, 69 FCU_DRAM_ADDR_HI_C4XXX = 0x18, 70 }; 71 72 enum fcu_cmd { 73 FCU_CTRL_CMD_NOOP = 0, 74 FCU_CTRL_CMD_AUTH = 1, 75 FCU_CTRL_CMD_LOAD = 2, 76 FCU_CTRL_CMD_START = 3 77 }; 78 79 enum fcu_sts { 80 FCU_STS_NO_STS = 0, 81 FCU_STS_VERI_DONE = 1, 82 FCU_STS_LOAD_DONE = 2, 83 FCU_STS_VERI_FAIL = 3, 84 FCU_STS_LOAD_FAIL = 4, 85 FCU_STS_BUSY = 5 86 }; 87 #define UA_ECS (0x1 << 31) 88 #define ACS_ABO_BITPOS 31 89 #define ACS_ACNO 0x7 90 #define CE_ENABLE_BITPOS 0x8 91 #define CE_LMADDR_0_GLOBAL_BITPOS 16 92 #define CE_LMADDR_1_GLOBAL_BITPOS 17 93 #define CE_LMADDR_2_GLOBAL_BITPOS 22 94 #define CE_LMADDR_3_GLOBAL_BITPOS 23 95 #define CE_T_INDEX_GLOBAL_BITPOS 21 96 #define CE_NN_MODE_BITPOS 20 97 #define CE_REG_PAR_ERR_BITPOS 25 98 #define CE_BREAKPOINT_BITPOS 27 99 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 100 #define CE_INUSE_CONTEXTS_BITPOS 31 101 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) 102 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) 103 #define XCWE_VOLUNTARY (0x1) 104 #define LCS_STATUS (0x1) 105 #define MMC_SHARE_CS_BITPOS 2 106 #define GLOBAL_CSR 0xA00 107 #define FCU_CTRL_AE_POS 0x8 108 #define FCU_AUTH_STS_MASK 0x7 109 #define FCU_STS_DONE_POS 0x9 110 #define FCU_STS_AUTHFWLD_POS 0X8 111 #define FCU_LOADED_AE_POS 0x16 112 #define FW_AUTH_WAIT_PERIOD 10 113 #define FW_AUTH_MAX_RETRY 300 114 #define FCU_OFFSET 0x8c0 115 #define FCU_OFFSET_C4XXX 0x1000 116 #define MAX_CPP_NUM 2 117 #define AE_CPP_NUM 2 118 #define AES_PER_CPP 16 119 #define SLICES_PER_CPP 6 120 #define ICP_QAT_AE_OFFSET 0x20000 121 #define ICP_QAT_AE_OFFSET_C4XXX 0x40000 122 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000) 123 #define ICP_QAT_CAP_OFFSET_C4XXX 0x70000 124 #define LOCAL_TO_XFER_REG_OFFSET 0x800 125 #define ICP_QAT_EP_OFFSET 0x3a000 126 #define ICP_QAT_EP_OFFSET_C4XXX 0x60000 127 #define MEM_CFG_ERR_BIT 0x20 128 129 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) 130 #define SET_CAP_CSR(handle, csr, val) \ 131 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val) 132 #define GET_CAP_CSR(handle, csr) \ 133 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr)) 134 #define SET_GLB_CSR(handle, csr, val) \ 135 ({ \ 136 typeof(handle) handle_ = (handle); \ 137 typeof(csr) csr_ = (csr); \ 138 typeof(val) val_ = (val); \ 139 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 140 SET_CAP_CSR(handle_, (csr_), (val_)) : \ 141 SET_CAP_CSR(handle_, csr_ + GLOBAL_CSR, val_); \ 142 }) 143 #define GET_GLB_CSR(handle, csr) \ 144 ({ \ 145 typeof(handle) handle_ = (handle); \ 146 typeof(csr) csr_ = (csr); \ 147 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 148 (GET_CAP_CSR(handle_, (csr_))) : \ 149 (GET_CAP_CSR(handle_, (GLOBAL_CSR + (csr_)))); \ 150 }) 151 #define SET_FCU_CSR(handle, csr, val) \ 152 ({ \ 153 typeof(handle) handle_ = (handle); \ 154 typeof(csr) csr_ = (csr); \ 155 typeof(val) val_ = (val); \ 156 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 157 SET_CAP_CSR(handle_, \ 158 ((csr_) + FCU_OFFSET_C4XXX), \ 159 (val_)) : \ 160 SET_CAP_CSR(handle_, ((csr_) + FCU_OFFSET), (val_)); \ 161 }) 162 #define GET_FCU_CSR(handle, csr) \ 163 ({ \ 164 typeof(handle) handle_ = (handle); \ 165 typeof(csr) csr_ = (csr); \ 166 (IS_QAT_GEN3(pci_get_device(GET_DEV(handle_->accel_dev)))) ? \ 167 GET_CAP_CSR(handle_, (FCU_OFFSET_C4XXX + (csr_))) : \ 168 GET_CAP_CSR(handle_, (FCU_OFFSET + (csr_))); \ 169 }) 170 #define AE_CSR(handle, ae) \ 171 ((handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12)) 172 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) 173 #define SET_AE_CSR(handle, ae, csr, val) \ 174 ADF_CSR_WR(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr), val) 175 #define GET_AE_CSR(handle, ae, csr) \ 176 ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr)) 177 #define AE_XFER(handle, ae) \ 178 ((handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12)) 179 #define AE_XFER_ADDR(handle, ae, reg) \ 180 (AE_XFER(handle, ae) + (((reg)&0xff) << 2)) 181 #define SET_AE_XFER(handle, ae, reg, val) \ 182 ADF_CSR_WR(handle->hal_misc_addr_v, AE_XFER_ADDR(handle, ae, reg), val) 183 #define SRAM_WRITE(handle, addr, val) \ 184 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val) 185 #define GET_CSR_OFFSET(device_id, cap_offset_, ae_offset_, ep_offset_) \ 186 ({ \ 187 int gen3 = IS_QAT_GEN3(device_id); \ 188 cap_offset_ = \ 189 (gen3 ? ICP_QAT_CAP_OFFSET_C4XXX : ICP_QAT_CAP_OFFSET); \ 190 ae_offset_ = \ 191 (gen3 ? ICP_QAT_AE_OFFSET_C4XXX : ICP_QAT_AE_OFFSET); \ 192 ep_offset_ = \ 193 (gen3 ? ICP_QAT_EP_OFFSET_C4XXX : ICP_QAT_EP_OFFSET); \ 194 }) 195 196 #endif 197