1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_PFVF_MSG_H 5 #define ADF_PFVF_MSG_H 6 7 /* 8 * PF<->VF Gen2 Messaging format 9 * 10 * The PF has an array of 32-bit PF2VF registers, one for each VF. The 11 * PF can access all these registers while each VF can access only the one 12 * register associated with that particular VF. 13 * 14 * The register functionally is split into two parts: 15 * The bottom half is for PF->VF messages. In particular when the first 16 * bit of this register (bit 0) gets set an interrupt will be triggered 17 * in the respective VF. 18 * The top half is for VF->PF messages. In particular when the first bit 19 * of this half of register (bit 16) gets set an interrupt will be triggered 20 * in the PF. 21 * 22 * The remaining bits within this register are available to encode messages. 23 * and implement a collision control mechanism to prevent concurrent use of 24 * the PF2VF register by both the PF and VF. 25 * 26 * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 27 * _______________________________________________ 28 * | | | | | | | | | | | | | | | | | 29 * +-----------------------------------------------+ 30 * \___________________________/ \_________/ ^ ^ 31 * ^ ^ | | 32 * | | | VF2PF Int 33 * | | Message Origin 34 * | Message Type 35 * Message-specific Data/Reserved 36 * 37 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 38 * _______________________________________________ 39 * | | | | | | | | | | | | | | | | | 40 * +-----------------------------------------------+ 41 * \___________________________/ \_________/ ^ ^ 42 * ^ ^ | | 43 * | | | PF2VF Int 44 * | | Message Origin 45 * | Message Type 46 * Message-specific Data/Reserved 47 * 48 * Message Origin (Should always be 1) 49 * A legacy out-of-tree QAT driver allowed for a set of messages not supported 50 * by this driver; these had a Msg Origin of 0 and are ignored by this driver. 51 * 52 * When a PF or VF attempts to send a message in the lower or upper 16 bits, 53 * respectively, the other 16 bits are written to first with a defined 54 * IN_USE_BY pattern as part of a collision control scheme (see function 55 * adf_gen2_pfvf_send() in adf_pf2vf_msg.c). 56 * 57 * 58 * PF<->VF Gen4 Messaging format 59 * 60 * Similarly to the gen2 messaging format, 32-bit long registers are used for 61 * communication between PF and VFs. However, each VF and PF share a pair of 62 * 32-bits register to avoid collisions: one for PV to VF messages and one 63 * for VF to PF messages. 64 * 65 * Both the Interrupt bit and the Message Origin bit retain the same position 66 * and meaning, although non-system messages are now deprecated and not 67 * expected. 68 * 69 * 31 30 9 8 7 6 5 4 3 2 1 0 70 * _______________________________________________ 71 * | | | . . . | | | | | | | | | | | 72 * +-----------------------------------------------+ 73 * \_____________________/ \_______________/ ^ ^ 74 * ^ ^ | | 75 * | | | PF/VF Int 76 * | | Message Origin 77 * | Message Type 78 * Message-specific Data/Reserved 79 * 80 * For both formats, the message reception is acknowledged by lowering the 81 * interrupt bit on the register where the message was sent. 82 */ 83 84 /* PFVF message common bits */ 85 #define ADF_PFVF_INT BIT(0) 86 #define ADF_PFVF_MSGORIGIN_SYSTEM BIT(1) 87 88 /* Different generations have different CSR layouts, use this struct 89 * to abstract these differences away 90 */ 91 struct pfvf_message { 92 u8 type; 93 u32 data; 94 }; 95 96 /* PF->VF messages */ 97 enum pf2vf_msgtype { 98 ADF_PF2VF_MSGTYPE_RESTARTING = 0x01, 99 ADF_PF2VF_MSGTYPE_VERSION_RESP = 0x02, 100 ADF_PF2VF_MSGTYPE_BLKMSG_RESP = 0x03, 101 /* Values from 0x10 are Gen4 specific, message type is only 4 bits in 102 Gen2 devices. */ 103 ADF_PF2VF_MSGTYPE_RP_RESET_RESP = 0x10, 104 }; 105 106 /* VF->PF messages */ 107 enum vf2pf_msgtype { 108 ADF_VF2PF_MSGTYPE_INIT = 0x03, 109 ADF_VF2PF_MSGTYPE_SHUTDOWN = 0x04, 110 ADF_VF2PF_MSGTYPE_VERSION_REQ = 0x05, 111 ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ = 0x06, 112 ADF_VF2PF_MSGTYPE_LARGE_BLOCK_REQ = 0x07, 113 ADF_VF2PF_MSGTYPE_MEDIUM_BLOCK_REQ = 0x08, 114 ADF_VF2PF_MSGTYPE_SMALL_BLOCK_REQ = 0x09, 115 /* Values from 0x10 are Gen4 specific, message type is only 4 bits in 116 Gen2 devices. */ 117 ADF_VF2PF_MSGTYPE_RP_RESET = 0x10, 118 }; 119 120 /* VF/PF compatibility version. */ 121 enum pfvf_compatibility_version { 122 /* Support for extended capabilities */ 123 ADF_PFVF_COMPAT_CAPABILITIES = 0x02, 124 /* In-use pattern cleared by receiver */ 125 ADF_PFVF_COMPAT_FAST_ACK = 0x03, 126 /* Ring to service mapping support for non-standard mappings */ 127 ADF_PFVF_COMPAT_RING_TO_SVC_MAP = 0x04, 128 /* Reference to the latest version */ 129 ADF_PFVF_COMPAT_THIS_VERSION = 0x04, 130 }; 131 132 /* PF->VF Version Response */ 133 #define ADF_PF2VF_VERSION_RESP_VERS_MASK GENMASK(7, 0) 134 #define ADF_PF2VF_VERSION_RESP_RESULT_MASK GENMASK(9, 8) 135 136 enum pf2vf_compat_response { 137 ADF_PF2VF_VF_COMPATIBLE = 0x01, 138 ADF_PF2VF_VF_INCOMPATIBLE = 0x02, 139 ADF_PF2VF_VF_COMPAT_UNKNOWN = 0x03, 140 }; 141 142 enum ring_reset_result { 143 RPRESET_SUCCESS = 0x00, 144 RPRESET_NOT_SUPPORTED = 0x01, 145 RPRESET_INVAL_BANK = 0x02, 146 RPRESET_TIMEOUT = 0x03, 147 }; 148 149 #define ADF_VF2PF_RNG_RESET_RP_MASK GENMASK(1, 0) 150 #define ADF_VF2PF_RNG_RESET_RSVD_MASK GENMASK(25, 2) 151 152 /* PF->VF Block Responses */ 153 #define ADF_PF2VF_BLKMSG_RESP_TYPE_MASK GENMASK(1, 0) 154 #define ADF_PF2VF_BLKMSG_RESP_DATA_MASK GENMASK(9, 2) 155 156 enum pf2vf_blkmsg_resp_type { 157 ADF_PF2VF_BLKMSG_RESP_TYPE_DATA = 0x00, 158 ADF_PF2VF_BLKMSG_RESP_TYPE_CRC = 0x01, 159 ADF_PF2VF_BLKMSG_RESP_TYPE_ERROR = 0x02, 160 }; 161 162 /* PF->VF Block Error Code */ 163 enum pf2vf_blkmsg_error { 164 ADF_PF2VF_INVALID_BLOCK_TYPE = 0x00, 165 ADF_PF2VF_INVALID_BYTE_NUM_REQ = 0x01, 166 ADF_PF2VF_PAYLOAD_TRUNCATED = 0x02, 167 ADF_PF2VF_UNSPECIFIED_ERROR = 0x03, 168 }; 169 170 /* VF->PF Block Requests */ 171 #define ADF_VF2PF_LARGE_BLOCK_TYPE_MASK GENMASK(1, 0) 172 #define ADF_VF2PF_LARGE_BLOCK_BYTE_MASK GENMASK(8, 2) 173 #define ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK GENMASK(2, 0) 174 #define ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK GENMASK(8, 3) 175 #define ADF_VF2PF_SMALL_BLOCK_TYPE_MASK GENMASK(3, 0) 176 #define ADF_VF2PF_SMALL_BLOCK_BYTE_MASK GENMASK(8, 4) 177 #define ADF_VF2PF_BLOCK_CRC_REQ_MASK BIT(9) 178 179 /* PF->VF Block Request Types 180 * 0..15 - 32 byte message 181 * 16..23 - 64 byte message 182 * 24..27 - 128 byte message 183 */ 184 enum vf2pf_blkmsg_req_type { 185 ADF_VF2PF_BLKMSG_REQ_CAP_SUMMARY = 0x02, 186 ADF_VF2PF_BLKMSG_REQ_RING_SVC_MAP = 0x03, 187 }; 188 189 #define ADF_VF2PF_SMALL_BLOCK_TYPE_MAX \ 190 (FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_TYPE_MASK)) 191 192 #define ADF_VF2PF_MEDIUM_BLOCK_TYPE_MAX \ 193 (FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK) + \ 194 ADF_VF2PF_SMALL_BLOCK_TYPE_MAX + 1) 195 196 #define ADF_VF2PF_LARGE_BLOCK_TYPE_MAX \ 197 (FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_TYPE_MASK) + \ 198 ADF_VF2PF_MEDIUM_BLOCK_TYPE_MAX) 199 200 #define ADF_VF2PF_SMALL_BLOCK_BYTE_MAX \ 201 FIELD_MAX(ADF_VF2PF_SMALL_BLOCK_BYTE_MASK) 202 203 #define ADF_VF2PF_MEDIUM_BLOCK_BYTE_MAX \ 204 FIELD_MAX(ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK) 205 206 #define ADF_VF2PF_LARGE_BLOCK_BYTE_MAX \ 207 FIELD_MAX(ADF_VF2PF_LARGE_BLOCK_BYTE_MASK) 208 209 struct pfvf_blkmsg_header { 210 u8 version; 211 u8 payload_size; 212 } __packed; 213 214 #define ADF_PFVF_BLKMSG_HEADER_SIZE (sizeof(struct pfvf_blkmsg_header)) 215 #define ADF_PFVF_BLKMSG_PAYLOAD_SIZE(blkmsg) \ 216 (sizeof(blkmsg) - ADF_PFVF_BLKMSG_HEADER_SIZE) 217 #define ADF_PFVF_BLKMSG_MSG_SIZE(blkmsg) \ 218 (ADF_PFVF_BLKMSG_HEADER_SIZE + (blkmsg)->hdr.payload_size) 219 #define ADF_PFVF_BLKMSG_MSG_MAX_SIZE 128 220 221 /* PF->VF Block message header bytes */ 222 #define ADF_PFVF_BLKMSG_VER_BYTE 0 223 #define ADF_PFVF_BLKMSG_LEN_BYTE 1 224 225 /* PF/VF Capabilities message values */ 226 enum blkmsg_capabilities_versions { 227 ADF_PFVF_CAPABILITIES_V1_VERSION = 0x01, 228 ADF_PFVF_CAPABILITIES_V2_VERSION = 0x02, 229 ADF_PFVF_CAPABILITIES_V3_VERSION = 0x03, 230 }; 231 232 struct capabilities_v1 { 233 struct pfvf_blkmsg_header hdr; 234 u32 ext_dc_caps; 235 } __packed; 236 237 struct capabilities_v2 { 238 struct pfvf_blkmsg_header hdr; 239 u32 ext_dc_caps; 240 u32 capabilities; 241 } __packed; 242 243 struct capabilities_v3 { 244 struct pfvf_blkmsg_header hdr; 245 u32 ext_dc_caps; 246 u32 capabilities; 247 u32 frequency; 248 } __packed; 249 250 /* PF/VF Ring to service mapping values */ 251 enum blkmsg_ring_to_svc_versions { 252 ADF_PFVF_RING_TO_SVC_VERSION = 0x01, 253 }; 254 255 struct ring_to_svc_map_v1 { 256 struct pfvf_blkmsg_header hdr; 257 u16 map; 258 } __packed; 259 260 #endif /* ADF_PFVF_MSG_H */ 261