1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 #ifndef ADF_GEN4_HW_CSR_DATA_H_ 4 #define ADF_GEN4_HW_CSR_DATA_H_ 5 6 #include "adf_accel_devices.h" 7 8 /* Transport access */ 9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 10 #define ADF_RING_CSR_RING_CONFIG 0x1000 11 #define ADF_RING_CSR_RING_LBASE 0x1040 12 #define ADF_RING_CSR_RING_UBASE 0x1080 13 #define ADF_RING_CSR_RING_HEAD 0x0C0 14 #define ADF_RING_CSR_RING_TAIL 0x100 15 #define ADF_RING_CSR_E_STAT 0x14C 16 #define ADF_RING_CSR_INT_FLAG 0x170 17 #define ADF_RING_CSR_INT_SRCSEL 0x174 18 #define ADF_RING_CSR_INT_COL_CTL 0x180 19 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 20 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 21 #define ADF_RING_CSR_INT_COL_EN 0x17C 22 #define ADF_RING_CSR_ADDR_OFFSET 0x100000 23 #define ADF_RING_BUNDLE_SIZE 0x2000 24 25 /* Ring reset */ 26 #define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC) 27 #define ADF_RPRESET_POLL_DELAY_US 20 28 #define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0) 29 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) 30 #define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0) 31 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) 32 33 #define ADF_WQM_CSR_RPRESETCTL_SHIFT 0 34 #define ADF_WQM_CSR_RPRESETCTL_DRAIN_SHIFT 2 35 #define ADF_WQM_CSR_RPRESETCTL_MASK (BIT(3) - 1) 36 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) 37 #define ADF_WQM_CSR_RPRESETSTS_SHIFT 0 38 #define ADF_WQM_CSR_RPRESETSTS_MASK (BIT(0)) 39 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) 40 41 #define BUILD_RING_BASE_ADDR(addr, size) \ 42 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 43 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 44 ADF_CSR_RD((csr_base_addr), \ 45 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 46 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 47 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 48 ADF_CSR_RD((csr_base_addr), \ 49 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 50 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 52 ADF_CSR_RD((csr_base_addr), \ 53 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 54 ADF_RING_CSR_E_STAT) 55 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 56 ADF_CSR_WR((csr_base_addr), \ 57 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 58 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \ 59 value) 60 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 61 do { \ 62 struct resource *_csr_base_addr = csr_base_addr; \ 63 u32 _bank = bank; \ 64 u32 _ring = ring; \ 65 dma_addr_t _value = value; \ 66 u32 l_base = 0, u_base = 0; \ 67 l_base = lower_32_bits(_value); \ 68 u_base = upper_32_bits(_value); \ 69 ADF_CSR_WR((_csr_base_addr), \ 70 ADF_RING_CSR_ADDR_OFFSET + \ 71 ADF_RING_BUNDLE_SIZE * (_bank) + \ 72 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), \ 73 l_base); \ 74 ADF_CSR_WR((_csr_base_addr), \ 75 ADF_RING_CSR_ADDR_OFFSET + \ 76 ADF_RING_BUNDLE_SIZE * (_bank) + \ 77 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), \ 78 u_base); \ 79 } while (0) 80 81 static inline u64 82 read_base_gen4(struct resource *csr_base_addr, u32 bank, u32 ring) 83 { 84 u32 l_base, u_base; 85 u64 addr; 86 87 l_base = ADF_CSR_RD(csr_base_addr, 88 ADF_RING_CSR_ADDR_OFFSET + 89 (ADF_RING_BUNDLE_SIZE * bank) + 90 ADF_RING_CSR_RING_LBASE + (ring << 2)); 91 u_base = ADF_CSR_RD(csr_base_addr, 92 ADF_RING_CSR_ADDR_OFFSET + 93 (ADF_RING_BUNDLE_SIZE * bank) + 94 ADF_RING_CSR_RING_UBASE + (ring << 2)); 95 96 addr = (u64)l_base & 0x00000000FFFFFFFFULL; 97 addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL; 98 99 return addr; 100 } 101 102 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ 103 read_base_gen4((csr_base_addr), (bank), (ring)) 104 105 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 106 ADF_CSR_WR((csr_base_addr), \ 107 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 108 ADF_RING_CSR_RING_HEAD + ((ring) << 2), \ 109 value) 110 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 111 ADF_CSR_WR((csr_base_addr), \ 112 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 113 ADF_RING_CSR_RING_TAIL + ((ring) << 2), \ 114 value) 115 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 116 ADF_CSR_WR((csr_base_addr), \ 117 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 118 ADF_RING_CSR_INT_FLAG, \ 119 (value)) 120 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 121 ADF_CSR_WR((csr_base_addr), \ 122 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 123 ADF_RING_CSR_INT_SRCSEL, \ 124 ADF_BANK_INT_SRC_SEL_MASK) 125 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 126 ADF_CSR_WR((csr_base_addr), \ 127 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 128 ADF_RING_CSR_INT_COL_EN, \ 129 (value)) 130 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 131 ADF_CSR_WR((csr_base_addr), \ 132 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 133 ADF_RING_CSR_INT_COL_CTL, \ 134 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 135 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 136 ADF_CSR_WR((csr_base_addr), \ 137 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 138 ADF_RING_CSR_INT_FLAG_AND_COL, \ 139 (value)) 140 141 /* Arbiter configuration */ 142 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 143 144 #define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \ 145 ADF_CSR_RD((csr_base_addr), \ 146 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 147 ADF_RING_CSR_RING_SRV_ARB_EN) 148 149 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 150 ADF_CSR_WR((csr_base_addr), \ 151 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 152 ADF_RING_CSR_RING_SRV_ARB_EN, \ 153 (value)) 154 155 /* WDT timers 156 * 157 * Timeout is in cycles. Clock speed may vary across products but this 158 * value should be a few milli-seconds. 159 */ 160 #define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL 161 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 162 #define ADF_SSMWDTL_OFFSET 0x54 163 #define ADF_SSMWDTH_OFFSET 0x5C 164 #define ADF_SSMWDTPKEL_OFFSET 0x58 165 #define ADF_SSMWDTPKEH_OFFSET 0x60 166 167 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE) 168 169 int adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 170 void adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 171 int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number); 172 #endif 173