1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_GEN4_HW_CSR_DATA_H_ 5 #define ADF_GEN4_HW_CSR_DATA_H_ 6 7 #include "adf_accel_devices.h" 8 9 /* Transport access */ 10 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 11 #define ADF_RING_CSR_RING_CONFIG 0x1000 12 #define ADF_RING_CSR_RING_LBASE 0x1040 13 #define ADF_RING_CSR_RING_UBASE 0x1080 14 #define ADF_RING_CSR_RING_HEAD 0x0C0 15 #define ADF_RING_CSR_RING_TAIL 0x100 16 #define ADF_RING_CSR_E_STAT 0x14C 17 #define ADF_RING_CSR_INT_FLAG 0x170 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_COL_CTL 0x180 20 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 21 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 22 #define ADF_RING_CSR_INT_COL_EN 0x17C 23 #define ADF_RING_CSR_ADDR_OFFSET 0x100000 24 #define ADF_RING_BUNDLE_SIZE 0x2000 25 26 /* Ring reset */ 27 #define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC) 28 #define ADF_RPRESET_POLL_DELAY_US 20 29 #define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0) 30 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) 31 #define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0) 32 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) 33 34 #define ADF_WQM_CSR_RPRESETCTL_SHIFT 0 35 #define ADF_WQM_CSR_RPRESETCTL_DRAIN_SHIFT 2 36 #define ADF_WQM_CSR_RPRESETCTL_MASK (BIT(3) - 1) 37 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3)) 38 #define ADF_WQM_CSR_RPRESETSTS_SHIFT 0 39 #define ADF_WQM_CSR_RPRESETSTS_MASK (BIT(0)) 40 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4) 41 42 #define BUILD_RING_BASE_ADDR(addr, size) \ 43 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 44 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 45 ADF_CSR_RD((csr_base_addr), \ 46 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 47 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 48 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 49 ADF_CSR_RD((csr_base_addr), \ 50 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 51 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 52 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 53 ADF_CSR_RD((csr_base_addr), \ 54 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 55 ADF_RING_CSR_E_STAT) 56 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 57 ADF_CSR_WR((csr_base_addr), \ 58 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 59 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \ 60 value) 61 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 62 do { \ 63 struct resource *_csr_base_addr = csr_base_addr; \ 64 u32 _bank = bank; \ 65 u32 _ring = ring; \ 66 dma_addr_t _value = value; \ 67 u32 l_base = 0, u_base = 0; \ 68 l_base = lower_32_bits(_value); \ 69 u_base = upper_32_bits(_value); \ 70 ADF_CSR_WR((_csr_base_addr), \ 71 ADF_RING_CSR_ADDR_OFFSET + \ 72 ADF_RING_BUNDLE_SIZE * (_bank) + \ 73 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), \ 74 l_base); \ 75 ADF_CSR_WR((_csr_base_addr), \ 76 ADF_RING_CSR_ADDR_OFFSET + \ 77 ADF_RING_BUNDLE_SIZE * (_bank) + \ 78 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), \ 79 u_base); \ 80 } while (0) 81 82 static inline u64 83 read_base_gen4(struct resource *csr_base_addr, u32 bank, u32 ring) 84 { 85 u32 l_base, u_base; 86 u64 addr; 87 88 l_base = ADF_CSR_RD(csr_base_addr, 89 ADF_RING_CSR_ADDR_OFFSET + 90 (ADF_RING_BUNDLE_SIZE * bank) + 91 ADF_RING_CSR_RING_LBASE + (ring << 2)); 92 u_base = ADF_CSR_RD(csr_base_addr, 93 ADF_RING_CSR_ADDR_OFFSET + 94 (ADF_RING_BUNDLE_SIZE * bank) + 95 ADF_RING_CSR_RING_UBASE + (ring << 2)); 96 97 addr = (u64)l_base & 0x00000000FFFFFFFFULL; 98 addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL; 99 100 return addr; 101 } 102 103 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ 104 read_base_gen4((csr_base_addr), (bank), (ring)) 105 106 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 107 ADF_CSR_WR((csr_base_addr), \ 108 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 109 ADF_RING_CSR_RING_HEAD + ((ring) << 2), \ 110 value) 111 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 112 ADF_CSR_WR((csr_base_addr), \ 113 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 114 ADF_RING_CSR_RING_TAIL + ((ring) << 2), \ 115 value) 116 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 117 ADF_CSR_WR((csr_base_addr), \ 118 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 119 ADF_RING_CSR_INT_FLAG, \ 120 (value)) 121 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 122 ADF_CSR_WR((csr_base_addr), \ 123 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 124 ADF_RING_CSR_INT_SRCSEL, \ 125 ADF_BANK_INT_SRC_SEL_MASK) 126 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 127 ADF_CSR_WR((csr_base_addr), \ 128 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 129 ADF_RING_CSR_INT_COL_EN, \ 130 (value)) 131 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 132 ADF_CSR_WR((csr_base_addr), \ 133 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 134 ADF_RING_CSR_INT_COL_CTL, \ 135 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 136 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 137 ADF_CSR_WR((csr_base_addr), \ 138 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 139 ADF_RING_CSR_INT_FLAG_AND_COL, \ 140 (value)) 141 142 /* Arbiter configuration */ 143 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 144 145 #define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \ 146 ADF_CSR_RD((csr_base_addr), \ 147 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 148 ADF_RING_CSR_RING_SRV_ARB_EN) 149 150 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 151 ADF_CSR_WR((csr_base_addr), \ 152 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 153 ADF_RING_CSR_RING_SRV_ARB_EN, \ 154 (value)) 155 156 /* WDT timers 157 * 158 * Timeout is in cycles. Clock speed may vary across products but this 159 * value should be a few milli-seconds. 160 */ 161 #define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL 162 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 163 #define ADF_SSMWDTL_OFFSET 0x54 164 #define ADF_SSMWDTH_OFFSET 0x5C 165 #define ADF_SSMWDTPKEL_OFFSET 0x58 166 #define ADF_SSMWDTPKEH_OFFSET 0x60 167 168 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE) 169 170 int adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 171 void adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 172 int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number); 173 #endif 174