1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_GEN4_HW_CSR_DATA_H_ 5 #define ADF_GEN4_HW_CSR_DATA_H_ 6 7 #include "adf_accel_devices.h" 8 9 /* Transport access */ 10 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 11 #define ADF_RING_CSR_RING_CONFIG 0x1000 12 #define ADF_RING_CSR_RING_LBASE 0x1040 13 #define ADF_RING_CSR_RING_UBASE 0x1080 14 #define ADF_RING_CSR_RING_HEAD 0x0C0 15 #define ADF_RING_CSR_RING_TAIL 0x100 16 #define ADF_RING_CSR_E_STAT 0x14C 17 #define ADF_RING_CSR_INT_FLAG 0x170 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_COL_CTL 0x180 20 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 21 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 22 #define ADF_RING_CSR_INT_COL_EN 0x17C 23 #define ADF_RING_CSR_ADDR_OFFSET 0x100000 24 #define ADF_RING_BUNDLE_SIZE 0x2000 25 26 #define BUILD_RING_BASE_ADDR(addr, size) \ 27 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 29 ADF_CSR_RD((csr_base_addr), \ 30 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 31 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 33 ADF_CSR_RD((csr_base_addr), \ 34 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 35 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 37 ADF_CSR_RD((csr_base_addr), \ 38 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 39 ADF_RING_CSR_E_STAT) 40 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 41 ADF_CSR_WR((csr_base_addr), \ 42 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 43 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \ 44 value) 45 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 46 do { \ 47 struct resource *_csr_base_addr = csr_base_addr; \ 48 u32 _bank = bank; \ 49 u32 _ring = ring; \ 50 dma_addr_t _value = value; \ 51 u32 l_base = 0, u_base = 0; \ 52 l_base = lower_32_bits(_value); \ 53 u_base = upper_32_bits(_value); \ 54 ADF_CSR_WR((_csr_base_addr), \ 55 ADF_RING_CSR_ADDR_OFFSET + \ 56 ADF_RING_BUNDLE_SIZE * (_bank) + \ 57 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), \ 58 l_base); \ 59 ADF_CSR_WR((_csr_base_addr), \ 60 ADF_RING_CSR_ADDR_OFFSET + \ 61 ADF_RING_BUNDLE_SIZE * (_bank) + \ 62 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), \ 63 u_base); \ 64 } while (0) 65 66 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 67 ADF_CSR_WR((csr_base_addr), \ 68 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 69 ADF_RING_CSR_RING_HEAD + ((ring) << 2), \ 70 value) 71 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 72 ADF_CSR_WR((csr_base_addr), \ 73 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 74 ADF_RING_CSR_RING_TAIL + ((ring) << 2), \ 75 value) 76 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 77 ADF_CSR_WR((csr_base_addr), \ 78 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 79 ADF_RING_CSR_INT_FLAG, \ 80 (value)) 81 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 82 ADF_CSR_WR((csr_base_addr), \ 83 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 84 ADF_RING_CSR_INT_SRCSEL, \ 85 ADF_BANK_INT_SRC_SEL_MASK) 86 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 87 ADF_CSR_WR((csr_base_addr), \ 88 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 89 ADF_RING_CSR_INT_COL_EN, \ 90 (value)) 91 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 92 ADF_CSR_WR((csr_base_addr), \ 93 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 94 ADF_RING_CSR_INT_COL_CTL, \ 95 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 96 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 97 ADF_CSR_WR((csr_base_addr), \ 98 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 99 ADF_RING_CSR_INT_FLAG_AND_COL, \ 100 (value)) 101 102 /* Arbiter configuration */ 103 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 104 105 #define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \ 106 ADF_CSR_RD((csr_base_addr), \ 107 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 108 ADF_RING_CSR_RING_SRV_ARB_EN) 109 110 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 111 ADF_CSR_WR((csr_base_addr), \ 112 ADF_RING_CSR_ADDR_OFFSET + ADF_RING_BUNDLE_SIZE * (bank) + \ 113 ADF_RING_CSR_RING_SRV_ARB_EN, \ 114 (value)) 115 116 /* WDT timers 117 * 118 * Timeout is in cycles. Clock speed may vary across products but this 119 * value should be a few milli-seconds. 120 */ 121 #define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL 122 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 123 #define ADF_SSMWDTL_OFFSET 0x54 124 #define ADF_SSMWDTH_OFFSET 0x5C 125 #define ADF_SSMWDTPKEL_OFFSET 0x58 126 #define ADF_SSMWDTPKEH_OFFSET 0x60 127 128 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE) 129 130 int adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 131 void adf_gen4_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 132 #endif 133