xref: /freebsd/sys/dev/qat/include/common/adf_gen2_hw_data.h (revision a64729f5077d77e13b9497cb33ecb3c82e606ee8)
1 /* SPDX-License-Identifier: BSD-3-Clause  */
2 /* Copyright(c) 2021 Intel Corporation */
3 #ifndef ADF_GEN2_HW_DATA_H_
4 #define ADF_GEN2_HW_DATA_H_
5 
6 #include "adf_accel_devices.h"
7 #include "adf_cfg_common.h"
8 
9 /* Transport access */
10 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12 #define ADF_RING_CSR_RING_CONFIG 0x000
13 #define ADF_RING_CSR_RING_LBASE 0x040
14 #define ADF_RING_CSR_RING_UBASE 0x080
15 #define ADF_RING_CSR_RING_HEAD 0x0C0
16 #define ADF_RING_CSR_RING_TAIL 0x100
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_INT_FLAG 0x170
19 #define ADF_RING_CSR_INT_SRCSEL 0x174
20 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
21 #define ADF_RING_CSR_INT_COL_EN 0x17C
22 #define ADF_RING_CSR_INT_COL_CTL 0x180
23 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
24 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
25 #define ADF_RING_CSR_ADDR_OFFSET 0x0
26 #define ADF_RING_BUNDLE_SIZE 0x1000
27 #define ADF_GEN2_RX_RINGS_OFFSET 8
28 #define ADF_GEN2_TX_RINGS_MASK 0xFF
29 
30 #define BUILD_RING_BASE_ADDR(addr, size)                                       \
31 	(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
32 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring)                          \
33 	ADF_CSR_RD(csr_base_addr,                                              \
34 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD +  \
35 		       ((ring) << 2))
36 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring)                          \
37 	ADF_CSR_RD(csr_base_addr,                                              \
38 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL +  \
39 		       ((ring) << 2))
40 #define READ_CSR_E_STAT(csr_base_addr, bank)                                   \
41 	ADF_CSR_RD(csr_base_addr,                                              \
42 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT)
43 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value)                \
44 	ADF_CSR_WR(csr_base_addr,                                              \
45 		   (ADF_RING_BUNDLE_SIZE * (bank)) +                           \
46 		       ADF_RING_CSR_RING_CONFIG + ((ring) << 2),               \
47 		   value)
48 
49 static inline uint64_t
50 read_base(struct resource *csr_base_addr, u32 bank, u32 ring)
51 {
52 	u32 l_base, u_base;
53 	u64 addr;
54 
55 	l_base = ADF_CSR_RD(csr_base_addr,
56 			    (ADF_RING_BUNDLE_SIZE * bank) +
57 				ADF_RING_CSR_RING_LBASE + (ring << 2));
58 	u_base = ADF_CSR_RD(csr_base_addr,
59 			    (ADF_RING_BUNDLE_SIZE * bank) +
60 				ADF_RING_CSR_RING_UBASE + (ring << 2));
61 
62 	addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL;
63 	addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL;
64 
65 	return addr;
66 }
67 
68 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring)                          \
69 	read_base(csr_base_addr, bank, ring)
70 
71 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value)                  \
72 	do {                                                                   \
73 		u32 l_base = 0, u_base = 0;                                    \
74 		l_base = (u32)((value)&0xFFFFFFFF);                            \
75 		u_base = (u32)(((value)&0xFFFFFFFF00000000ULL) >> 32);         \
76 		ADF_CSR_WR(csr_base_addr,                                      \
77 			   (ADF_RING_BUNDLE_SIZE * (bank)) +                   \
78 			       ADF_RING_CSR_RING_LBASE + ((ring) << 2),        \
79 			   l_base);                                            \
80 		ADF_CSR_WR(csr_base_addr,                                      \
81 			   (ADF_RING_BUNDLE_SIZE * (bank)) +                   \
82 			       ADF_RING_CSR_RING_UBASE + ((ring) << 2),        \
83 			   u_base);                                            \
84 	} while (0)
85 
86 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value)                  \
87 	ADF_CSR_WR(csr_base_addr,                                              \
88 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD +  \
89 		       ((ring) << 2),                                          \
90 		   value)
91 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value)                  \
92 	ADF_CSR_WR(csr_base_addr,                                              \
93 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL +  \
94 		       ((ring) << 2),                                          \
95 		   value)
96 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value)                         \
97 	ADF_CSR_WR(csr_base_addr,                                              \
98 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG,    \
99 		   value)
100 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank)                              \
101 	do {                                                                   \
102 		ADF_CSR_WR(csr_base_addr,                                      \
103 			   (ADF_RING_BUNDLE_SIZE * (bank)) +                   \
104 			       ADF_RING_CSR_INT_SRCSEL,                        \
105 			   ADF_BANK_INT_SRC_SEL_MASK_0);                       \
106 		ADF_CSR_WR(csr_base_addr,                                      \
107 			   (ADF_RING_BUNDLE_SIZE * (bank)) +                   \
108 			       ADF_RING_CSR_INT_SRCSEL_2,                      \
109 			   ADF_BANK_INT_SRC_SEL_MASK_X);                       \
110 	} while (0)
111 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value)                       \
112 	ADF_CSR_WR(csr_base_addr,                                              \
113 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_EN,  \
114 		   value)
115 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value)                      \
116 	ADF_CSR_WR(csr_base_addr,                                              \
117 		   (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_CTL, \
118 		   ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
119 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value)                 \
120 	ADF_CSR_WR(csr_base_addr,                                              \
121 		   (ADF_RING_BUNDLE_SIZE * (bank)) +                           \
122 		       ADF_RING_CSR_INT_FLAG_AND_COL,                          \
123 		   value)
124 
125 /* AE to function map */
126 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
127 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
128 #define AE2FUNCTION_MAP_REG_SIZE 4
129 #define AE2FUNCTION_MAP_VALID BIT(7)
130 
131 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index)                      \
132 	ADF_CSR_RD(pmisc_bar_addr,                                             \
133 		   AE2FUNCTION_MAP_A_OFFSET +                                  \
134 		       AE2FUNCTION_MAP_REG_SIZE * (index))
135 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value)              \
136 	ADF_CSR_WR(pmisc_bar_addr,                                             \
137 		   AE2FUNCTION_MAP_A_OFFSET +                                  \
138 		       AE2FUNCTION_MAP_REG_SIZE * (index),                     \
139 		   value)
140 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index)                      \
141 	ADF_CSR_RD(pmisc_bar_addr,                                             \
142 		   AE2FUNCTION_MAP_B_OFFSET +                                  \
143 		       AE2FUNCTION_MAP_REG_SIZE * (index))
144 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value)              \
145 	ADF_CSR_WR(pmisc_bar_addr,                                             \
146 		   AE2FUNCTION_MAP_B_OFFSET +                                  \
147 		       AE2FUNCTION_MAP_REG_SIZE * (index),                     \
148 		   value)
149 
150 /* Admin Interface Offsets */
151 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
152 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
153 #define ADF_MAILBOX_BASE_OFFSET 0x20970
154 
155 /* Arbiter configuration */
156 #define ADF_ARB_OFFSET 0x30000
157 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
158 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
159 #define ADF_ARB_REG_SLOT 0x1000
160 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
161 
162 #define READ_CSR_RING_SRV_ARB_EN(csr_addr, index)                              \
163 	ADF_CSR_RD(csr_addr,                                                   \
164 		   ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)))
165 
166 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value)                      \
167 	ADF_CSR_WR(csr_addr,                                                   \
168 		   ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)), \
169 		   value)
170 
171 /* Power gating */
172 #define ADF_POWERGATE_DC BIT(23)
173 #define ADF_POWERGATE_PKE BIT(24)
174 
175 /* Default ring mapping */
176 #define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP                                       \
177 	(CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT |                            \
178 	 CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT |                            \
179 	 UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT |                            \
180 	 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
181 
182 /* Error detection and correction */
183 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818)
184 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960)
185 #define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28)
186 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
187 #define ADF_GEN2_UERRSSMSH(i) ((i)*0x4000 + 0x18)
188 #define ADF_GEN2_CERRSSMSH(i) ((i)*0x4000 + 0x10)
189 #define ADF_GEN2_ERRSSMSH_EN BIT(3)
190 
191 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND)
192 
193 void adf_gen2_init_hw_csr_info(struct adf_hw_csr_info *csr_info);
194 
195 #endif
196