1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2021 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_GEN2_HW_DATA_H_ 5 #define ADF_GEN2_HW_DATA_H_ 6 7 #include "adf_accel_devices.h" 8 #include "adf_cfg_common.h" 9 10 /* Transport access */ 11 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 12 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 13 #define ADF_RING_CSR_RING_CONFIG 0x000 14 #define ADF_RING_CSR_RING_LBASE 0x040 15 #define ADF_RING_CSR_RING_UBASE 0x080 16 #define ADF_RING_CSR_RING_HEAD 0x0C0 17 #define ADF_RING_CSR_RING_TAIL 0x100 18 #define ADF_RING_CSR_E_STAT 0x14C 19 #define ADF_RING_CSR_INT_FLAG 0x170 20 #define ADF_RING_CSR_INT_SRCSEL 0x174 21 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 22 #define ADF_RING_CSR_INT_COL_EN 0x17C 23 #define ADF_RING_CSR_INT_COL_CTL 0x180 24 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 25 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 26 #define ADF_RING_CSR_ADDR_OFFSET 0x0 27 #define ADF_RING_BUNDLE_SIZE 0x1000 28 #define ADF_GEN2_RX_RINGS_OFFSET 8 29 #define ADF_GEN2_TX_RINGS_MASK 0xFF 30 31 #define BUILD_RING_BASE_ADDR(addr, size) \ 32 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) 33 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 34 ADF_CSR_RD(csr_base_addr, \ 35 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \ 36 ((ring) << 2)) 37 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 38 ADF_CSR_RD(csr_base_addr, \ 39 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \ 40 ((ring) << 2)) 41 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 42 ADF_CSR_RD(csr_base_addr, \ 43 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT) 44 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 45 ADF_CSR_WR(csr_base_addr, \ 46 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 47 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), \ 48 value) 49 50 static inline uint64_t 51 read_base(struct resource *csr_base_addr, u32 bank, u32 ring) 52 { 53 u32 l_base, u_base; 54 u64 addr; 55 56 l_base = ADF_CSR_RD(csr_base_addr, 57 (ADF_RING_BUNDLE_SIZE * bank) + 58 ADF_RING_CSR_RING_LBASE + (ring << 2)); 59 u_base = ADF_CSR_RD(csr_base_addr, 60 (ADF_RING_BUNDLE_SIZE * bank) + 61 ADF_RING_CSR_RING_UBASE + (ring << 2)); 62 63 addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL; 64 addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL; 65 66 return addr; 67 } 68 69 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ 70 read_base(csr_base_addr, bank, ring) 71 72 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 73 do { \ 74 u32 l_base = 0, u_base = 0; \ 75 l_base = (u32)((value)&0xFFFFFFFF); \ 76 u_base = (u32)(((value)&0xFFFFFFFF00000000ULL) >> 32); \ 77 ADF_CSR_WR(csr_base_addr, \ 78 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 79 ADF_RING_CSR_RING_LBASE + ((ring) << 2), \ 80 l_base); \ 81 ADF_CSR_WR(csr_base_addr, \ 82 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 83 ADF_RING_CSR_RING_UBASE + ((ring) << 2), \ 84 u_base); \ 85 } while (0) 86 87 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 88 ADF_CSR_WR(csr_base_addr, \ 89 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \ 90 ((ring) << 2), \ 91 value) 92 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 93 ADF_CSR_WR(csr_base_addr, \ 94 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \ 95 ((ring) << 2), \ 96 value) 97 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 98 ADF_CSR_WR(csr_base_addr, \ 99 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \ 100 value) 101 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 102 do { \ 103 ADF_CSR_WR(csr_base_addr, \ 104 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 105 ADF_RING_CSR_INT_SRCSEL, \ 106 ADF_BANK_INT_SRC_SEL_MASK_0); \ 107 ADF_CSR_WR(csr_base_addr, \ 108 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 109 ADF_RING_CSR_INT_SRCSEL_2, \ 110 ADF_BANK_INT_SRC_SEL_MASK_X); \ 111 } while (0) 112 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 113 ADF_CSR_WR(csr_base_addr, \ 114 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_EN, \ 115 value) 116 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 117 ADF_CSR_WR(csr_base_addr, \ 118 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_CTL, \ 119 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 120 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 121 ADF_CSR_WR(csr_base_addr, \ 122 (ADF_RING_BUNDLE_SIZE * (bank)) + \ 123 ADF_RING_CSR_INT_FLAG_AND_COL, \ 124 value) 125 126 /* AE to function map */ 127 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190) 128 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310) 129 #define AE2FUNCTION_MAP_REG_SIZE 4 130 #define AE2FUNCTION_MAP_VALID BIT(7) 131 132 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \ 133 ADF_CSR_RD(pmisc_bar_addr, \ 134 AE2FUNCTION_MAP_A_OFFSET + \ 135 AE2FUNCTION_MAP_REG_SIZE * (index)) 136 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ 137 ADF_CSR_WR(pmisc_bar_addr, \ 138 AE2FUNCTION_MAP_A_OFFSET + \ 139 AE2FUNCTION_MAP_REG_SIZE * (index), \ 140 value) 141 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \ 142 ADF_CSR_RD(pmisc_bar_addr, \ 143 AE2FUNCTION_MAP_B_OFFSET + \ 144 AE2FUNCTION_MAP_REG_SIZE * (index)) 145 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ 146 ADF_CSR_WR(pmisc_bar_addr, \ 147 AE2FUNCTION_MAP_B_OFFSET + \ 148 AE2FUNCTION_MAP_REG_SIZE * (index), \ 149 value) 150 151 /* Admin Interface Offsets */ 152 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 153 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 154 #define ADF_MAILBOX_BASE_OFFSET 0x20970 155 156 /* Arbiter configuration */ 157 #define ADF_ARB_OFFSET 0x30000 158 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180 159 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 160 #define ADF_ARB_REG_SLOT 0x1000 161 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C 162 163 #define READ_CSR_RING_SRV_ARB_EN(csr_addr, index) \ 164 ADF_CSR_RD(csr_addr, \ 165 ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index))) 166 167 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \ 168 ADF_CSR_WR(csr_addr, \ 169 ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * (index)), \ 170 value) 171 172 /* Power gating */ 173 #define ADF_POWERGATE_DC BIT(23) 174 #define ADF_POWERGATE_PKE BIT(24) 175 176 /* Default ring mapping */ 177 #define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \ 178 (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \ 179 CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ 180 UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ 181 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT) 182 183 /* Error detection and correction */ 184 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818) 185 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960) 186 #define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28) 187 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 188 #define ADF_GEN2_UERRSSMSH(i) ((i)*0x4000 + 0x18) 189 #define ADF_GEN2_CERRSSMSH(i) ((i)*0x4000 + 0x10) 190 #define ADF_GEN2_ERRSSMSH_EN BIT(3) 191 192 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND) 193 194 void adf_gen2_init_hw_csr_info(struct adf_hw_csr_info *csr_info); 195 196 #endif 197