1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef ADF_CFG_COMMON_H_ 5 #define ADF_CFG_COMMON_H_ 6 7 #include <sys/types.h> 8 #include <sys/ioccom.h> 9 #include <sys/cpuset.h> 10 11 #define ADF_CFG_MAX_STR_LEN 128 12 #define ADF_CFG_MAX_KEY_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN 13 /* 14 * Max value length increased to 128 to support more length of values. 15 * like Dc0CoreAffinity = 0, 1, 2,... config values to max cores 16 */ 17 #define ADF_CFG_MAX_VAL_LEN_IN_BYTES 128 18 #define ADF_CFG_MAX_SECTION_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN 19 #define ADF_CFG_NULL_TERM_SIZE 1 20 #define ADF_CFG_BASE_DEC 10 21 #define ADF_CFG_BASE_HEX 16 22 #define ADF_CFG_ALL_DEVICES 0xFFFE 23 #define ADF_CFG_NO_DEVICE 0xFFFF 24 #define ADF_CFG_AFFINITY_WHATEVER 0xFF 25 #define MAX_DEVICE_NAME_SIZE 32 26 #define ADF_MAX_DEVICES (32 * 32) 27 #define ADF_MAX_ACCELENGINES 12 28 #define ADF_CFG_STORAGE_ENABLED 1 29 #define ADF_DEVS_ARRAY_SIZE BITS_TO_LONGS(ADF_MAX_DEVICES) 30 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x3000000 31 #define ADF_WDT_TIMER_SYM_COMP_MS 3 32 #define ADF_MIN_HB_TIMER_MS 100 33 #define ADF_CFG_MAX_NUM_OF_SECTIONS 16 34 #define ADF_CFG_MAX_NUM_OF_TOKENS 16 35 #define ADF_CFG_MAX_TOKENS_IN_CONFIG 8 36 #define ADF_CFG_RESP_POLL 1 37 #define ADF_CFG_RESP_EPOLL 2 38 #define ADF_CFG_DEF_CY_RING_ASYM_SIZE 64 39 #define ADF_CFG_DEF_CY_RING_SYM_SIZE 512 40 #define ADF_CFG_DEF_DC_RING_SIZE 512 41 #define ADF_CFG_MAX_CORE_NUM 256 42 #define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM 43 #define ADF_CFG_MAX_TOKEN_LEN 10 44 #define ADF_CFG_ACCEL_DEF_COALES 1 45 #define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000 46 #define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0 47 #define ADF_CFG_ASYM_SRV_MASK 1 48 #define ADF_CFG_SYM_SRV_MASK 2 49 #define ADF_CFG_DC_SRV_MASK 8 50 #define ADF_CFG_UNKNOWN_SRV_MASK 0 51 #define ADF_CFG_DEF_ASYM_MASK 0x03 52 #define ADF_CFG_MAX_SERVICES 4 53 #define ADF_MAX_SERVICES 3 54 55 enum adf_svc_type { 56 ADF_SVC_ASYM = 0, 57 ADF_SVC_SYM = 1, 58 ADF_SVC_DC = 2, 59 ADF_SVC_NONE = 3 60 }; 61 62 struct adf_pci_address { 63 unsigned char bus; 64 unsigned char dev; 65 unsigned char func; 66 } __packed; 67 68 #define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0 69 #define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3 70 #define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6 71 #define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9 72 73 enum adf_cfg_service_type { NA = 0, CRYPTO, COMP, SYM, ASYM, USED }; 74 75 enum adf_cfg_bundle_type { FREE, KERNEL, USER }; 76 77 enum adf_cfg_val_type { ADF_DEC, ADF_HEX, ADF_STR }; 78 79 enum adf_device_type { 80 DEV_UNKNOWN = 0, 81 DEV_DH895XCC, 82 DEV_DH895XCCVF, 83 DEV_C62X, 84 DEV_C62XVF, 85 DEV_C3XXX, 86 DEV_C3XXXVF, 87 DEV_200XX, 88 DEV_200XXVF, 89 DEV_C4XXX, 90 DEV_C4XXXVF 91 }; 92 93 enum adf_cfg_fw_image_type { 94 ADF_FW_IMAGE_DEFAULT = 0, 95 ADF_FW_IMAGE_CRYPTO, 96 ADF_FW_IMAGE_COMPRESSION, 97 ADF_FW_IMAGE_CUSTOM1 98 }; 99 100 struct adf_dev_status_info { 101 enum adf_device_type type; 102 uint16_t accel_id; 103 uint16_t instance_id; 104 uint8_t num_ae; 105 uint8_t num_accel; 106 uint8_t num_logical_accel; 107 uint8_t banks_per_accel; 108 uint8_t state; 109 uint8_t bus; 110 uint8_t dev; 111 uint8_t fun; 112 int domain; 113 char name[MAX_DEVICE_NAME_SIZE]; 114 u8 sku; 115 u32 node_id; 116 u32 device_mem_available; 117 u32 pci_device_id; 118 }; 119 120 struct adf_cfg_device { 121 /* contains all the bundles info */ 122 struct adf_cfg_bundle **bundles; 123 /* contains all the instances info */ 124 struct adf_cfg_instance **instances; 125 int bundle_num; 126 int instance_index; 127 char name[ADF_CFG_MAX_STR_LEN]; 128 int dev_id; 129 int max_kernel_bundle_nr; 130 u16 total_num_inst; 131 }; 132 133 enum adf_accel_serv_type { 134 ADF_ACCEL_SERV_NA = 0x0, 135 ADF_ACCEL_SERV_ASYM, 136 ADF_ACCEL_SERV_SYM, 137 ADF_ACCEL_SERV_RND, 138 ADF_ACCEL_SERV_DC 139 }; 140 141 struct adf_cfg_ring { 142 u8 mode : 1; 143 enum adf_accel_serv_type serv_type; 144 u8 number : 4; 145 }; 146 147 struct adf_cfg_bundle { 148 /* Section(s) name this bundle is shared by */ 149 char **sections; 150 int max_section; 151 int section_index; 152 int number; 153 enum adf_cfg_bundle_type type; 154 cpuset_t affinity_mask; 155 int polling_mode; 156 int instance_num; 157 int num_of_rings; 158 /* contains all the info about rings */ 159 struct adf_cfg_ring **rings; 160 u16 in_use; 161 }; 162 163 struct adf_cfg_instance { 164 enum adf_cfg_service_type stype; 165 char name[ADF_CFG_MAX_STR_LEN]; 166 int polling_mode; 167 cpuset_t affinity_mask; 168 /* rings within an instance for services */ 169 int asym_tx; 170 int asym_rx; 171 int sym_tx; 172 int sym_rx; 173 int dc_tx; 174 int dc_rx; 175 int bundle; 176 }; 177 178 #define ADF_CFG_MAX_CORE_NUM 256 179 #define ADF_CFG_MAX_TOKENS_IN_CONFIG 8 180 #define ADF_CFG_MAX_TOKEN_LEN 10 181 #define ADF_CFG_MAX_TOKENS ADF_CFG_MAX_CORE_NUM 182 #define ADF_CFG_ACCEL_DEF_COALES 1 183 #define ADF_CFG_ACCEL_DEF_COALES_TIMER 10000 184 #define ADF_CFG_ACCEL_DEF_COALES_NUM_MSG 0 185 #define ADF_CFG_RESP_EPOLL 2 186 #define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3 187 #define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6 188 #define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9 189 #define ADF_CFG_RESP_POLL 1 190 #define ADF_CFG_ASYM_SRV_MASK 1 191 #define ADF_CFG_SYM_SRV_MASK 2 192 #define ADF_CFG_DC_SRV_MASK 8 193 #define ADF_CFG_UNKNOWN_SRV_MASK 0 194 #define ADF_CFG_DEF_ASYM_MASK 0x03 195 #define ADF_CFG_MAX_SERVICES 4 196 197 #define ADF_CFG_HB_DEFAULT_VALUE 500 198 #define ADF_CFG_HB_COUNT_THRESHOLD 3 199 #define ADF_MIN_HB_TIMER_MS 100 200 201 enum adf_device_heartbeat_status { 202 DEV_HB_UNRESPONSIVE = 0, 203 DEV_HB_ALIVE, 204 DEV_HB_UNSUPPORTED 205 }; 206 207 struct adf_dev_heartbeat_status_ctl { 208 uint16_t device_id; 209 enum adf_device_heartbeat_status status; 210 }; 211 #endif 212