xref: /freebsd/sys/dev/qat/include/common/adf_accel_devices.h (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
3 /* $FreeBSD$ */
4 #ifndef ADF_ACCEL_DEVICES_H_
5 #define ADF_ACCEL_DEVICES_H_
6 
7 #include "qat_freebsd.h"
8 #include "adf_cfg_common.h"
9 
10 #define ADF_CFG_NUM_SERVICES 4
11 
12 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
13 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
14 #define ADF_C62X_DEVICE_NAME "c6xx"
15 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
16 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
17 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
18 #define ADF_200XX_DEVICE_NAME "200xx"
19 #define ADF_200XXVF_DEVICE_NAME "200xxvf"
20 #define ADF_C4XXX_DEVICE_NAME "c4xxx"
21 #define ADF_C4XXXVF_DEVICE_NAME "c4xxxvf"
22 #define ADF_DH895XCC_PCI_DEVICE_ID 0x435
23 #define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443
24 #define ADF_C62X_PCI_DEVICE_ID 0x37c8
25 #define ADF_C62XIOV_PCI_DEVICE_ID 0x37c9
26 #define ADF_C3XXX_PCI_DEVICE_ID 0x19e2
27 #define ADF_C3XXXIOV_PCI_DEVICE_ID 0x19e3
28 #define ADF_200XX_PCI_DEVICE_ID 0x18ee
29 #define ADF_200XXIOV_PCI_DEVICE_ID 0x18ef
30 #define ADF_D15XX_PCI_DEVICE_ID 0x6f54
31 #define ADF_D15XXIOV_PCI_DEVICE_ID 0x6f55
32 #define ADF_C4XXX_PCI_DEVICE_ID 0x18a0
33 #define ADF_C4XXXIOV_PCI_DEVICE_ID 0x18a1
34 
35 #define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); })
36 #define ADF_VF2PF_SET_SIZE 32
37 #define ADF_MAX_VF2PF_SET 4
38 #define ADF_VF2PF_SET_OFFSET(set_nr) ((set_nr)*ADF_VF2PF_SET_SIZE)
39 #define ADF_VF2PF_VFNR_TO_SET(vf_nr) ((vf_nr) / ADF_VF2PF_SET_SIZE)
40 #define ADF_VF2PF_VFNR_TO_MASK(vf_nr)                                          \
41 	({                                                                     \
42 		u32 vf_nr_ = (vf_nr);                                          \
43 		BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET(        \
44 		    vf_nr_));                                                  \
45 	})
46 
47 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
48 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
49 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
50 #define ADF_PCI_MAX_BARS 3
51 #define ADF_DEVICE_NAME_LENGTH 32
52 #define ADF_ETR_MAX_RINGS_PER_BANK 16
53 #define ADF_MAX_MSIX_VECTOR_NAME 16
54 #define ADF_DEVICE_NAME_PREFIX "qat_"
55 #define ADF_STOP_RETRY 50
56 #define ADF_NUM_THREADS_PER_AE (8)
57 #define ADF_AE_ADMIN_THREAD (7)
58 #define ADF_NUM_PKE_STRAND (2)
59 #define ADF_AE_STRAND0_THREAD (8)
60 #define ADF_AE_STRAND1_THREAD (9)
61 #define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND)
62 #define ADF_CFG_NUM_SERVICES 4
63 #define ADF_SRV_TYPE_BIT_LEN 3
64 #define ADF_SRV_TYPE_MASK 0x7
65 #define ADF_RINGS_PER_SRV_TYPE 2
66 #define ADF_THRD_ABILITY_BIT_LEN 4
67 #define ADF_THRD_ABILITY_MASK 0xf
68 #define ADF_VF_OFFSET 0x8
69 #define ADF_MAX_FUNC_PER_DEV 0x7
70 #define ADF_PCI_DEV_OFFSET 0x3
71 
72 #define ADF_SRV_TYPE_BIT_LEN 3
73 #define ADF_SRV_TYPE_MASK 0x7
74 
75 #define GET_SRV_TYPE(ena_srv_mask, srv)                                        \
76 	(((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK)
77 
78 #define ADF_DEFAULT_RING_TO_SRV_MAP                                            \
79 	(CRYPTO | CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT |                   \
80 	 NA << ADF_CFG_SERV_RING_PAIR_2_SHIFT |                                \
81 	 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
82 
83 enum adf_accel_capabilities {
84 	ADF_ACCEL_CAPABILITIES_NULL = 0,
85 	ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
86 	ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
87 	ADF_ACCEL_CAPABILITIES_CIPHER = 4,
88 	ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
89 	ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
90 	ADF_ACCEL_CAPABILITIES_DEPRECATED = 64,
91 	ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
92 };
93 
94 struct adf_bar {
95 	rman_res_t base_addr;
96 	struct resource *virt_addr;
97 	rman_res_t size;
98 } __packed;
99 
100 struct adf_accel_msix {
101 	struct msix_entry *entries;
102 	u32 num_entries;
103 } __packed;
104 
105 struct adf_accel_pci {
106 	device_t pci_dev;
107 	struct adf_accel_msix msix_entries;
108 	struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
109 	uint8_t revid;
110 	uint8_t sku;
111 	int node;
112 } __packed;
113 
114 enum dev_state { DEV_DOWN = 0, DEV_UP };
115 
116 enum dev_sku_info {
117 	DEV_SKU_1 = 0,
118 	DEV_SKU_2,
119 	DEV_SKU_3,
120 	DEV_SKU_4,
121 	DEV_SKU_VF,
122 	DEV_SKU_1_CY,
123 	DEV_SKU_2_CY,
124 	DEV_SKU_3_CY,
125 	DEV_SKU_UNKNOWN
126 };
127 
128 static inline const char *
129 get_sku_info(enum dev_sku_info info)
130 {
131 	switch (info) {
132 	case DEV_SKU_1:
133 		return "SKU1";
134 	case DEV_SKU_1_CY:
135 		return "SKU1CY";
136 	case DEV_SKU_2:
137 		return "SKU2";
138 	case DEV_SKU_2_CY:
139 		return "SKU2CY";
140 	case DEV_SKU_3:
141 		return "SKU3";
142 	case DEV_SKU_3_CY:
143 		return "SKU3CY";
144 	case DEV_SKU_4:
145 		return "SKU4";
146 	case DEV_SKU_VF:
147 		return "SKUVF";
148 	case DEV_SKU_UNKNOWN:
149 	default:
150 		break;
151 	}
152 	return "Unknown SKU";
153 }
154 
155 enum adf_accel_unit_services {
156 	ADF_ACCEL_SERVICE_NULL = 0,
157 	ADF_ACCEL_INLINE_CRYPTO = 1,
158 	ADF_ACCEL_CRYPTO = 2,
159 	ADF_ACCEL_COMPRESSION = 4
160 };
161 
162 struct adf_ae_info {
163 	u32 num_asym_thd;
164 	u32 num_sym_thd;
165 	u32 num_dc_thd;
166 } __packed;
167 
168 struct adf_accel_unit {
169 	u8 au_mask;
170 	u32 accel_mask;
171 	u64 ae_mask;
172 	u64 comp_ae_mask;
173 	u32 num_ae;
174 	enum adf_accel_unit_services services;
175 } __packed;
176 
177 struct adf_accel_unit_info {
178 	u32 inline_ingress_msk;
179 	u32 inline_egress_msk;
180 	u32 sym_ae_msk;
181 	u32 asym_ae_msk;
182 	u32 dc_ae_msk;
183 	u8 num_cy_au;
184 	u8 num_dc_au;
185 	u8 num_inline_au;
186 	struct adf_accel_unit *au;
187 	const struct adf_ae_info *ae_info;
188 } __packed;
189 
190 struct adf_hw_aram_info {
191 	/* Inline Egress mask. "1" = AE is working with egress traffic */
192 	u32 inline_direction_egress_mask;
193 	/* Inline congestion managmenet profiles set in config file */
194 	u32 inline_congest_mngt_profile;
195 	/* Initialise CY AE mask, "1" = AE is used for CY operations */
196 	u32 cy_ae_mask;
197 	/* Initialise DC AE mask, "1" = AE is used for DC operations */
198 	u32 dc_ae_mask;
199 	/* Number of long words used to define the ARAM regions */
200 	u32 num_aram_lw_entries;
201 	/* ARAM region definitions */
202 	u32 mmp_region_size;
203 	u32 mmp_region_offset;
204 	u32 skm_region_size;
205 	u32 skm_region_offset;
206 	/*
207 	 * Defines size and offset of compression intermediate buffers stored
208 	 * in ARAM (device's on-chip memory).
209 	 */
210 	u32 inter_buff_aram_region_size;
211 	u32 inter_buff_aram_region_offset;
212 	u32 sadb_region_size;
213 	u32 sadb_region_offset;
214 } __packed;
215 
216 struct adf_hw_device_class {
217 	const char *name;
218 	const enum adf_device_type type;
219 	uint32_t instances;
220 } __packed;
221 
222 struct arb_info {
223 	u32 arbiter_offset;
224 	u32 wrk_thd_2_srv_arb_map;
225 	u32 wrk_cfg_offset;
226 } __packed;
227 
228 struct admin_info {
229 	u32 admin_msg_ur;
230 	u32 admin_msg_lr;
231 	u32 mailbox_offset;
232 } __packed;
233 
234 struct adf_cfg_device_data;
235 struct adf_accel_dev;
236 struct adf_etr_data;
237 struct adf_etr_ring_data;
238 
239 struct adf_hw_device_data {
240 	struct adf_hw_device_class *dev_class;
241 	uint32_t (*get_accel_mask)(struct adf_accel_dev *accel_dev);
242 	uint32_t (*get_ae_mask)(struct adf_accel_dev *accel_dev);
243 	uint32_t (*get_sram_bar_id)(struct adf_hw_device_data *self);
244 	uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self);
245 	uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self);
246 	uint32_t (*get_num_aes)(struct adf_hw_device_data *self);
247 	uint32_t (*get_num_accels)(struct adf_hw_device_data *self);
248 	void (*notify_and_wait_ethernet)(struct adf_accel_dev *accel_dev);
249 	bool (*get_eth_doorbell_msg)(struct adf_accel_dev *accel_dev);
250 	uint32_t (*get_pf2vf_offset)(uint32_t i);
251 	uint32_t (*get_vintmsk_offset)(uint32_t i);
252 	u32 (*get_vintsou_offset)(void);
253 	void (*get_arb_info)(struct arb_info *arb_csrs_info);
254 	void (*get_admin_info)(struct admin_info *admin_csrs_info);
255 	void (*get_errsou_offset)(u32 *errsou3, u32 *errsou5);
256 	uint32_t (*get_num_accel_units)(struct adf_hw_device_data *self);
257 	int (*init_accel_units)(struct adf_accel_dev *accel_dev);
258 	void (*exit_accel_units)(struct adf_accel_dev *accel_dev);
259 	uint32_t (*get_clock_speed)(struct adf_hw_device_data *self);
260 	enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
261 	bool (*check_prod_sku)(struct adf_accel_dev *accel_dev);
262 	int (*alloc_irq)(struct adf_accel_dev *accel_dev);
263 	void (*free_irq)(struct adf_accel_dev *accel_dev);
264 	void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
265 	int (*check_uncorrectable_error)(struct adf_accel_dev *accel_dev);
266 	void (*print_err_registers)(struct adf_accel_dev *accel_dev);
267 	void (*disable_error_interrupts)(struct adf_accel_dev *accel_dev);
268 	int (*init_ras)(struct adf_accel_dev *accel_dev);
269 	void (*exit_ras)(struct adf_accel_dev *accel_dev);
270 	void (*disable_arb)(struct adf_accel_dev *accel_dev);
271 	void (*update_ras_errors)(struct adf_accel_dev *accel_dev, int error);
272 	bool (*ras_interrupts)(struct adf_accel_dev *accel_dev,
273 			       bool *reset_required);
274 	int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
275 	void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
276 	int (*send_admin_init)(struct adf_accel_dev *accel_dev);
277 	void (*set_asym_rings_mask)(struct adf_accel_dev *accel_dev);
278 	int (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev,
279 				   u16 *ring_to_svc_map);
280 	uint32_t (*get_accel_cap)(struct adf_accel_dev *accel_dev);
281 	int (*init_arb)(struct adf_accel_dev *accel_dev);
282 	void (*exit_arb)(struct adf_accel_dev *accel_dev);
283 	void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
284 				const uint32_t **cfg);
285 	int (*get_heartbeat_status)(struct adf_accel_dev *accel_dev);
286 	uint32_t (*get_ae_clock)(struct adf_hw_device_data *self);
287 	void (*disable_iov)(struct adf_accel_dev *accel_dev);
288 	void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
289 				      bool enable);
290 	void (*enable_ints)(struct adf_accel_dev *accel_dev);
291 	bool (*check_slice_hang)(struct adf_accel_dev *accel_dev);
292 	int (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
293 	int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
294 	int (*disable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
295 	void (*reset_device)(struct adf_accel_dev *accel_dev);
296 	void (*reset_hw_units)(struct adf_accel_dev *accel_dev);
297 	int (*measure_clock)(struct adf_accel_dev *accel_dev);
298 	void (*restore_device)(struct adf_accel_dev *accel_dev);
299 	uint32_t (*get_obj_cfg_ae_mask)(struct adf_accel_dev *accel_dev,
300 					enum adf_accel_unit_services services);
301 	int (*add_pke_stats)(struct adf_accel_dev *accel_dev);
302 	void (*remove_pke_stats)(struct adf_accel_dev *accel_dev);
303 	int (*add_misc_error)(struct adf_accel_dev *accel_dev);
304 	int (*count_ras_event)(struct adf_accel_dev *accel_dev,
305 			       u32 *ras_event,
306 			       char *aeidstr);
307 	void (*remove_misc_error)(struct adf_accel_dev *accel_dev);
308 	int (*configure_accel_units)(struct adf_accel_dev *accel_dev);
309 	uint32_t (*get_objs_num)(struct adf_accel_dev *accel_dev);
310 	const char *(*get_obj_name)(struct adf_accel_dev *accel_dev,
311 				    enum adf_accel_unit_services services);
312 	void (*pre_reset)(struct adf_accel_dev *accel_dev);
313 	void (*post_reset)(struct adf_accel_dev *accel_dev);
314 	const char *fw_name;
315 	const char *fw_mmp_name;
316 	bool reset_ack;
317 	uint32_t fuses;
318 	uint32_t accel_capabilities_mask;
319 	uint32_t instance_id;
320 	uint16_t accel_mask;
321 	u32 aerucm_mask;
322 	u32 ae_mask;
323 	u32 service_mask;
324 	uint16_t tx_rings_mask;
325 	uint8_t tx_rx_gap;
326 	uint8_t num_banks;
327 	u8 num_rings_per_bank;
328 	uint8_t num_accel;
329 	uint8_t num_logical_accel;
330 	uint8_t num_engines;
331 	uint8_t min_iov_compat_ver;
332 	int (*get_storage_enabled)(struct adf_accel_dev *accel_dev,
333 				   uint32_t *storage_enabled);
334 	u8 query_storage_cap;
335 	u32 clock_frequency;
336 	u8 storage_enable;
337 	u32 extended_dc_capabilities;
338 	int (*config_device)(struct adf_accel_dev *accel_dev);
339 	u16 asym_rings_mask;
340 	int (*get_fw_image_type)(struct adf_accel_dev *accel_dev,
341 				 enum adf_cfg_fw_image_type *fw_image_type);
342 	u16 ring_to_svc_map;
343 } __packed;
344 
345 /* helper enum for performing CSR operations */
346 enum operation {
347 	AND,
348 	OR,
349 };
350 
351 /* 32-bit CSR write macro */
352 #define ADF_CSR_WR(csr_base, csr_offset, val)                                  \
353 	bus_write_4(csr_base, csr_offset, val)
354 
355 /* 64-bit CSR write macro */
356 #ifdef __x86_64__
357 #define ADF_CSR_WR64(csr_base, csr_offset, val)                                \
358 	bus_write_8(csr_base, csr_offset, val)
359 #else
360 static __inline void
361 adf_csr_wr64(struct resource *csr_base, bus_size_t offset, uint64_t value)
362 {
363 	bus_write_4(csr_base, offset, (uint32_t)value);
364 	bus_write_4(csr_base, offset + 4, (uint32_t)(value >> 32));
365 }
366 #define ADF_CSR_WR64(csr_base, csr_offset, val)                                \
367 	adf_csr_wr64(csr_base, csr_offset, val)
368 #endif
369 
370 /* 32-bit CSR read macro */
371 #define ADF_CSR_RD(csr_base, csr_offset) bus_read_4(csr_base, csr_offset)
372 
373 /* 64-bit CSR read macro */
374 #ifdef __x86_64__
375 #define ADF_CSR_RD64(csr_base, csr_offset) bus_read_8(csr_base, csr_offset)
376 #else
377 static __inline uint64_t
378 adf_csr_rd64(struct resource *csr_base, bus_size_t offset)
379 {
380 	return (((uint64_t)bus_read_4(csr_base, offset)) |
381 		(((uint64_t)bus_read_4(csr_base, offset + 4)) << 32));
382 }
383 #define ADF_CSR_RD64(csr_base, csr_offset) adf_csr_rd64(csr_base, csr_offset)
384 #endif
385 
386 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev)
387 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
388 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
389 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
390 #define GET_DEV_SKU(accel_dev) (accel_dev->accel_pci_dev.sku)
391 #define GET_NUM_RINGS_PER_BANK(accel_dev)                                      \
392 	(GET_HW_DATA(accel_dev)->num_rings_per_bank)
393 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
394 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
395 #define GET_SRV_TYPE(ena_srv_mask, srv)                                        \
396 	(((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK)
397 #define SET_ASYM_MASK(asym_mask, srv)                                          \
398 	({                                                                     \
399 		typeof(srv) srv_ = (srv);                                      \
400 		(asym_mask) |= ((1 << (srv_)*ADF_RINGS_PER_SRV_TYPE) |         \
401 				(1 << ((srv_)*ADF_RINGS_PER_SRV_TYPE + 1)));   \
402 	})
403 
404 #define GET_NUM_RINGS_PER_BANK(accel_dev)                                      \
405 	(GET_HW_DATA(accel_dev)->num_rings_per_bank)
406 #define GET_MAX_PROCESSES(accel_dev)                                           \
407 	({                                                                     \
408 		typeof(accel_dev) dev = (accel_dev);                           \
409 		(GET_MAX_BANKS(dev) * (GET_NUM_RINGS_PER_BANK(dev) / 2));      \
410 	})
411 #define GET_DU_TABLE(accel_dev) (accel_dev->du_table)
412 
413 static inline void
414 adf_csr_fetch_and_and(struct resource *csr, size_t offs, unsigned long mask)
415 {
416 	unsigned int val = ADF_CSR_RD(csr, offs);
417 
418 	val &= mask;
419 	ADF_CSR_WR(csr, offs, val);
420 }
421 
422 static inline void
423 adf_csr_fetch_and_or(struct resource *csr, size_t offs, unsigned long mask)
424 {
425 	unsigned int val = ADF_CSR_RD(csr, offs);
426 
427 	val |= mask;
428 	ADF_CSR_WR(csr, offs, val);
429 }
430 
431 static inline void
432 adf_csr_fetch_and_update(enum operation op,
433 			 struct resource *csr,
434 			 size_t offs,
435 			 unsigned long mask)
436 {
437 	switch (op) {
438 	case AND:
439 		adf_csr_fetch_and_and(csr, offs, mask);
440 		break;
441 	case OR:
442 		adf_csr_fetch_and_or(csr, offs, mask);
443 		break;
444 	}
445 }
446 
447 struct pfvf_stats {
448 	struct dentry *stats_file;
449 	/* Messages put in CSR */
450 	unsigned int tx;
451 	/* Messages read from CSR */
452 	unsigned int rx;
453 	/* Interrupt fired but int bit was clear */
454 	unsigned int spurious;
455 	/* Block messages sent */
456 	unsigned int blk_tx;
457 	/* Block messages received */
458 	unsigned int blk_rx;
459 	/* Blocks received with CRC errors */
460 	unsigned int crc_err;
461 	/* CSR in use by other side */
462 	unsigned int busy;
463 	/* Receiver did not acknowledge */
464 	unsigned int no_ack;
465 	/* Collision detected */
466 	unsigned int collision;
467 	/* Couldn't send a response */
468 	unsigned int tx_timeout;
469 	/* Didn't receive a response */
470 	unsigned int rx_timeout;
471 	/* Responses received */
472 	unsigned int rx_rsp;
473 	/* Messages re-transmitted */
474 	unsigned int retry;
475 	/* Event put timeout */
476 	unsigned int event_timeout;
477 };
478 
479 #define NUM_PFVF_COUNTERS 14
480 
481 void adf_get_admin_info(struct admin_info *admin_csrs_info);
482 struct adf_admin_comms {
483 	bus_addr_t phy_addr;
484 	bus_addr_t const_tbl_addr;
485 	bus_addr_t aram_map_phys_addr;
486 	bus_addr_t phy_hb_addr;
487 	bus_dmamap_t aram_map;
488 	bus_dmamap_t const_tbl_map;
489 	bus_dmamap_t hb_map;
490 	char *virt_addr;
491 	char *virt_hb_addr;
492 	struct resource *mailbox_addr;
493 	struct sx lock;
494 	struct bus_dmamem dma_mem;
495 	struct bus_dmamem dma_hb;
496 };
497 
498 struct icp_qat_fw_loader_handle;
499 struct adf_fw_loader_data {
500 	struct icp_qat_fw_loader_handle *fw_loader;
501 	const struct firmware *uof_fw;
502 	const struct firmware *mmp_fw;
503 };
504 
505 struct adf_accel_vf_info {
506 	struct adf_accel_dev *accel_dev;
507 	struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
508 	u32 vf_nr;
509 	bool init;
510 	u8 compat_ver;
511 	struct pfvf_stats pfvf_counters;
512 };
513 
514 struct adf_fw_versions {
515 	u8 fw_version_major;
516 	u8 fw_version_minor;
517 	u8 fw_version_patch;
518 	u8 mmp_version_major;
519 	u8 mmp_version_minor;
520 	u8 mmp_version_patch;
521 };
522 
523 #define ADF_COMPAT_CHECKER_MAX 8
524 typedef int (*adf_iov_compat_checker_t)(struct adf_accel_dev *accel_dev,
525 					u8 vf_compat_ver);
526 struct adf_accel_compat_manager {
527 	u8 num_chker;
528 	adf_iov_compat_checker_t iov_compat_checkers[ADF_COMPAT_CHECKER_MAX];
529 };
530 
531 struct adf_heartbeat;
532 struct adf_accel_dev {
533 	struct adf_hw_aram_info *aram_info;
534 	struct adf_accel_unit_info *au_info;
535 	struct adf_etr_data *transport;
536 	struct adf_hw_device_data *hw_device;
537 	struct adf_cfg_device_data *cfg;
538 	struct adf_fw_loader_data *fw_loader;
539 	struct adf_admin_comms *admin;
540 	struct adf_heartbeat *heartbeat;
541 	struct adf_fw_versions fw_versions;
542 	unsigned int autoreset_on_error;
543 	struct adf_fw_counters_data *fw_counters_data;
544 	struct sysctl_oid *debugfs_ae_config;
545 	struct list_head crypto_list;
546 	atomic_t *ras_counters;
547 	unsigned long status;
548 	atomic_t ref_count;
549 	bus_dma_tag_t dma_tag;
550 	struct sysctl_ctx_list sysctl_ctx;
551 	struct sysctl_oid *ras_correctable;
552 	struct sysctl_oid *ras_uncorrectable;
553 	struct sysctl_oid *ras_fatal;
554 	struct sysctl_oid *ras_reset;
555 	struct sysctl_oid *pke_replay_dbgfile;
556 	struct sysctl_oid *misc_error_dbgfile;
557 	struct list_head list;
558 	struct adf_accel_pci accel_pci_dev;
559 	struct adf_accel_compat_manager *cm;
560 	u8 compat_ver;
561 	union {
562 		struct {
563 			/* vf_info is non-zero when SR-IOV is init'ed */
564 			struct adf_accel_vf_info *vf_info;
565 			int num_vfs;
566 		} pf;
567 		struct {
568 			struct resource *irq;
569 			void *cookie;
570 			char *irq_name;
571 			struct task pf2vf_bh_tasklet;
572 			struct mutex vf2pf_lock; /* protect CSR access */
573 			int iov_msg_completion;
574 			uint8_t compatible;
575 			uint8_t pf_version;
576 			u8 pf2vf_block_byte;
577 			u8 pf2vf_block_resp_type;
578 			struct pfvf_stats pfvf_counters;
579 		} vf;
580 	} u1;
581 	bool is_vf;
582 	u32 accel_id;
583 	void *lac_dev;
584 };
585 #endif
586