1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 45 #include <dev/pci/pcivar.h> 46 47 #include <dev/puc/puc_bus.h> 48 #include <dev/puc/puc_cfg.h> 49 #include <dev/puc/puc_bfe.h> 50 51 static puc_config_f puc_config_amc; 52 static puc_config_f puc_config_diva; 53 static puc_config_f puc_config_exar; 54 static puc_config_f puc_config_exar_pcie; 55 static puc_config_f puc_config_icbook; 56 static puc_config_f puc_config_moxa; 57 static puc_config_f puc_config_oxford_pci954; 58 static puc_config_f puc_config_oxford_pcie; 59 static puc_config_f puc_config_quatech; 60 static puc_config_f puc_config_syba; 61 static puc_config_f puc_config_siig; 62 static puc_config_f puc_config_sunix; 63 static puc_config_f puc_config_timedia; 64 static puc_config_f puc_config_titan; 65 66 const struct puc_cfg puc_pci_devices[] = { 67 68 { 0x0009, 0x7168, 0xffff, 0, 69 "Sunix SUN1889", 70 DEFAULT_RCLK * 8, 71 PUC_PORT_2S, 0x10, 0, 8, 72 }, 73 74 { 0x103c, 0x1048, 0x103c, 0x1049, 75 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 76 DEFAULT_RCLK, 77 PUC_PORT_3S, 0x10, 0, -1, 78 .config_function = puc_config_diva 79 }, 80 81 { 0x103c, 0x1048, 0x103c, 0x104a, 82 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 83 DEFAULT_RCLK, 84 PUC_PORT_2S, 0x10, 0, -1, 85 .config_function = puc_config_diva 86 }, 87 88 { 0x103c, 0x1048, 0x103c, 0x104b, 89 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 90 DEFAULT_RCLK, 91 PUC_PORT_4S, 0x10, 0, -1, 92 .config_function = puc_config_diva 93 }, 94 95 { 0x103c, 0x1048, 0x103c, 0x1223, 96 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 97 DEFAULT_RCLK, 98 PUC_PORT_3S, 0x10, 0, -1, 99 .config_function = puc_config_diva 100 }, 101 102 { 0x103c, 0x1048, 0x103c, 0x1226, 103 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 104 DEFAULT_RCLK, 105 PUC_PORT_3S, 0x10, 0, -1, 106 .config_function = puc_config_diva 107 }, 108 109 { 0x103c, 0x1048, 0x103c, 0x1282, 110 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 111 DEFAULT_RCLK, 112 PUC_PORT_3S, 0x10, 0, -1, 113 .config_function = puc_config_diva 114 }, 115 116 { 0x10b5, 0x1076, 0x10b5, 0x1076, 117 "VScom PCI-800", 118 DEFAULT_RCLK * 8, 119 PUC_PORT_8S, 0x18, 0, 8, 120 }, 121 122 { 0x10b5, 0x1077, 0x10b5, 0x1077, 123 "VScom PCI-400", 124 DEFAULT_RCLK * 8, 125 PUC_PORT_4S, 0x18, 0, 8, 126 }, 127 128 { 0x10b5, 0x1103, 0x10b5, 0x1103, 129 "VScom PCI-200", 130 DEFAULT_RCLK * 8, 131 PUC_PORT_2S, 0x18, 4, 0, 132 }, 133 134 /* 135 * Boca Research Turbo Serial 658 (8 serial port) card. 136 * Appears to be the same as Chase Research PLC PCI-FAST8 137 * and Perle PCI-FAST8 Multi-Port serial cards. 138 */ 139 { 0x10b5, 0x9050, 0x12e0, 0x0021, 140 "Boca Research Turbo Serial 658", 141 DEFAULT_RCLK * 4, 142 PUC_PORT_8S, 0x18, 0, 8, 143 }, 144 145 { 0x10b5, 0x9050, 0x12e0, 0x0031, 146 "Boca Research Turbo Serial 654", 147 DEFAULT_RCLK * 4, 148 PUC_PORT_4S, 0x18, 0, 8, 149 }, 150 151 /* 152 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 153 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 154 * into the subsystem fields, and claims that it's a 155 * network/misc (0x02/0x80) device. 156 */ 157 { 0x10b5, 0x9050, 0xd84d, 0x6808, 158 "Dolphin Peripherals 4035", 159 DEFAULT_RCLK, 160 PUC_PORT_2S, 0x18, 4, 0, 161 }, 162 163 /* 164 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 165 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 166 * into the subsystem fields, and claims that it's a 167 * network/misc (0x02/0x80) device. 168 */ 169 { 0x10b5, 0x9050, 0xd84d, 0x6810, 170 "Dolphin Peripherals 4014", 171 0, 172 PUC_PORT_2P, 0x20, 4, 0, 173 }, 174 175 { 0x10e8, 0x818e, 0xffff, 0, 176 "Applied Micro Circuits 8 Port UART", 177 DEFAULT_RCLK, 178 PUC_PORT_8S, 0x14, -1, -1, 179 .config_function = puc_config_amc 180 }, 181 182 { 0x11fe, 0x8010, 0xffff, 0, 183 "Comtrol RocketPort 550/8 RJ11 part A", 184 DEFAULT_RCLK * 4, 185 PUC_PORT_4S, 0x10, 0, 8, 186 }, 187 188 { 0x11fe, 0x8011, 0xffff, 0, 189 "Comtrol RocketPort 550/8 RJ11 part B", 190 DEFAULT_RCLK * 4, 191 PUC_PORT_4S, 0x10, 0, 8, 192 }, 193 194 { 0x11fe, 0x8012, 0xffff, 0, 195 "Comtrol RocketPort 550/8 Octa part A", 196 DEFAULT_RCLK * 4, 197 PUC_PORT_4S, 0x10, 0, 8, 198 }, 199 200 { 0x11fe, 0x8013, 0xffff, 0, 201 "Comtrol RocketPort 550/8 Octa part B", 202 DEFAULT_RCLK * 4, 203 PUC_PORT_4S, 0x10, 0, 8, 204 }, 205 206 { 0x11fe, 0x8014, 0xffff, 0, 207 "Comtrol RocketPort 550/4 RJ45", 208 DEFAULT_RCLK * 4, 209 PUC_PORT_4S, 0x10, 0, 8, 210 }, 211 212 { 0x11fe, 0x8015, 0xffff, 0, 213 "Comtrol RocketPort 550/Quad", 214 DEFAULT_RCLK * 4, 215 PUC_PORT_4S, 0x10, 0, 8, 216 }, 217 218 { 0x11fe, 0x8016, 0xffff, 0, 219 "Comtrol RocketPort 550/16 part A", 220 DEFAULT_RCLK * 4, 221 PUC_PORT_4S, 0x10, 0, 8, 222 }, 223 224 { 0x11fe, 0x8017, 0xffff, 0, 225 "Comtrol RocketPort 550/16 part B", 226 DEFAULT_RCLK * 4, 227 PUC_PORT_12S, 0x10, 0, 8, 228 }, 229 230 { 0x11fe, 0x8018, 0xffff, 0, 231 "Comtrol RocketPort 550/8 part A", 232 DEFAULT_RCLK * 4, 233 PUC_PORT_4S, 0x10, 0, 8, 234 }, 235 236 { 0x11fe, 0x8019, 0xffff, 0, 237 "Comtrol RocketPort 550/8 part B", 238 DEFAULT_RCLK * 4, 239 PUC_PORT_4S, 0x10, 0, 8, 240 }, 241 242 /* 243 * IBM SurePOS 300 Series (481033H) serial ports 244 * Details can be found on the IBM RSS websites 245 */ 246 247 { 0x1014, 0x0297, 0xffff, 0, 248 "IBM SurePOS 300 Series (481033H) serial ports", 249 DEFAULT_RCLK, 250 PUC_PORT_4S, 0x10, 4, 0 251 }, 252 253 /* 254 * SIIG Boards. 255 * 256 * SIIG provides documentation for their boards at: 257 * <URL:http://www.siig.com/downloads.asp> 258 */ 259 260 { 0x131f, 0x1010, 0xffff, 0, 261 "SIIG Cyber I/O PCI 16C550 (10x family)", 262 DEFAULT_RCLK, 263 PUC_PORT_1S1P, 0x18, 4, 0, 264 }, 265 266 { 0x131f, 0x1011, 0xffff, 0, 267 "SIIG Cyber I/O PCI 16C650 (10x family)", 268 DEFAULT_RCLK, 269 PUC_PORT_1S1P, 0x18, 4, 0, 270 }, 271 272 { 0x131f, 0x1012, 0xffff, 0, 273 "SIIG Cyber I/O PCI 16C850 (10x family)", 274 DEFAULT_RCLK, 275 PUC_PORT_1S1P, 0x18, 4, 0, 276 }, 277 278 { 0x131f, 0x1021, 0xffff, 0, 279 "SIIG Cyber Parallel Dual PCI (10x family)", 280 0, 281 PUC_PORT_2P, 0x18, 8, 0, 282 }, 283 284 { 0x131f, 0x1030, 0xffff, 0, 285 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 286 DEFAULT_RCLK, 287 PUC_PORT_2S, 0x18, 4, 0, 288 }, 289 290 { 0x131f, 0x1031, 0xffff, 0, 291 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 292 DEFAULT_RCLK, 293 PUC_PORT_2S, 0x18, 4, 0, 294 }, 295 296 { 0x131f, 0x1032, 0xffff, 0, 297 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 298 DEFAULT_RCLK, 299 PUC_PORT_2S, 0x18, 4, 0, 300 }, 301 302 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 303 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 304 DEFAULT_RCLK, 305 PUC_PORT_2S1P, 0x18, 4, 0, 306 }, 307 308 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 309 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 310 DEFAULT_RCLK, 311 PUC_PORT_2S1P, 0x18, 4, 0, 312 }, 313 314 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 315 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 316 DEFAULT_RCLK, 317 PUC_PORT_2S1P, 0x18, 4, 0, 318 }, 319 320 { 0x131f, 0x1050, 0xffff, 0, 321 "SIIG Cyber 4S PCI 16C550 (10x family)", 322 DEFAULT_RCLK, 323 PUC_PORT_4S, 0x18, 4, 0, 324 }, 325 326 { 0x131f, 0x1051, 0xffff, 0, 327 "SIIG Cyber 4S PCI 16C650 (10x family)", 328 DEFAULT_RCLK, 329 PUC_PORT_4S, 0x18, 4, 0, 330 }, 331 332 { 0x131f, 0x1052, 0xffff, 0, 333 "SIIG Cyber 4S PCI 16C850 (10x family)", 334 DEFAULT_RCLK, 335 PUC_PORT_4S, 0x18, 4, 0, 336 }, 337 338 { 0x131f, 0x2010, 0xffff, 0, 339 "SIIG Cyber I/O PCI 16C550 (20x family)", 340 DEFAULT_RCLK, 341 PUC_PORT_1S1P, 0x10, 4, 0, 342 }, 343 344 { 0x131f, 0x2011, 0xffff, 0, 345 "SIIG Cyber I/O PCI 16C650 (20x family)", 346 DEFAULT_RCLK, 347 PUC_PORT_1S1P, 0x10, 4, 0, 348 }, 349 350 { 0x131f, 0x2012, 0xffff, 0, 351 "SIIG Cyber I/O PCI 16C850 (20x family)", 352 DEFAULT_RCLK, 353 PUC_PORT_1S1P, 0x10, 4, 0, 354 }, 355 356 { 0x131f, 0x2021, 0xffff, 0, 357 "SIIG Cyber Parallel Dual PCI (20x family)", 358 0, 359 PUC_PORT_2P, 0x10, 8, 0, 360 }, 361 362 { 0x131f, 0x2030, 0xffff, 0, 363 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 364 DEFAULT_RCLK, 365 PUC_PORT_2S, 0x10, 4, 0, 366 }, 367 368 { 0x131f, 0x2031, 0xffff, 0, 369 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 370 DEFAULT_RCLK, 371 PUC_PORT_2S, 0x10, 4, 0, 372 }, 373 374 { 0x131f, 0x2032, 0xffff, 0, 375 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 376 DEFAULT_RCLK, 377 PUC_PORT_2S, 0x10, 4, 0, 378 }, 379 380 { 0x131f, 0x2040, 0xffff, 0, 381 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 382 DEFAULT_RCLK, 383 PUC_PORT_1S2P, 0x10, -1, 0, 384 .config_function = puc_config_siig 385 }, 386 387 { 0x131f, 0x2041, 0xffff, 0, 388 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 389 DEFAULT_RCLK, 390 PUC_PORT_1S2P, 0x10, -1, 0, 391 .config_function = puc_config_siig 392 }, 393 394 { 0x131f, 0x2042, 0xffff, 0, 395 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 396 DEFAULT_RCLK, 397 PUC_PORT_1S2P, 0x10, -1, 0, 398 .config_function = puc_config_siig 399 }, 400 401 { 0x131f, 0x2050, 0xffff, 0, 402 "SIIG Cyber 4S PCI 16C550 (20x family)", 403 DEFAULT_RCLK, 404 PUC_PORT_4S, 0x10, 4, 0, 405 }, 406 407 { 0x131f, 0x2051, 0xffff, 0, 408 "SIIG Cyber 4S PCI 16C650 (20x family)", 409 DEFAULT_RCLK, 410 PUC_PORT_4S, 0x10, 4, 0, 411 }, 412 413 { 0x131f, 0x2052, 0xffff, 0, 414 "SIIG Cyber 4S PCI 16C850 (20x family)", 415 DEFAULT_RCLK, 416 PUC_PORT_4S, 0x10, 4, 0, 417 }, 418 419 { 0x131f, 0x2060, 0xffff, 0, 420 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 421 DEFAULT_RCLK, 422 PUC_PORT_2S1P, 0x10, 4, 0, 423 }, 424 425 { 0x131f, 0x2061, 0xffff, 0, 426 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 427 DEFAULT_RCLK, 428 PUC_PORT_2S1P, 0x10, 4, 0, 429 }, 430 431 { 0x131f, 0x2062, 0xffff, 0, 432 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 433 DEFAULT_RCLK, 434 PUC_PORT_2S1P, 0x10, 4, 0, 435 }, 436 437 { 0x131f, 0x2081, 0xffff, 0, 438 "SIIG PS8000 8S PCI 16C650 (20x family)", 439 DEFAULT_RCLK, 440 PUC_PORT_8S, 0x10, -1, -1, 441 .config_function = puc_config_siig 442 }, 443 444 { 0x135c, 0x0010, 0xffff, 0, 445 "Quatech QSC-100", 446 -3, /* max 8x clock rate */ 447 PUC_PORT_4S, 0x14, 0, 8, 448 .config_function = puc_config_quatech 449 }, 450 451 { 0x135c, 0x0020, 0xffff, 0, 452 "Quatech DSC-100", 453 -1, /* max 2x clock rate */ 454 PUC_PORT_2S, 0x14, 0, 8, 455 .config_function = puc_config_quatech 456 }, 457 458 { 0x135c, 0x0030, 0xffff, 0, 459 "Quatech DSC-200/300", 460 -1, /* max 2x clock rate */ 461 PUC_PORT_2S, 0x14, 0, 8, 462 .config_function = puc_config_quatech 463 }, 464 465 { 0x135c, 0x0040, 0xffff, 0, 466 "Quatech QSC-200/300", 467 -3, /* max 8x clock rate */ 468 PUC_PORT_4S, 0x14, 0, 8, 469 .config_function = puc_config_quatech 470 }, 471 472 { 0x135c, 0x0050, 0xffff, 0, 473 "Quatech ESC-100D", 474 -3, /* max 8x clock rate */ 475 PUC_PORT_8S, 0x14, 0, 8, 476 .config_function = puc_config_quatech 477 }, 478 479 { 0x135c, 0x0060, 0xffff, 0, 480 "Quatech ESC-100M", 481 -3, /* max 8x clock rate */ 482 PUC_PORT_8S, 0x14, 0, 8, 483 .config_function = puc_config_quatech 484 }, 485 486 { 0x135c, 0x0170, 0xffff, 0, 487 "Quatech QSCLP-100", 488 -1, /* max 2x clock rate */ 489 PUC_PORT_4S, 0x18, 0, 8, 490 .config_function = puc_config_quatech 491 }, 492 493 { 0x135c, 0x0180, 0xffff, 0, 494 "Quatech DSCLP-100", 495 -1, /* max 3x clock rate */ 496 PUC_PORT_2S, 0x18, 0, 8, 497 .config_function = puc_config_quatech 498 }, 499 500 { 0x135c, 0x01b0, 0xffff, 0, 501 "Quatech DSCLP-200/300", 502 -1, /* max 2x clock rate */ 503 PUC_PORT_2S, 0x18, 0, 8, 504 .config_function = puc_config_quatech 505 }, 506 507 { 0x135c, 0x01e0, 0xffff, 0, 508 "Quatech ESCLP-100", 509 -3, /* max 8x clock rate */ 510 PUC_PORT_8S, 0x10, 0, 8, 511 .config_function = puc_config_quatech 512 }, 513 514 { 0x1393, 0x1024, 0xffff, 0, 515 "Moxa Technologies, Smartio CP-102E/PCIe", 516 DEFAULT_RCLK * 8, 517 PUC_PORT_2S, 0x14, 0, -1, 518 .config_function = puc_config_moxa 519 }, 520 521 { 0x1393, 0x1025, 0xffff, 0, 522 "Moxa Technologies, Smartio CP-102EL/PCIe", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_2S, 0x14, 0, -1, 525 .config_function = puc_config_moxa 526 }, 527 528 { 0x1393, 0x1040, 0xffff, 0, 529 "Moxa Technologies, Smartio C104H/PCI", 530 DEFAULT_RCLK * 8, 531 PUC_PORT_4S, 0x18, 0, 8, 532 }, 533 534 { 0x1393, 0x1041, 0xffff, 0, 535 "Moxa Technologies, Smartio CP-104UL/PCI", 536 DEFAULT_RCLK * 8, 537 PUC_PORT_4S, 0x18, 0, 8, 538 }, 539 540 { 0x1393, 0x1042, 0xffff, 0, 541 "Moxa Technologies, Smartio CP-104JU/PCI", 542 DEFAULT_RCLK * 8, 543 PUC_PORT_4S, 0x18, 0, 8, 544 }, 545 546 { 0x1393, 0x1043, 0xffff, 0, 547 "Moxa Technologies, Smartio CP-104EL/PCIe", 548 DEFAULT_RCLK * 8, 549 PUC_PORT_4S, 0x18, 0, 8, 550 }, 551 552 { 0x1393, 0x1045, 0xffff, 0, 553 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 554 DEFAULT_RCLK * 8, 555 PUC_PORT_4S, 0x14, 0, -1, 556 .config_function = puc_config_moxa 557 }, 558 559 { 0x1393, 0x1120, 0xffff, 0, 560 "Moxa Technologies, CP-112UL", 561 DEFAULT_RCLK * 8, 562 PUC_PORT_2S, 0x18, 0, 8, 563 }, 564 565 { 0x1393, 0x1141, 0xffff, 0, 566 "Moxa Technologies, Industio CP-114", 567 DEFAULT_RCLK * 8, 568 PUC_PORT_4S, 0x18, 0, 8, 569 }, 570 571 { 0x1393, 0x1144, 0xffff, 0, 572 "Moxa Technologies, Smartio CP-114EL/PCIe", 573 DEFAULT_RCLK * 8, 574 PUC_PORT_4S, 0x14, 0, -1, 575 .config_function = puc_config_moxa 576 }, 577 578 { 0x1393, 0x1182, 0xffff, 0, 579 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 580 DEFAULT_RCLK * 8, 581 PUC_PORT_8S, 0x14, 0, -1, 582 .config_function = puc_config_moxa 583 }, 584 585 { 0x1393, 0x1680, 0xffff, 0, 586 "Moxa Technologies, C168H/PCI", 587 DEFAULT_RCLK * 8, 588 PUC_PORT_8S, 0x18, 0, 8, 589 }, 590 591 { 0x1393, 0x1681, 0xffff, 0, 592 "Moxa Technologies, C168U/PCI", 593 DEFAULT_RCLK * 8, 594 PUC_PORT_8S, 0x18, 0, 8, 595 }, 596 597 { 0x1393, 0x1682, 0xffff, 0, 598 "Moxa Technologies, CP-168EL/PCIe", 599 DEFAULT_RCLK * 8, 600 PUC_PORT_8S, 0x18, 0, 8, 601 }, 602 603 { 0x1393, 0x1683, 0xffff, 0, 604 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 605 DEFAULT_RCLK * 8, 606 PUC_PORT_8S, 0x14, 0, -1, 607 .config_function = puc_config_moxa 608 }, 609 610 { 0x13a8, 0x0152, 0xffff, 0, 611 "Exar XR17C/D152", 612 DEFAULT_RCLK * 8, 613 PUC_PORT_2S, 0x10, 0, -1, 614 .config_function = puc_config_exar 615 }, 616 617 { 0x13a8, 0x0154, 0xffff, 0, 618 "Exar XR17C154", 619 DEFAULT_RCLK * 8, 620 PUC_PORT_4S, 0x10, 0, -1, 621 .config_function = puc_config_exar 622 }, 623 624 { 0x13a8, 0x0158, 0xffff, 0, 625 "Exar XR17C158", 626 DEFAULT_RCLK * 8, 627 PUC_PORT_8S, 0x10, 0, -1, 628 .config_function = puc_config_exar 629 }, 630 631 { 0x13a8, 0x0258, 0xffff, 0, 632 "Exar XR17V258IV", 633 DEFAULT_RCLK * 8, 634 PUC_PORT_8S, 0x10, 0, -1, 635 .config_function = puc_config_exar 636 }, 637 638 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 639 { 0x13a8, 0x0358, 0xffff, 0, 640 "Exar XR17V358", 641 125000000, 642 PUC_PORT_8S, 0x10, 0, -1, 643 .config_function = puc_config_exar_pcie 644 }, 645 646 { 0x13fe, 0x1600, 0x1602, 0x0002, 647 "Advantech PCI-1602", 648 DEFAULT_RCLK * 8, 649 PUC_PORT_2S, 0x10, 0, 8, 650 }, 651 652 { 0x1407, 0x0100, 0xffff, 0, 653 "Lava Computers Dual Serial", 654 DEFAULT_RCLK, 655 PUC_PORT_2S, 0x10, 4, 0, 656 }, 657 658 { 0x1407, 0x0101, 0xffff, 0, 659 "Lava Computers Quatro A", 660 DEFAULT_RCLK, 661 PUC_PORT_2S, 0x10, 4, 0, 662 }, 663 664 { 0x1407, 0x0102, 0xffff, 0, 665 "Lava Computers Quatro B", 666 DEFAULT_RCLK, 667 PUC_PORT_2S, 0x10, 4, 0, 668 }, 669 670 { 0x1407, 0x0120, 0xffff, 0, 671 "Lava Computers Quattro-PCI A", 672 DEFAULT_RCLK, 673 PUC_PORT_2S, 0x10, 4, 0, 674 }, 675 676 { 0x1407, 0x0121, 0xffff, 0, 677 "Lava Computers Quattro-PCI B", 678 DEFAULT_RCLK, 679 PUC_PORT_2S, 0x10, 4, 0, 680 }, 681 682 { 0x1407, 0x0180, 0xffff, 0, 683 "Lava Computers Octo A", 684 DEFAULT_RCLK, 685 PUC_PORT_4S, 0x10, 4, 0, 686 }, 687 688 { 0x1407, 0x0181, 0xffff, 0, 689 "Lava Computers Octo B", 690 DEFAULT_RCLK, 691 PUC_PORT_4S, 0x10, 4, 0, 692 }, 693 694 { 0x1409, 0x7268, 0xffff, 0, 695 "Sunix SUN1888", 696 0, 697 PUC_PORT_2P, 0x10, 0, 8, 698 }, 699 700 { 0x1409, 0x7168, 0xffff, 0, 701 NULL, 702 DEFAULT_RCLK * 8, 703 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 704 .config_function = puc_config_timedia 705 }, 706 707 /* 708 * Boards with an Oxford Semiconductor chip. 709 * 710 * Oxford Semiconductor provides documentation for their chip at: 711 * <URL:http://www.plxtech.com/products/uart/> 712 * 713 * As sold by Kouwell <URL:http://www.kouwell.com/>. 714 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 715 */ 716 { 717 0x1415, 0x9501, 0x10fc, 0xc070, 718 "I-O DATA RSA-PCI2/R", 719 DEFAULT_RCLK * 8, 720 PUC_PORT_2S, 0x10, 0, 8, 721 }, 722 723 { 0x1415, 0x9501, 0x131f, 0x2050, 724 "SIIG Cyber 4 PCI 16550", 725 DEFAULT_RCLK * 10, 726 PUC_PORT_4S, 0x10, 0, 8, 727 }, 728 729 { 0x1415, 0x9501, 0x131f, 0x2051, 730 "SIIG Cyber 4S PCI 16C650 (20x family)", 731 DEFAULT_RCLK * 10, 732 PUC_PORT_4S, 0x10, 0, 8, 733 }, 734 735 { 0x1415, 0x9501, 0x131f, 0x2052, 736 "SIIG Quartet Serial 850", 737 DEFAULT_RCLK * 10, 738 PUC_PORT_4S, 0x10, 0, 8, 739 }, 740 741 { 0x1415, 0x9501, 0x14db, 0x2150, 742 "Kuroutoshikou SERIAL4P-LPPCI2", 743 DEFAULT_RCLK * 10, 744 PUC_PORT_4S, 0x10, 0, 8, 745 }, 746 747 { 0x1415, 0x9501, 0xffff, 0, 748 "Oxford Semiconductor OX16PCI954 UARTs", 749 0, 750 PUC_PORT_4S, 0x10, 0, 8, 751 .config_function = puc_config_oxford_pci954 752 }, 753 754 { 0x1415, 0x950a, 0x131f, 0x2030, 755 "SIIG Cyber 2S PCIe", 756 DEFAULT_RCLK * 10, 757 PUC_PORT_2S, 0x10, 0, 8, 758 }, 759 760 { 0x1415, 0x950a, 0x131f, 0x2032, 761 "SIIG Cyber Serial Dual PCI 16C850", 762 DEFAULT_RCLK * 10, 763 PUC_PORT_4S, 0x10, 0, 8, 764 }, 765 766 { 0x1415, 0x950a, 0xffff, 0, 767 "Oxford Semiconductor OX16PCI954 UARTs", 768 DEFAULT_RCLK, 769 PUC_PORT_4S, 0x10, 0, 8, 770 }, 771 772 { 0x1415, 0x9511, 0xffff, 0, 773 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 774 DEFAULT_RCLK, 775 PUC_PORT_4S, 0x10, 0, 8, 776 }, 777 778 { 0x1415, 0x9521, 0xffff, 0, 779 "Oxford Semiconductor OX16PCI952 UARTs", 780 DEFAULT_RCLK, 781 PUC_PORT_2S, 0x10, 4, 0, 782 }, 783 784 { 0x1415, 0x9538, 0xffff, 0, 785 "Oxford Semiconductor OX16PCI958 UARTs", 786 DEFAULT_RCLK, 787 PUC_PORT_8S, 0x18, 0, 8, 788 }, 789 790 /* 791 * Perle boards use Oxford Semiconductor chips, but they store the 792 * Oxford Semiconductor device ID as a subvendor device ID and use 793 * their own device IDs. 794 */ 795 796 { 0x155f, 0x0331, 0xffff, 0, 797 "Perle Ultraport4 Express", 798 DEFAULT_RCLK * 8, 799 PUC_PORT_4S, 0x10, 0, 8, 800 }, 801 802 { 0x155f, 0xB012, 0xffff, 0, 803 "Perle Speed2 LE", 804 DEFAULT_RCLK * 8, 805 PUC_PORT_2S, 0x10, 0, 8, 806 }, 807 808 { 0x155f, 0xB022, 0xffff, 0, 809 "Perle Speed2 LE", 810 DEFAULT_RCLK * 8, 811 PUC_PORT_2S, 0x10, 0, 8, 812 }, 813 814 { 0x155f, 0xB004, 0xffff, 0, 815 "Perle Speed4 LE", 816 DEFAULT_RCLK * 8, 817 PUC_PORT_4S, 0x10, 0, 8, 818 }, 819 820 { 0x155f, 0xB008, 0xffff, 0, 821 "Perle Speed8 LE", 822 DEFAULT_RCLK * 8, 823 PUC_PORT_8S, 0x10, 0, 8, 824 }, 825 826 827 /* 828 * Oxford Semiconductor PCI Express Expresso family 829 * 830 * Found in many 'native' PCI Express serial boards such as: 831 * 832 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 833 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 834 * 835 * Lindy 51189 (4 port) 836 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 837 * 838 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 839 * <URL:http://www.startech.com> 840 */ 841 842 { 0x1415, 0xc11b, 0xffff, 0, 843 "Oxford Semiconductor OXPCIe952 1S1P", 844 DEFAULT_RCLK * 0x22, 845 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 846 .config_function = puc_config_oxford_pcie 847 }, 848 849 { 0x1415, 0xc138, 0xffff, 0, 850 "Oxford Semiconductor OXPCIe952 UARTs", 851 DEFAULT_RCLK * 0x22, 852 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 853 .config_function = puc_config_oxford_pcie 854 }, 855 856 { 0x1415, 0xc158, 0xffff, 0, 857 "Oxford Semiconductor OXPCIe952 UARTs", 858 DEFAULT_RCLK * 0x22, 859 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 860 .config_function = puc_config_oxford_pcie 861 }, 862 863 { 0x1415, 0xc15d, 0xffff, 0, 864 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 865 DEFAULT_RCLK * 0x22, 866 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 867 .config_function = puc_config_oxford_pcie 868 }, 869 870 { 0x1415, 0xc208, 0xffff, 0, 871 "Oxford Semiconductor OXPCIe954 UARTs", 872 DEFAULT_RCLK * 0x22, 873 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 874 .config_function = puc_config_oxford_pcie 875 }, 876 877 { 0x1415, 0xc20d, 0xffff, 0, 878 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 879 DEFAULT_RCLK * 0x22, 880 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 881 .config_function = puc_config_oxford_pcie 882 }, 883 884 { 0x1415, 0xc308, 0xffff, 0, 885 "Oxford Semiconductor OXPCIe958 UARTs", 886 DEFAULT_RCLK * 0x22, 887 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 888 .config_function = puc_config_oxford_pcie 889 }, 890 891 { 0x1415, 0xc30d, 0xffff, 0, 892 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 893 DEFAULT_RCLK * 0x22, 894 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 895 .config_function = puc_config_oxford_pcie 896 }, 897 898 { 0x14d2, 0x8010, 0xffff, 0, 899 "VScom PCI-100L", 900 DEFAULT_RCLK * 8, 901 PUC_PORT_1S, 0x14, 0, 0, 902 }, 903 904 { 0x14d2, 0x8020, 0xffff, 0, 905 "VScom PCI-200L", 906 DEFAULT_RCLK * 8, 907 PUC_PORT_2S, 0x14, 4, 0, 908 }, 909 910 { 0x14d2, 0x8028, 0xffff, 0, 911 "VScom 200Li", 912 DEFAULT_RCLK, 913 PUC_PORT_2S, 0x20, 0, 8, 914 }, 915 916 /* 917 * VScom (Titan?) PCI-800L. More modern variant of the 918 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 919 * two of them obviously implemented as macro cells in 920 * the ASIC. This causes the weird port access pattern 921 * below, where two of the IO port ranges each access 922 * one of the ASIC UARTs, and a block of IO addresses 923 * access the external UARTs. 924 */ 925 { 0x14d2, 0x8080, 0xffff, 0, 926 "Titan VScom PCI-800L", 927 DEFAULT_RCLK * 8, 928 PUC_PORT_8S, 0x14, -1, -1, 929 .config_function = puc_config_titan 930 }, 931 932 /* 933 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 934 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 935 * device ID 3 and PCI device 1 device ID 4. 936 */ 937 { 0x14d2, 0xa003, 0xffff, 0, 938 "Titan PCI-800H", 939 DEFAULT_RCLK * 8, 940 PUC_PORT_4S, 0x10, 0, 8, 941 }, 942 943 { 0x14d2, 0xa004, 0xffff, 0, 944 "Titan PCI-800H", 945 DEFAULT_RCLK * 8, 946 PUC_PORT_4S, 0x10, 0, 8, 947 }, 948 949 { 0x14d2, 0xa005, 0xffff, 0, 950 "Titan PCI-200H", 951 DEFAULT_RCLK * 8, 952 PUC_PORT_2S, 0x10, 0, 8, 953 }, 954 955 { 0x14d2, 0xe020, 0xffff, 0, 956 "Titan VScom PCI-200HV2", 957 DEFAULT_RCLK * 8, 958 PUC_PORT_2S, 0x10, 4, 0, 959 }, 960 961 { 0x14d2, 0xa007, 0xffff, 0, 962 "Titan VScom PCIex-800H", 963 DEFAULT_RCLK * 8, 964 PUC_PORT_4S, 0x10, 0, 8, 965 }, 966 967 { 0x14d2, 0xa008, 0xffff, 0, 968 "Titan VScom PCIex-800H", 969 DEFAULT_RCLK * 8, 970 PUC_PORT_4S, 0x10, 0, 8, 971 }, 972 973 { 0x14db, 0x2130, 0xffff, 0, 974 "Avlab Technology, PCI IO 2S", 975 DEFAULT_RCLK, 976 PUC_PORT_2S, 0x10, 4, 0, 977 }, 978 979 { 0x14db, 0x2150, 0xffff, 0, 980 "Avlab Low Profile PCI 4 Serial", 981 DEFAULT_RCLK, 982 PUC_PORT_4S, 0x10, 4, 0, 983 }, 984 985 { 0x14db, 0x2152, 0xffff, 0, 986 "Avlab Low Profile PCI 4 Serial", 987 DEFAULT_RCLK, 988 PUC_PORT_4S, 0x10, 4, 0, 989 }, 990 991 { 0x1592, 0x0781, 0xffff, 0, 992 "Syba Tech Ltd. PCI-4S2P-550-ECP", 993 DEFAULT_RCLK, 994 PUC_PORT_4S1P, 0x10, 0, -1, 995 .config_function = puc_config_syba 996 }, 997 998 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 999 "Sunix SER5xxxx 2-port serial", 1000 DEFAULT_RCLK * 8, 1001 PUC_PORT_2S, 0x10, 0, 8, 1002 }, 1003 1004 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1005 "Sunix SER5xxxx 4-port serial", 1006 DEFAULT_RCLK * 8, 1007 PUC_PORT_4S, 0x10, 0, 8, 1008 }, 1009 1010 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1011 "Sunix SER5xxxx 8-port serial", 1012 DEFAULT_RCLK * 8, 1013 PUC_PORT_8S, -1, -1, -1, 1014 .config_function = puc_config_sunix 1015 }, 1016 1017 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1018 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1019 DEFAULT_RCLK * 8, 1020 PUC_PORT_1S1P, -1, -1, -1, 1021 .config_function = puc_config_sunix 1022 }, 1023 1024 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1025 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1026 DEFAULT_RCLK * 8, 1027 PUC_PORT_2S1P, -1, -1, -1, 1028 .config_function = puc_config_sunix 1029 }, 1030 1031 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1032 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1033 DEFAULT_RCLK * 8, 1034 PUC_PORT_4S1P, -1, -1, -1, 1035 .config_function = puc_config_sunix 1036 }, 1037 1038 { 0x5372, 0x6873, 0xffff, 0, 1039 "Sun 1040 PCI Quad Serial", 1040 DEFAULT_RCLK, 1041 PUC_PORT_4S, 0x10, 4, 0, 1042 }, 1043 1044 { 0x6666, 0x0001, 0xffff, 0, 1045 "Decision Computer Inc, PCCOM 4-port serial", 1046 DEFAULT_RCLK, 1047 PUC_PORT_4S, 0x1c, 0, 8, 1048 }, 1049 1050 { 0x6666, 0x0002, 0xffff, 0, 1051 "Decision Computer Inc, PCCOM 8-port serial", 1052 DEFAULT_RCLK, 1053 PUC_PORT_8S, 0x1c, 0, 8, 1054 }, 1055 1056 { 0x6666, 0x0004, 0xffff, 0, 1057 "PCCOM dual port RS232/422/485", 1058 DEFAULT_RCLK, 1059 PUC_PORT_2S, 0x1c, 0, 8, 1060 }, 1061 1062 { 0x9710, 0x9815, 0xffff, 0, 1063 "NetMos NM9815 Dual 1284 Printer port", 1064 0, 1065 PUC_PORT_2P, 0x10, 8, 0, 1066 }, 1067 1068 /* 1069 * This is more specific than the generic NM9835 entry, and is placed 1070 * here to _prevent_ puc(4) from claiming this single port card. 1071 * 1072 * uart(4) will claim this device. 1073 */ 1074 { 0x9710, 0x9835, 0x1000, 1, 1075 "NetMos NM9835 based 1-port serial", 1076 DEFAULT_RCLK, 1077 PUC_PORT_1S, 0x10, 4, 0, 1078 }, 1079 1080 { 0x9710, 0x9835, 0x1000, 2, 1081 "NetMos NM9835 based 2-port serial", 1082 DEFAULT_RCLK, 1083 PUC_PORT_2S, 0x10, 4, 0, 1084 }, 1085 1086 { 0x9710, 0x9835, 0xffff, 0, 1087 "NetMos NM9835 Dual UART and 1284 Printer port", 1088 DEFAULT_RCLK, 1089 PUC_PORT_2S1P, 0x10, 4, 0, 1090 }, 1091 1092 { 0x9710, 0x9845, 0x1000, 0x0006, 1093 "NetMos NM9845 6 Port UART", 1094 DEFAULT_RCLK, 1095 PUC_PORT_6S, 0x10, 4, 0, 1096 }, 1097 1098 { 0x9710, 0x9845, 0xffff, 0, 1099 "NetMos NM9845 Quad UART and 1284 Printer port", 1100 DEFAULT_RCLK, 1101 PUC_PORT_4S1P, 0x10, 4, 0, 1102 }, 1103 1104 { 0x9710, 0x9865, 0xa000, 0x3002, 1105 "NetMos NM9865 Dual UART", 1106 DEFAULT_RCLK, 1107 PUC_PORT_2S, 0x10, 4, 0, 1108 }, 1109 1110 { 0x9710, 0x9865, 0xa000, 0x3003, 1111 "NetMos NM9865 Triple UART", 1112 DEFAULT_RCLK, 1113 PUC_PORT_3S, 0x10, 4, 0, 1114 }, 1115 1116 { 0x9710, 0x9865, 0xa000, 0x3004, 1117 "NetMos NM9865 Quad UART", 1118 DEFAULT_RCLK, 1119 PUC_PORT_4S, 0x10, 4, 0, 1120 }, 1121 1122 { 0x9710, 0x9865, 0xa000, 0x3011, 1123 "NetMos NM9865 Single UART and 1284 Printer port", 1124 DEFAULT_RCLK, 1125 PUC_PORT_1S1P, 0x10, 4, 0, 1126 }, 1127 1128 { 0x9710, 0x9865, 0xa000, 0x3012, 1129 "NetMos NM9865 Dual UART and 1284 Printer port", 1130 DEFAULT_RCLK, 1131 PUC_PORT_2S1P, 0x10, 4, 0, 1132 }, 1133 1134 { 0x9710, 0x9865, 0xa000, 0x3020, 1135 "NetMos NM9865 Dual 1284 Printer port", 1136 DEFAULT_RCLK, 1137 PUC_PORT_2P, 0x10, 4, 0, 1138 }, 1139 1140 { 0xb00c, 0x021c, 0xffff, 0, 1141 "IC Book Labs Gunboat x4 Lite", 1142 DEFAULT_RCLK, 1143 PUC_PORT_4S, 0x10, 0, 8, 1144 .config_function = puc_config_icbook 1145 }, 1146 1147 { 0xb00c, 0x031c, 0xffff, 0, 1148 "IC Book Labs Gunboat x4 Pro", 1149 DEFAULT_RCLK, 1150 PUC_PORT_4S, 0x10, 0, 8, 1151 .config_function = puc_config_icbook 1152 }, 1153 1154 { 0xb00c, 0x041c, 0xffff, 0, 1155 "IC Book Labs Ironclad x8 Lite", 1156 DEFAULT_RCLK, 1157 PUC_PORT_8S, 0x10, 0, 8, 1158 .config_function = puc_config_icbook 1159 }, 1160 1161 { 0xb00c, 0x051c, 0xffff, 0, 1162 "IC Book Labs Ironclad x8 Pro", 1163 DEFAULT_RCLK, 1164 PUC_PORT_8S, 0x10, 0, 8, 1165 .config_function = puc_config_icbook 1166 }, 1167 1168 { 0xb00c, 0x081c, 0xffff, 0, 1169 "IC Book Labs Dreadnought x16 Pro", 1170 DEFAULT_RCLK * 8, 1171 PUC_PORT_16S, 0x10, 0, 8, 1172 .config_function = puc_config_icbook 1173 }, 1174 1175 { 0xb00c, 0x091c, 0xffff, 0, 1176 "IC Book Labs Dreadnought x16 Lite", 1177 DEFAULT_RCLK, 1178 PUC_PORT_16S, 0x10, 0, 8, 1179 .config_function = puc_config_icbook 1180 }, 1181 1182 { 0xb00c, 0x0a1c, 0xffff, 0, 1183 "IC Book Labs Gunboat x2 Low Profile", 1184 DEFAULT_RCLK, 1185 PUC_PORT_2S, 0x10, 0, 8, 1186 }, 1187 1188 { 0xb00c, 0x0b1c, 0xffff, 0, 1189 "IC Book Labs Gunboat x4 Low Profile", 1190 DEFAULT_RCLK, 1191 PUC_PORT_4S, 0x10, 0, 8, 1192 .config_function = puc_config_icbook 1193 }, 1194 1195 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1196 }; 1197 1198 static int 1199 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1200 intptr_t *res) 1201 { 1202 switch (cmd) { 1203 case PUC_CFG_GET_OFS: 1204 *res = 8 * (port & 1); 1205 return (0); 1206 case PUC_CFG_GET_RID: 1207 *res = 0x14 + (port >> 1) * 4; 1208 return (0); 1209 default: 1210 break; 1211 } 1212 return (ENXIO); 1213 } 1214 1215 static int 1216 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1217 intptr_t *res) 1218 { 1219 const struct puc_cfg *cfg = sc->sc_cfg; 1220 1221 if (cmd == PUC_CFG_GET_OFS) { 1222 if (cfg->subdevice == 0x1282) /* Everest SP */ 1223 port <<= 1; 1224 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1225 port = (port == 3) ? 4 : port; 1226 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1227 return (0); 1228 } 1229 return (ENXIO); 1230 } 1231 1232 static int 1233 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1234 intptr_t *res) 1235 { 1236 if (cmd == PUC_CFG_GET_OFS) { 1237 *res = port * 0x200; 1238 return (0); 1239 } 1240 return (ENXIO); 1241 } 1242 1243 static int 1244 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1245 intptr_t *res) 1246 { 1247 if (cmd == PUC_CFG_GET_OFS) { 1248 *res = port * 0x400; 1249 return (0); 1250 } 1251 return (ENXIO); 1252 } 1253 1254 static int 1255 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1256 intptr_t *res) 1257 { 1258 if (cmd == PUC_CFG_GET_ILR) { 1259 *res = PUC_ILR_DIGI; 1260 return (0); 1261 } 1262 return (ENXIO); 1263 } 1264 1265 static int 1266 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1267 intptr_t *res) 1268 { 1269 if (cmd == PUC_CFG_GET_OFS) { 1270 const struct puc_cfg *cfg = sc->sc_cfg; 1271 1272 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1273 port = 7; 1274 *res = port * 0x200; 1275 1276 return 0; 1277 } 1278 return (ENXIO); 1279 } 1280 1281 static int 1282 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1283 intptr_t *res) 1284 { 1285 const struct puc_cfg *cfg = sc->sc_cfg; 1286 struct puc_bar *bar; 1287 uint8_t v0, v1; 1288 1289 switch (cmd) { 1290 case PUC_CFG_SETUP: 1291 /* 1292 * Check if the scratchpad register is enabled or if the 1293 * interrupt status and options registers are active. 1294 */ 1295 bar = puc_get_bar(sc, cfg->rid); 1296 if (bar == NULL) 1297 return (ENXIO); 1298 /* Set DLAB in the LCR register of UART 0. */ 1299 bus_write_1(bar->b_res, 3, 0x80); 1300 /* Write 0 to the SPR register of UART 0. */ 1301 bus_write_1(bar->b_res, 7, 0); 1302 /* Read back the contents of the SPR register of UART 0. */ 1303 v0 = bus_read_1(bar->b_res, 7); 1304 /* Write a specific value to the SPR register of UART 0. */ 1305 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1306 /* Read back the contents of the SPR register of UART 0. */ 1307 v1 = bus_read_1(bar->b_res, 7); 1308 /* Clear DLAB in the LCR register of UART 0. */ 1309 bus_write_1(bar->b_res, 3, 0); 1310 /* Save the two values read-back from the SPR register. */ 1311 sc->sc_cfg_data = (v0 << 8) | v1; 1312 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1313 /* 1314 * The SPR register echoed the two values written 1315 * by us. This means that the SPAD jumper is set. 1316 */ 1317 device_printf(sc->sc_dev, "warning: extra features " 1318 "not usable -- SPAD compatibility enabled\n"); 1319 return (0); 1320 } 1321 if (v0 != 0) { 1322 /* 1323 * The first value doesn't match. This can only mean 1324 * that the SPAD jumper is not set and that a non- 1325 * standard fixed clock multiplier jumper is set. 1326 */ 1327 if (bootverbose) 1328 device_printf(sc->sc_dev, "fixed clock rate " 1329 "multiplier of %d\n", 1 << v0); 1330 if (v0 < -cfg->clock) 1331 device_printf(sc->sc_dev, "warning: " 1332 "suboptimal fixed clock rate multiplier " 1333 "setting\n"); 1334 return (0); 1335 } 1336 /* 1337 * The first value matched, but the second didn't. We know 1338 * that the SPAD jumper is not set. We also know that the 1339 * clock rate multiplier is software controlled *and* that 1340 * we just programmed it to the maximum allowed. 1341 */ 1342 if (bootverbose) 1343 device_printf(sc->sc_dev, "clock rate multiplier of " 1344 "%d selected\n", 1 << -cfg->clock); 1345 return (0); 1346 case PUC_CFG_GET_CLOCK: 1347 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1348 v1 = sc->sc_cfg_data & 0xff; 1349 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1350 /* 1351 * XXX With the SPAD jumper applied, there's no 1352 * easy way of knowing if there's also a clock 1353 * rate multiplier jumper installed. Let's hope 1354 * not... 1355 */ 1356 *res = DEFAULT_RCLK; 1357 } else if (v0 == 0) { 1358 /* 1359 * No clock rate multiplier jumper installed, 1360 * so we programmed the board with the maximum 1361 * multiplier allowed as given to us in the 1362 * clock field of the config record (negated). 1363 */ 1364 *res = DEFAULT_RCLK << -cfg->clock; 1365 } else 1366 *res = DEFAULT_RCLK << v0; 1367 return (0); 1368 case PUC_CFG_GET_ILR: 1369 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1370 v1 = sc->sc_cfg_data & 0xff; 1371 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1372 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1373 return (0); 1374 default: 1375 break; 1376 } 1377 return (ENXIO); 1378 } 1379 1380 static int 1381 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1382 intptr_t *res) 1383 { 1384 static int base[] = { 0x251, 0x3f0, 0 }; 1385 const struct puc_cfg *cfg = sc->sc_cfg; 1386 struct puc_bar *bar; 1387 int efir, idx, ofs; 1388 uint8_t v; 1389 1390 switch (cmd) { 1391 case PUC_CFG_SETUP: 1392 bar = puc_get_bar(sc, cfg->rid); 1393 if (bar == NULL) 1394 return (ENXIO); 1395 1396 /* configure both W83877TFs */ 1397 bus_write_1(bar->b_res, 0x250, 0x89); 1398 bus_write_1(bar->b_res, 0x3f0, 0x87); 1399 bus_write_1(bar->b_res, 0x3f0, 0x87); 1400 idx = 0; 1401 while (base[idx] != 0) { 1402 efir = base[idx]; 1403 bus_write_1(bar->b_res, efir, 0x09); 1404 v = bus_read_1(bar->b_res, efir + 1); 1405 if ((v & 0x0f) != 0x0c) 1406 return (ENXIO); 1407 bus_write_1(bar->b_res, efir, 0x16); 1408 v = bus_read_1(bar->b_res, efir + 1); 1409 bus_write_1(bar->b_res, efir, 0x16); 1410 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1411 bus_write_1(bar->b_res, efir, 0x16); 1412 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1413 ofs = base[idx] & 0x300; 1414 bus_write_1(bar->b_res, efir, 0x23); 1415 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1416 bus_write_1(bar->b_res, efir, 0x24); 1417 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1418 bus_write_1(bar->b_res, efir, 0x25); 1419 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1420 bus_write_1(bar->b_res, efir, 0x17); 1421 bus_write_1(bar->b_res, efir + 1, 0x03); 1422 bus_write_1(bar->b_res, efir, 0x28); 1423 bus_write_1(bar->b_res, efir + 1, 0x43); 1424 idx++; 1425 } 1426 bus_write_1(bar->b_res, 0x250, 0xaa); 1427 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1428 return (0); 1429 case PUC_CFG_GET_OFS: 1430 switch (port) { 1431 case 0: 1432 *res = 0x2f8; 1433 return (0); 1434 case 1: 1435 *res = 0x2e8; 1436 return (0); 1437 case 2: 1438 *res = 0x3f8; 1439 return (0); 1440 case 3: 1441 *res = 0x3e8; 1442 return (0); 1443 case 4: 1444 *res = 0x278; 1445 return (0); 1446 } 1447 break; 1448 default: 1449 break; 1450 } 1451 return (ENXIO); 1452 } 1453 1454 static int 1455 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1456 intptr_t *res) 1457 { 1458 const struct puc_cfg *cfg = sc->sc_cfg; 1459 1460 switch (cmd) { 1461 case PUC_CFG_GET_OFS: 1462 if (cfg->ports == PUC_PORT_8S) { 1463 *res = (port > 4) ? 8 * (port - 4) : 0; 1464 return (0); 1465 } 1466 break; 1467 case PUC_CFG_GET_RID: 1468 if (cfg->ports == PUC_PORT_8S) { 1469 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1470 return (0); 1471 } 1472 if (cfg->ports == PUC_PORT_2S1P) { 1473 switch (port) { 1474 case 0: *res = 0x10; return (0); 1475 case 1: *res = 0x14; return (0); 1476 case 2: *res = 0x1c; return (0); 1477 } 1478 } 1479 break; 1480 default: 1481 break; 1482 } 1483 return (ENXIO); 1484 } 1485 1486 static int 1487 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1488 intptr_t *res) 1489 { 1490 static const uint16_t dual[] = { 1491 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1492 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1493 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1494 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1495 0xD079, 0 1496 }; 1497 static const uint16_t quad[] = { 1498 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1499 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1500 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1501 0xB157, 0 1502 }; 1503 static const uint16_t octa[] = { 1504 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1505 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1506 }; 1507 static const struct { 1508 int ports; 1509 const uint16_t *ids; 1510 } subdevs[] = { 1511 { 2, dual }, 1512 { 4, quad }, 1513 { 8, octa }, 1514 { 0, NULL } 1515 }; 1516 static char desc[64]; 1517 int dev, id; 1518 uint16_t subdev; 1519 1520 switch (cmd) { 1521 case PUC_CFG_GET_CLOCK: 1522 if (port < 2) 1523 *res = DEFAULT_RCLK * 8; 1524 else 1525 *res = DEFAULT_RCLK; 1526 return (0); 1527 case PUC_CFG_GET_DESC: 1528 snprintf(desc, sizeof(desc), 1529 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1530 *res = (intptr_t)desc; 1531 return (0); 1532 case PUC_CFG_GET_NPORTS: 1533 subdev = pci_get_subdevice(sc->sc_dev); 1534 dev = 0; 1535 while (subdevs[dev].ports != 0) { 1536 id = 0; 1537 while (subdevs[dev].ids[id] != 0) { 1538 if (subdev == subdevs[dev].ids[id]) { 1539 sc->sc_cfg_data = subdevs[dev].ports; 1540 *res = sc->sc_cfg_data; 1541 return (0); 1542 } 1543 id++; 1544 } 1545 dev++; 1546 } 1547 return (ENXIO); 1548 case PUC_CFG_GET_OFS: 1549 *res = (port == 1 || port == 3) ? 8 : 0; 1550 return (0); 1551 case PUC_CFG_GET_RID: 1552 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1553 return (0); 1554 case PUC_CFG_GET_TYPE: 1555 *res = PUC_TYPE_SERIAL; 1556 return (0); 1557 default: 1558 break; 1559 } 1560 return (ENXIO); 1561 } 1562 1563 static int 1564 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1565 int port __unused, intptr_t *res) 1566 { 1567 1568 switch (cmd) { 1569 case PUC_CFG_GET_CLOCK: 1570 /* 1571 * OXu16PCI954 use a 14.7456 MHz clock by default while 1572 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1573 */ 1574 if (pci_get_revid(sc->sc_dev) == 1) 1575 *res = DEFAULT_RCLK * 8; 1576 else 1577 *res = DEFAULT_RCLK; 1578 return (0); 1579 default: 1580 break; 1581 } 1582 return (ENXIO); 1583 } 1584 1585 static int 1586 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1587 intptr_t *res) 1588 { 1589 const struct puc_cfg *cfg = sc->sc_cfg; 1590 int idx; 1591 struct puc_bar *bar; 1592 uint8_t value; 1593 1594 switch (cmd) { 1595 case PUC_CFG_SETUP: 1596 device_printf(sc->sc_dev, "%d UARTs detected\n", 1597 sc->sc_nports); 1598 1599 /* Set UARTs to enhanced mode */ 1600 bar = puc_get_bar(sc, cfg->rid); 1601 if (bar == NULL) 1602 return (ENXIO); 1603 for (idx = 0; idx < sc->sc_nports; idx++) { 1604 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1605 0x92); 1606 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1607 value | 0x10); 1608 } 1609 return (0); 1610 case PUC_CFG_GET_LEN: 1611 *res = 0x200; 1612 return (0); 1613 case PUC_CFG_GET_NPORTS: 1614 /* 1615 * Check if we are being called from puc_bfe_attach() 1616 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1617 * puc_get_bar(), so we return a value of 16. This has cosmetic 1618 * side-effects at worst; in PUC_CFG_GET_DESC, 1619 * (int)sc->sc_cfg_data will not contain the true number of 1620 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1621 * call for this device family anyway. 1622 * 1623 * The check is for initialisation of sc->sc_bar[idx], which is 1624 * only done in puc_bfe_attach(). 1625 */ 1626 idx = 0; 1627 do { 1628 if (sc->sc_bar[idx++].b_rid != -1) { 1629 sc->sc_cfg_data = 16; 1630 *res = sc->sc_cfg_data; 1631 return (0); 1632 } 1633 } while (idx < PUC_PCI_BARS); 1634 1635 bar = puc_get_bar(sc, cfg->rid); 1636 if (bar == NULL) 1637 return (ENXIO); 1638 1639 value = bus_read_1(bar->b_res, 0x04); 1640 if (value == 0) 1641 return (ENXIO); 1642 1643 sc->sc_cfg_data = value; 1644 *res = sc->sc_cfg_data; 1645 return (0); 1646 case PUC_CFG_GET_OFS: 1647 *res = 0x1000 + (port << 9); 1648 return (0); 1649 case PUC_CFG_GET_TYPE: 1650 *res = PUC_TYPE_SERIAL; 1651 return (0); 1652 default: 1653 break; 1654 } 1655 return (ENXIO); 1656 } 1657 1658 static int 1659 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1660 intptr_t *res) 1661 { 1662 int error; 1663 1664 switch (cmd) { 1665 case PUC_CFG_GET_OFS: 1666 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1667 if (error != 0) 1668 return (error); 1669 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1670 return (0); 1671 case PUC_CFG_GET_RID: 1672 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1673 if (error != 0) 1674 return (error); 1675 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1676 return (0); 1677 default: 1678 break; 1679 } 1680 return (ENXIO); 1681 } 1682 1683 static int 1684 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1685 intptr_t *res) 1686 { 1687 switch (cmd) { 1688 case PUC_CFG_GET_OFS: 1689 *res = (port < 3) ? 0 : (port - 2) << 3; 1690 return (0); 1691 case PUC_CFG_GET_RID: 1692 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1693 return (0); 1694 default: 1695 break; 1696 } 1697 return (ENXIO); 1698 } 1699