1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * PCI "universal" communications card driver configuration data (used to 34 * match/attach the cards). 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/sysctl.h> 42 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 47 #include <dev/ic/ns16550.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <dev/puc/puc_bus.h> 53 #include <dev/puc/puc_cfg.h> 54 #include <dev/puc/puc_bfe.h> 55 56 static puc_config_f puc_config_advantech; 57 static puc_config_f puc_config_amc; 58 static puc_config_f puc_config_diva; 59 static puc_config_f puc_config_exar; 60 static puc_config_f puc_config_exar_pcie; 61 static puc_config_f puc_config_icbook; 62 static puc_config_f puc_config_moxa; 63 static puc_config_f puc_config_oxford_pci954; 64 static puc_config_f puc_config_oxford_pcie; 65 static puc_config_f puc_config_quatech; 66 static puc_config_f puc_config_syba; 67 static puc_config_f puc_config_siig; 68 static puc_config_f puc_config_sunix; 69 static puc_config_f puc_config_timedia; 70 static puc_config_f puc_config_titan; 71 72 const struct puc_cfg puc_pci_devices[] = { 73 { 0x0009, 0x7168, 0xffff, 0, 74 "Sunix SUN1889", 75 DEFAULT_RCLK * 8, 76 PUC_PORT_2S, 0x10, 0, 8, 77 }, 78 79 { 0x103c, 0x1048, 0x103c, 0x1049, 80 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 81 DEFAULT_RCLK, 82 PUC_PORT_3S, 0x10, 0, -1, 83 .config_function = puc_config_diva 84 }, 85 86 { 0x103c, 0x1048, 0x103c, 0x104a, 87 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 88 DEFAULT_RCLK, 89 PUC_PORT_2S, 0x10, 0, -1, 90 .config_function = puc_config_diva 91 }, 92 93 { 0x103c, 0x1048, 0x103c, 0x104b, 94 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 95 DEFAULT_RCLK, 96 PUC_PORT_4S, 0x10, 0, -1, 97 .config_function = puc_config_diva 98 }, 99 100 { 0x103c, 0x1048, 0x103c, 0x1223, 101 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 102 DEFAULT_RCLK, 103 PUC_PORT_3S, 0x10, 0, -1, 104 .config_function = puc_config_diva 105 }, 106 107 { 0x103c, 0x1048, 0x103c, 0x1226, 108 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 109 DEFAULT_RCLK, 110 PUC_PORT_3S, 0x10, 0, -1, 111 .config_function = puc_config_diva 112 }, 113 114 { 0x103c, 0x1048, 0x103c, 0x1282, 115 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 116 DEFAULT_RCLK, 117 PUC_PORT_3S, 0x10, 0, -1, 118 .config_function = puc_config_diva 119 }, 120 121 { 0x10b5, 0x1076, 0x10b5, 0x1076, 122 "VScom PCI-800", 123 DEFAULT_RCLK * 8, 124 PUC_PORT_8S, 0x18, 0, 8, 125 }, 126 127 { 0x10b5, 0x1077, 0x10b5, 0x1077, 128 "VScom PCI-400", 129 DEFAULT_RCLK * 8, 130 PUC_PORT_4S, 0x18, 0, 8, 131 }, 132 133 { 0x10b5, 0x1103, 0x10b5, 0x1103, 134 "VScom PCI-200", 135 DEFAULT_RCLK * 8, 136 PUC_PORT_2S, 0x18, 4, 0, 137 }, 138 139 /* 140 * Boca Research Turbo Serial 658 (8 serial port) card. 141 * Appears to be the same as Chase Research PLC PCI-FAST8 142 * and Perle PCI-FAST8 Multi-Port serial cards. 143 */ 144 { 0x10b5, 0x9050, 0x12e0, 0x0021, 145 "Boca Research Turbo Serial 658", 146 DEFAULT_RCLK * 4, 147 PUC_PORT_8S, 0x18, 0, 8, 148 }, 149 150 { 0x10b5, 0x9050, 0x12e0, 0x0031, 151 "Boca Research Turbo Serial 654", 152 DEFAULT_RCLK * 4, 153 PUC_PORT_4S, 0x18, 0, 8, 154 }, 155 156 /* 157 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 158 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 159 * into the subsystem fields, and claims that it's a 160 * network/misc (0x02/0x80) device. 161 */ 162 { 0x10b5, 0x9050, 0xd84d, 0x6808, 163 "Dolphin Peripherals 4035", 164 DEFAULT_RCLK, 165 PUC_PORT_2S, 0x18, 4, 0, 166 }, 167 168 /* 169 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 170 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 171 * into the subsystem fields, and claims that it's a 172 * network/misc (0x02/0x80) device. 173 */ 174 { 0x10b5, 0x9050, 0xd84d, 0x6810, 175 "Dolphin Peripherals 4014", 176 0, 177 PUC_PORT_2P, 0x20, 4, 0, 178 }, 179 180 { 0x10e8, 0x818e, 0xffff, 0, 181 "Applied Micro Circuits 8 Port UART", 182 DEFAULT_RCLK, 183 PUC_PORT_8S, 0x14, -1, -1, 184 .config_function = puc_config_amc 185 }, 186 187 /* 188 * The following members of the Digi International Neo series are 189 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV. 190 * Accordingly, the PCIe versions of these cards incorporate a PLX 191 * PCIe-PCI-bridge. 192 */ 193 194 { 0x114f, 0x00b0, 0xffff, 0, 195 "Digi Neo PCI 4 Port", 196 DEFAULT_RCLK * 8, 197 PUC_PORT_4S, 0x10, 0, -1, 198 .config_function = puc_config_exar 199 }, 200 201 { 0x114f, 0x00b1, 0xffff, 0, 202 "Digi Neo PCI 8 Port", 203 DEFAULT_RCLK * 8, 204 PUC_PORT_8S, 0x10, 0, -1, 205 .config_function = puc_config_exar 206 }, 207 208 { 0x114f, 0x00f0, 0xffff, 0, 209 "Digi Neo PCIe 8 Port", 210 DEFAULT_RCLK * 8, 211 PUC_PORT_8S, 0x10, 0, -1, 212 .config_function = puc_config_exar 213 }, 214 215 { 0x114f, 0x00f1, 0xffff, 0, 216 "Digi Neo PCIe 4 Port", 217 DEFAULT_RCLK * 8, 218 PUC_PORT_4S, 0x10, 0, -1, 219 .config_function = puc_config_exar 220 }, 221 222 { 0x114f, 0x00f2, 0xffff, 0, 223 "Digi Neo PCIe 4 Port RJ45", 224 DEFAULT_RCLK * 8, 225 PUC_PORT_4S, 0x10, 0, -1, 226 .config_function = puc_config_exar 227 }, 228 229 { 0x114f, 0x00f3, 0xffff, 0, 230 "Digi Neo PCIe 8 Port RJ45", 231 DEFAULT_RCLK * 8, 232 PUC_PORT_8S, 0x10, 0, -1, 233 .config_function = puc_config_exar 234 }, 235 236 { 0x11fe, 0x8010, 0xffff, 0, 237 "Comtrol RocketPort 550/8 RJ11 part A", 238 DEFAULT_RCLK * 4, 239 PUC_PORT_4S, 0x10, 0, 8, 240 }, 241 242 { 0x11fe, 0x8011, 0xffff, 0, 243 "Comtrol RocketPort 550/8 RJ11 part B", 244 DEFAULT_RCLK * 4, 245 PUC_PORT_4S, 0x10, 0, 8, 246 }, 247 248 { 0x11fe, 0x8012, 0xffff, 0, 249 "Comtrol RocketPort 550/8 Octa part A", 250 DEFAULT_RCLK * 4, 251 PUC_PORT_4S, 0x10, 0, 8, 252 }, 253 254 { 0x11fe, 0x8013, 0xffff, 0, 255 "Comtrol RocketPort 550/8 Octa part B", 256 DEFAULT_RCLK * 4, 257 PUC_PORT_4S, 0x10, 0, 8, 258 }, 259 260 { 0x11fe, 0x8014, 0xffff, 0, 261 "Comtrol RocketPort 550/4 RJ45", 262 DEFAULT_RCLK * 4, 263 PUC_PORT_4S, 0x10, 0, 8, 264 }, 265 266 { 0x11fe, 0x8015, 0xffff, 0, 267 "Comtrol RocketPort 550/Quad", 268 DEFAULT_RCLK * 4, 269 PUC_PORT_4S, 0x10, 0, 8, 270 }, 271 272 { 0x11fe, 0x8016, 0xffff, 0, 273 "Comtrol RocketPort 550/16 part A", 274 DEFAULT_RCLK * 4, 275 PUC_PORT_4S, 0x10, 0, 8, 276 }, 277 278 { 0x11fe, 0x8017, 0xffff, 0, 279 "Comtrol RocketPort 550/16 part B", 280 DEFAULT_RCLK * 4, 281 PUC_PORT_12S, 0x10, 0, 8, 282 }, 283 284 { 0x11fe, 0x8018, 0xffff, 0, 285 "Comtrol RocketPort 550/8 part A", 286 DEFAULT_RCLK * 4, 287 PUC_PORT_4S, 0x10, 0, 8, 288 }, 289 290 { 0x11fe, 0x8019, 0xffff, 0, 291 "Comtrol RocketPort 550/8 part B", 292 DEFAULT_RCLK * 4, 293 PUC_PORT_4S, 0x10, 0, 8, 294 }, 295 296 /* 297 * IBM SurePOS 300 Series (481033H) serial ports 298 * Details can be found on the IBM RSS websites 299 */ 300 301 { 0x1014, 0x0297, 0xffff, 0, 302 "IBM SurePOS 300 Series (481033H) serial ports", 303 DEFAULT_RCLK, 304 PUC_PORT_4S, 0x10, 4, 0 305 }, 306 307 /* 308 * SIIG Boards. 309 * 310 * SIIG provides documentation for their boards at: 311 * <URL:http://www.siig.com/downloads.asp> 312 */ 313 314 { 0x131f, 0x1010, 0xffff, 0, 315 "SIIG Cyber I/O PCI 16C550 (10x family)", 316 DEFAULT_RCLK, 317 PUC_PORT_1S1P, 0x18, 4, 0, 318 }, 319 320 { 0x131f, 0x1011, 0xffff, 0, 321 "SIIG Cyber I/O PCI 16C650 (10x family)", 322 DEFAULT_RCLK, 323 PUC_PORT_1S1P, 0x18, 4, 0, 324 }, 325 326 { 0x131f, 0x1012, 0xffff, 0, 327 "SIIG Cyber I/O PCI 16C850 (10x family)", 328 DEFAULT_RCLK, 329 PUC_PORT_1S1P, 0x18, 4, 0, 330 }, 331 332 { 0x131f, 0x1021, 0xffff, 0, 333 "SIIG Cyber Parallel Dual PCI (10x family)", 334 0, 335 PUC_PORT_2P, 0x18, 8, 0, 336 }, 337 338 { 0x131f, 0x1030, 0xffff, 0, 339 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 340 DEFAULT_RCLK, 341 PUC_PORT_2S, 0x18, 4, 0, 342 }, 343 344 { 0x131f, 0x1031, 0xffff, 0, 345 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 346 DEFAULT_RCLK, 347 PUC_PORT_2S, 0x18, 4, 0, 348 }, 349 350 { 0x131f, 0x1032, 0xffff, 0, 351 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 352 DEFAULT_RCLK, 353 PUC_PORT_2S, 0x18, 4, 0, 354 }, 355 356 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 357 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 358 DEFAULT_RCLK, 359 PUC_PORT_2S1P, 0x18, 4, 0, 360 }, 361 362 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 363 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 364 DEFAULT_RCLK, 365 PUC_PORT_2S1P, 0x18, 4, 0, 366 }, 367 368 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 369 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 370 DEFAULT_RCLK, 371 PUC_PORT_2S1P, 0x18, 4, 0, 372 }, 373 374 { 0x131f, 0x1050, 0xffff, 0, 375 "SIIG Cyber 4S PCI 16C550 (10x family)", 376 DEFAULT_RCLK, 377 PUC_PORT_4S, 0x18, 4, 0, 378 }, 379 380 { 0x131f, 0x1051, 0xffff, 0, 381 "SIIG Cyber 4S PCI 16C650 (10x family)", 382 DEFAULT_RCLK, 383 PUC_PORT_4S, 0x18, 4, 0, 384 }, 385 386 { 0x131f, 0x1052, 0xffff, 0, 387 "SIIG Cyber 4S PCI 16C850 (10x family)", 388 DEFAULT_RCLK, 389 PUC_PORT_4S, 0x18, 4, 0, 390 }, 391 392 { 0x131f, 0x2010, 0xffff, 0, 393 "SIIG Cyber I/O PCI 16C550 (20x family)", 394 DEFAULT_RCLK, 395 PUC_PORT_1S1P, 0x10, 4, 0, 396 }, 397 398 { 0x131f, 0x2011, 0xffff, 0, 399 "SIIG Cyber I/O PCI 16C650 (20x family)", 400 DEFAULT_RCLK, 401 PUC_PORT_1S1P, 0x10, 4, 0, 402 }, 403 404 { 0x131f, 0x2012, 0xffff, 0, 405 "SIIG Cyber I/O PCI 16C850 (20x family)", 406 DEFAULT_RCLK, 407 PUC_PORT_1S1P, 0x10, 4, 0, 408 }, 409 410 { 0x131f, 0x2021, 0xffff, 0, 411 "SIIG Cyber Parallel Dual PCI (20x family)", 412 0, 413 PUC_PORT_2P, 0x10, 8, 0, 414 }, 415 416 { 0x131f, 0x2030, 0xffff, 0, 417 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 418 DEFAULT_RCLK, 419 PUC_PORT_2S, 0x10, 4, 0, 420 }, 421 422 { 0x131f, 0x2031, 0xffff, 0, 423 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 424 DEFAULT_RCLK, 425 PUC_PORT_2S, 0x10, 4, 0, 426 }, 427 428 { 0x131f, 0x2032, 0xffff, 0, 429 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 430 DEFAULT_RCLK, 431 PUC_PORT_2S, 0x10, 4, 0, 432 }, 433 434 { 0x131f, 0x2040, 0xffff, 0, 435 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 436 DEFAULT_RCLK, 437 PUC_PORT_1S2P, 0x10, -1, 0, 438 .config_function = puc_config_siig 439 }, 440 441 { 0x131f, 0x2041, 0xffff, 0, 442 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 443 DEFAULT_RCLK, 444 PUC_PORT_1S2P, 0x10, -1, 0, 445 .config_function = puc_config_siig 446 }, 447 448 { 0x131f, 0x2042, 0xffff, 0, 449 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 450 DEFAULT_RCLK, 451 PUC_PORT_1S2P, 0x10, -1, 0, 452 .config_function = puc_config_siig 453 }, 454 455 { 0x131f, 0x2050, 0xffff, 0, 456 "SIIG Cyber 4S PCI 16C550 (20x family)", 457 DEFAULT_RCLK, 458 PUC_PORT_4S, 0x10, 4, 0, 459 }, 460 461 { 0x131f, 0x2051, 0xffff, 0, 462 "SIIG Cyber 4S PCI 16C650 (20x family)", 463 DEFAULT_RCLK, 464 PUC_PORT_4S, 0x10, 4, 0, 465 }, 466 467 { 0x131f, 0x2052, 0xffff, 0, 468 "SIIG Cyber 4S PCI 16C850 (20x family)", 469 DEFAULT_RCLK, 470 PUC_PORT_4S, 0x10, 4, 0, 471 }, 472 473 { 0x131f, 0x2060, 0xffff, 0, 474 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 475 DEFAULT_RCLK, 476 PUC_PORT_2S1P, 0x10, 4, 0, 477 }, 478 479 { 0x131f, 0x2061, 0xffff, 0, 480 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 481 DEFAULT_RCLK, 482 PUC_PORT_2S1P, 0x10, 4, 0, 483 }, 484 485 { 0x131f, 0x2062, 0xffff, 0, 486 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 487 DEFAULT_RCLK, 488 PUC_PORT_2S1P, 0x10, 4, 0, 489 }, 490 491 { 0x131f, 0x2081, 0xffff, 0, 492 "SIIG PS8000 8S PCI 16C650 (20x family)", 493 DEFAULT_RCLK, 494 PUC_PORT_8S, 0x10, -1, -1, 495 .config_function = puc_config_siig 496 }, 497 498 { 0x135c, 0x0010, 0xffff, 0, 499 "Quatech QSC-100", 500 -3, /* max 8x clock rate */ 501 PUC_PORT_4S, 0x14, 0, 8, 502 .config_function = puc_config_quatech 503 }, 504 505 { 0x135c, 0x0020, 0xffff, 0, 506 "Quatech DSC-100", 507 -1, /* max 2x clock rate */ 508 PUC_PORT_2S, 0x14, 0, 8, 509 .config_function = puc_config_quatech 510 }, 511 512 { 0x135c, 0x0030, 0xffff, 0, 513 "Quatech DSC-200/300", 514 -1, /* max 2x clock rate */ 515 PUC_PORT_2S, 0x14, 0, 8, 516 .config_function = puc_config_quatech 517 }, 518 519 { 0x135c, 0x0040, 0xffff, 0, 520 "Quatech QSC-200/300", 521 -3, /* max 8x clock rate */ 522 PUC_PORT_4S, 0x14, 0, 8, 523 .config_function = puc_config_quatech 524 }, 525 526 { 0x135c, 0x0050, 0xffff, 0, 527 "Quatech ESC-100D", 528 -3, /* max 8x clock rate */ 529 PUC_PORT_8S, 0x14, 0, 8, 530 .config_function = puc_config_quatech 531 }, 532 533 { 0x135c, 0x0060, 0xffff, 0, 534 "Quatech ESC-100M", 535 -3, /* max 8x clock rate */ 536 PUC_PORT_8S, 0x14, 0, 8, 537 .config_function = puc_config_quatech 538 }, 539 540 { 0x135c, 0x0170, 0xffff, 0, 541 "Quatech QSCLP-100", 542 -1, /* max 2x clock rate */ 543 PUC_PORT_4S, 0x18, 0, 8, 544 .config_function = puc_config_quatech 545 }, 546 547 { 0x135c, 0x0180, 0xffff, 0, 548 "Quatech DSCLP-100", 549 -1, /* max 3x clock rate */ 550 PUC_PORT_2S, 0x18, 0, 8, 551 .config_function = puc_config_quatech 552 }, 553 554 { 0x135c, 0x01b0, 0xffff, 0, 555 "Quatech DSCLP-200/300", 556 -1, /* max 2x clock rate */ 557 PUC_PORT_2S, 0x18, 0, 8, 558 .config_function = puc_config_quatech 559 }, 560 561 { 0x135c, 0x01e0, 0xffff, 0, 562 "Quatech ESCLP-100", 563 -3, /* max 8x clock rate */ 564 PUC_PORT_8S, 0x10, 0, 8, 565 .config_function = puc_config_quatech 566 }, 567 568 { 0x1393, 0x1024, 0xffff, 0, 569 "Moxa Technologies, Smartio CP-102E/PCIe", 570 DEFAULT_RCLK * 8, 571 PUC_PORT_2S, 0x14, 0, -1, 572 .config_function = puc_config_moxa 573 }, 574 575 { 0x1393, 0x1025, 0xffff, 0, 576 "Moxa Technologies, Smartio CP-102EL/PCIe", 577 DEFAULT_RCLK * 8, 578 PUC_PORT_2S, 0x14, 0, -1, 579 .config_function = puc_config_moxa 580 }, 581 582 { 0x1393, 0x1040, 0xffff, 0, 583 "Moxa Technologies, Smartio C104H/PCI", 584 DEFAULT_RCLK * 8, 585 PUC_PORT_4S, 0x18, 0, 8, 586 }, 587 588 { 0x1393, 0x1041, 0xffff, 0, 589 "Moxa Technologies, Smartio CP-104UL/PCI", 590 DEFAULT_RCLK * 8, 591 PUC_PORT_4S, 0x18, 0, 8, 592 }, 593 594 { 0x1393, 0x1042, 0xffff, 0, 595 "Moxa Technologies, Smartio CP-104JU/PCI", 596 DEFAULT_RCLK * 8, 597 PUC_PORT_4S, 0x18, 0, 8, 598 }, 599 600 { 0x1393, 0x1043, 0xffff, 0, 601 "Moxa Technologies, Smartio CP-104EL/PCIe", 602 DEFAULT_RCLK * 8, 603 PUC_PORT_4S, 0x18, 0, 8, 604 }, 605 606 { 0x1393, 0x1045, 0xffff, 0, 607 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 608 DEFAULT_RCLK * 8, 609 PUC_PORT_4S, 0x14, 0, -1, 610 .config_function = puc_config_moxa 611 }, 612 613 { 0x1393, 0x1120, 0xffff, 0, 614 "Moxa Technologies, CP-112UL", 615 DEFAULT_RCLK * 8, 616 PUC_PORT_2S, 0x18, 0, 8, 617 }, 618 619 { 0x1393, 0x1141, 0xffff, 0, 620 "Moxa Technologies, Industio CP-114", 621 DEFAULT_RCLK * 8, 622 PUC_PORT_4S, 0x18, 0, 8, 623 }, 624 625 { 0x1393, 0x1144, 0xffff, 0, 626 "Moxa Technologies, Smartio CP-114EL/PCIe", 627 DEFAULT_RCLK * 8, 628 PUC_PORT_4S, 0x14, 0, -1, 629 .config_function = puc_config_moxa 630 }, 631 632 { 0x1393, 0x1182, 0xffff, 0, 633 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 634 DEFAULT_RCLK * 8, 635 PUC_PORT_8S, 0x14, 0, -1, 636 .config_function = puc_config_moxa 637 }, 638 639 { 0x1393, 0x1680, 0xffff, 0, 640 "Moxa Technologies, C168H/PCI", 641 DEFAULT_RCLK * 8, 642 PUC_PORT_8S, 0x18, 0, 8, 643 }, 644 645 { 0x1393, 0x1681, 0xffff, 0, 646 "Moxa Technologies, C168U/PCI", 647 DEFAULT_RCLK * 8, 648 PUC_PORT_8S, 0x18, 0, 8, 649 }, 650 651 { 0x1393, 0x1682, 0xffff, 0, 652 "Moxa Technologies, CP-168EL/PCIe", 653 DEFAULT_RCLK * 8, 654 PUC_PORT_8S, 0x18, 0, 8, 655 }, 656 657 { 0x1393, 0x1683, 0xffff, 0, 658 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 659 DEFAULT_RCLK * 8, 660 PUC_PORT_8S, 0x14, 0, -1, 661 .config_function = puc_config_moxa 662 }, 663 664 { 0x13a8, 0x0152, 0xffff, 0, 665 "Exar XR17C/D152", 666 DEFAULT_RCLK * 8, 667 PUC_PORT_2S, 0x10, 0, -1, 668 .config_function = puc_config_exar 669 }, 670 671 { 0x13a8, 0x0154, 0xffff, 0, 672 "Exar XR17C154", 673 DEFAULT_RCLK * 8, 674 PUC_PORT_4S, 0x10, 0, -1, 675 .config_function = puc_config_exar 676 }, 677 678 { 0x13a8, 0x0158, 0xffff, 0, 679 "Exar XR17C158", 680 DEFAULT_RCLK * 8, 681 PUC_PORT_8S, 0x10, 0, -1, 682 .config_function = puc_config_exar 683 }, 684 685 { 0x13a8, 0x0258, 0xffff, 0, 686 "Exar XR17V258IV", 687 DEFAULT_RCLK * 8, 688 PUC_PORT_8S, 0x10, 0, -1, 689 .config_function = puc_config_exar 690 }, 691 692 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 693 { 0x13a8, 0x0358, 0xffff, 0, 694 "Exar XR17V358", 695 125000000, 696 PUC_PORT_8S, 0x10, 0, -1, 697 .config_function = puc_config_exar_pcie 698 }, 699 700 /* 701 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford 702 * Semiconductor OXuPCI954. Note these boards have a hardware bug in 703 * that they drive the RS-422/485 transmitters after power-on until a 704 * driver initalizes the UARTs. 705 */ 706 { 0x13fe, 0x1600, 0x1602, 0x0002, 707 "Advantech PCI-1602 Rev. A", 708 DEFAULT_RCLK * 8, 709 PUC_PORT_2S, 0x10, 0, 8, 710 .config_function = puc_config_advantech 711 }, 712 713 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */ 714 { 0x13fe, 0xa102, 0x13fe, 0xa102, 715 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)", 716 DEFAULT_RCLK * 8, 717 PUC_PORT_2S, 0x10, 4, 0, 718 .config_function = puc_config_advantech 719 }, 720 721 { 0x1407, 0x0100, 0xffff, 0, 722 "Lava Computers Dual Serial", 723 DEFAULT_RCLK, 724 PUC_PORT_2S, 0x10, 4, 0, 725 }, 726 727 { 0x1407, 0x0101, 0xffff, 0, 728 "Lava Computers Quatro A", 729 DEFAULT_RCLK, 730 PUC_PORT_2S, 0x10, 4, 0, 731 }, 732 733 { 0x1407, 0x0102, 0xffff, 0, 734 "Lava Computers Quatro B", 735 DEFAULT_RCLK, 736 PUC_PORT_2S, 0x10, 4, 0, 737 }, 738 739 { 0x1407, 0x0120, 0xffff, 0, 740 "Lava Computers Quattro-PCI A", 741 DEFAULT_RCLK, 742 PUC_PORT_2S, 0x10, 4, 0, 743 }, 744 745 { 0x1407, 0x0121, 0xffff, 0, 746 "Lava Computers Quattro-PCI B", 747 DEFAULT_RCLK, 748 PUC_PORT_2S, 0x10, 4, 0, 749 }, 750 751 { 0x1407, 0x0180, 0xffff, 0, 752 "Lava Computers Octo A", 753 DEFAULT_RCLK, 754 PUC_PORT_4S, 0x10, 4, 0, 755 }, 756 757 { 0x1407, 0x0181, 0xffff, 0, 758 "Lava Computers Octo B", 759 DEFAULT_RCLK, 760 PUC_PORT_4S, 0x10, 4, 0, 761 }, 762 763 { 0x1409, 0x7268, 0xffff, 0, 764 "Sunix SUN1888", 765 0, 766 PUC_PORT_2P, 0x10, 0, 8, 767 }, 768 769 { 0x1409, 0x7168, 0xffff, 0, 770 NULL, 771 DEFAULT_RCLK * 8, 772 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 773 .config_function = puc_config_timedia 774 }, 775 776 /* 777 * Boards with an Oxford Semiconductor chip. 778 * 779 * Oxford Semiconductor provides documentation for their chip at: 780 * <URL:http://www.plxtech.com/products/uart/> 781 * 782 * As sold by Kouwell <URL:http://www.kouwell.com/>. 783 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 784 */ 785 { 786 0x1415, 0x9501, 0x10fc, 0xc070, 787 "I-O DATA RSA-PCI2/R", 788 DEFAULT_RCLK * 8, 789 PUC_PORT_2S, 0x10, 0, 8, 790 }, 791 792 { 0x1415, 0x9501, 0x131f, 0x2050, 793 "SIIG Cyber 4 PCI 16550", 794 DEFAULT_RCLK * 10, 795 PUC_PORT_4S, 0x10, 0, 8, 796 }, 797 798 { 0x1415, 0x9501, 0x131f, 0x2051, 799 "SIIG Cyber 4S PCI 16C650 (20x family)", 800 DEFAULT_RCLK * 10, 801 PUC_PORT_4S, 0x10, 0, 8, 802 }, 803 804 { 0x1415, 0x9501, 0x131f, 0x2052, 805 "SIIG Quartet Serial 850", 806 DEFAULT_RCLK * 10, 807 PUC_PORT_4S, 0x10, 0, 8, 808 }, 809 810 { 0x1415, 0x9501, 0x14db, 0x2150, 811 "Kuroutoshikou SERIAL4P-LPPCI2", 812 DEFAULT_RCLK * 10, 813 PUC_PORT_4S, 0x10, 0, 8, 814 }, 815 816 { 0x1415, 0x9501, 0xffff, 0, 817 "Oxford Semiconductor OX16PCI954 UARTs", 818 0, 819 PUC_PORT_4S, 0x10, 0, 8, 820 .config_function = puc_config_oxford_pci954 821 }, 822 823 { 0x1415, 0x950a, 0x131f, 0x2030, 824 "SIIG Cyber 2S PCIe", 825 DEFAULT_RCLK * 10, 826 PUC_PORT_2S, 0x10, 0, 8, 827 }, 828 829 { 0x1415, 0x950a, 0x131f, 0x2032, 830 "SIIG Cyber Serial Dual PCI 16C850", 831 DEFAULT_RCLK * 10, 832 PUC_PORT_4S, 0x10, 0, 8, 833 }, 834 835 { 0x1415, 0x950a, 0x131f, 0x2061, 836 "SIIG Cyber 2SP1 PCIe", 837 DEFAULT_RCLK * 10, 838 PUC_PORT_2S, 0x10, 0, 8, 839 }, 840 841 { 0x1415, 0x950a, 0xffff, 0, 842 "Oxford Semiconductor OX16PCI954 UARTs", 843 DEFAULT_RCLK, 844 PUC_PORT_4S, 0x10, 0, 8, 845 }, 846 847 { 0x1415, 0x9511, 0xffff, 0, 848 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 849 DEFAULT_RCLK, 850 PUC_PORT_4S, 0x10, 0, 8, 851 }, 852 853 { 0x1415, 0x9521, 0xffff, 0, 854 "Oxford Semiconductor OX16PCI952 UARTs", 855 DEFAULT_RCLK, 856 PUC_PORT_2S, 0x10, 4, 0, 857 }, 858 859 { 0x1415, 0x9538, 0xffff, 0, 860 "Oxford Semiconductor OX16PCI958 UARTs", 861 DEFAULT_RCLK, 862 PUC_PORT_8S, 0x18, 0, 8, 863 }, 864 865 /* 866 * Perle boards use Oxford Semiconductor chips, but they store the 867 * Oxford Semiconductor device ID as a subvendor device ID and use 868 * their own device IDs. 869 */ 870 871 { 0x155f, 0x0331, 0xffff, 0, 872 "Perle Ultraport4 Express", 873 DEFAULT_RCLK * 8, 874 PUC_PORT_4S, 0x10, 0, 8, 875 }, 876 877 { 0x155f, 0xB012, 0xffff, 0, 878 "Perle Speed2 LE", 879 DEFAULT_RCLK * 8, 880 PUC_PORT_2S, 0x10, 0, 8, 881 }, 882 883 { 0x155f, 0xB022, 0xffff, 0, 884 "Perle Speed2 LE", 885 DEFAULT_RCLK * 8, 886 PUC_PORT_2S, 0x10, 0, 8, 887 }, 888 889 { 0x155f, 0xB004, 0xffff, 0, 890 "Perle Speed4 LE", 891 DEFAULT_RCLK * 8, 892 PUC_PORT_4S, 0x10, 0, 8, 893 }, 894 895 { 0x155f, 0xB008, 0xffff, 0, 896 "Perle Speed8 LE", 897 DEFAULT_RCLK * 8, 898 PUC_PORT_8S, 0x10, 0, 8, 899 }, 900 901 902 /* 903 * Oxford Semiconductor PCI Express Expresso family 904 * 905 * Found in many 'native' PCI Express serial boards such as: 906 * 907 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 908 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 909 * 910 * Lindy 51189 (4 port) 911 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 912 * 913 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 914 * <URL:http://www.startech.com> 915 */ 916 917 { 0x1415, 0xc11b, 0xffff, 0, 918 "Oxford Semiconductor OXPCIe952 1S1P", 919 DEFAULT_RCLK * 0x22, 920 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 921 .config_function = puc_config_oxford_pcie 922 }, 923 924 { 0x1415, 0xc138, 0xffff, 0, 925 "Oxford Semiconductor OXPCIe952 UARTs", 926 DEFAULT_RCLK * 0x22, 927 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 928 .config_function = puc_config_oxford_pcie 929 }, 930 931 { 0x1415, 0xc158, 0xffff, 0, 932 "Oxford Semiconductor OXPCIe952 UARTs", 933 DEFAULT_RCLK * 0x22, 934 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 935 .config_function = puc_config_oxford_pcie 936 }, 937 938 { 0x1415, 0xc15d, 0xffff, 0, 939 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 940 DEFAULT_RCLK * 0x22, 941 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 942 .config_function = puc_config_oxford_pcie 943 }, 944 945 { 0x1415, 0xc208, 0xffff, 0, 946 "Oxford Semiconductor OXPCIe954 UARTs", 947 DEFAULT_RCLK * 0x22, 948 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 949 .config_function = puc_config_oxford_pcie 950 }, 951 952 { 0x1415, 0xc20d, 0xffff, 0, 953 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 954 DEFAULT_RCLK * 0x22, 955 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 956 .config_function = puc_config_oxford_pcie 957 }, 958 959 { 0x1415, 0xc308, 0xffff, 0, 960 "Oxford Semiconductor OXPCIe958 UARTs", 961 DEFAULT_RCLK * 0x22, 962 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 963 .config_function = puc_config_oxford_pcie 964 }, 965 966 { 0x1415, 0xc30d, 0xffff, 0, 967 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 968 DEFAULT_RCLK * 0x22, 969 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 970 .config_function = puc_config_oxford_pcie 971 }, 972 973 { 0x14d2, 0x8010, 0xffff, 0, 974 "VScom PCI-100L", 975 DEFAULT_RCLK * 8, 976 PUC_PORT_1S, 0x14, 0, 0, 977 }, 978 979 { 0x14d2, 0x8020, 0xffff, 0, 980 "VScom PCI-200L", 981 DEFAULT_RCLK * 8, 982 PUC_PORT_2S, 0x14, 4, 0, 983 }, 984 985 { 0x14d2, 0x8028, 0xffff, 0, 986 "VScom 200Li", 987 DEFAULT_RCLK, 988 PUC_PORT_2S, 0x20, 0, 8, 989 }, 990 991 /* 992 * VScom (Titan?) PCI-800L. More modern variant of the 993 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 994 * two of them obviously implemented as macro cells in 995 * the ASIC. This causes the weird port access pattern 996 * below, where two of the IO port ranges each access 997 * one of the ASIC UARTs, and a block of IO addresses 998 * access the external UARTs. 999 */ 1000 { 0x14d2, 0x8080, 0xffff, 0, 1001 "Titan VScom PCI-800L", 1002 DEFAULT_RCLK * 8, 1003 PUC_PORT_8S, 0x14, -1, -1, 1004 .config_function = puc_config_titan 1005 }, 1006 1007 /* 1008 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 1009 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 1010 * device ID 3 and PCI device 1 device ID 4. 1011 */ 1012 { 0x14d2, 0xa003, 0xffff, 0, 1013 "Titan PCI-800H", 1014 DEFAULT_RCLK * 8, 1015 PUC_PORT_4S, 0x10, 0, 8, 1016 }, 1017 1018 { 0x14d2, 0xa004, 0xffff, 0, 1019 "Titan PCI-800H", 1020 DEFAULT_RCLK * 8, 1021 PUC_PORT_4S, 0x10, 0, 8, 1022 }, 1023 1024 { 0x14d2, 0xa005, 0xffff, 0, 1025 "Titan PCI-200H", 1026 DEFAULT_RCLK * 8, 1027 PUC_PORT_2S, 0x10, 0, 8, 1028 }, 1029 1030 { 0x14d2, 0xe020, 0xffff, 0, 1031 "Titan VScom PCI-200HV2", 1032 DEFAULT_RCLK * 8, 1033 PUC_PORT_2S, 0x10, 4, 0, 1034 }, 1035 1036 { 0x14d2, 0xa007, 0xffff, 0, 1037 "Titan VScom PCIex-800H", 1038 DEFAULT_RCLK * 8, 1039 PUC_PORT_4S, 0x10, 0, 8, 1040 }, 1041 1042 { 0x14d2, 0xa008, 0xffff, 0, 1043 "Titan VScom PCIex-800H", 1044 DEFAULT_RCLK * 8, 1045 PUC_PORT_4S, 0x10, 0, 8, 1046 }, 1047 1048 { 0x14db, 0x2130, 0xffff, 0, 1049 "Avlab Technology, PCI IO 2S", 1050 DEFAULT_RCLK, 1051 PUC_PORT_2S, 0x10, 4, 0, 1052 }, 1053 1054 { 0x14db, 0x2150, 0xffff, 0, 1055 "Avlab Low Profile PCI 4 Serial", 1056 DEFAULT_RCLK, 1057 PUC_PORT_4S, 0x10, 4, 0, 1058 }, 1059 1060 { 0x14db, 0x2152, 0xffff, 0, 1061 "Avlab Low Profile PCI 4 Serial", 1062 DEFAULT_RCLK, 1063 PUC_PORT_4S, 0x10, 4, 0, 1064 }, 1065 1066 { 0x1592, 0x0781, 0xffff, 0, 1067 "Syba Tech Ltd. PCI-4S2P-550-ECP", 1068 DEFAULT_RCLK, 1069 PUC_PORT_4S1P, 0x10, 0, -1, 1070 .config_function = puc_config_syba 1071 }, 1072 1073 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 1074 "Sunix SER5xxxx 2-port serial", 1075 DEFAULT_RCLK * 8, 1076 PUC_PORT_2S, 0x10, 0, 8, 1077 }, 1078 1079 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1080 "Sunix SER5xxxx 4-port serial", 1081 DEFAULT_RCLK * 8, 1082 PUC_PORT_4S, 0x10, 0, 8, 1083 }, 1084 1085 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1086 "Sunix SER5xxxx 8-port serial", 1087 DEFAULT_RCLK * 8, 1088 PUC_PORT_8S, -1, -1, -1, 1089 .config_function = puc_config_sunix 1090 }, 1091 1092 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1093 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1094 DEFAULT_RCLK * 8, 1095 PUC_PORT_1S1P, -1, -1, -1, 1096 .config_function = puc_config_sunix 1097 }, 1098 1099 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1100 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1101 DEFAULT_RCLK * 8, 1102 PUC_PORT_2S1P, -1, -1, -1, 1103 .config_function = puc_config_sunix 1104 }, 1105 1106 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1107 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1108 DEFAULT_RCLK * 8, 1109 PUC_PORT_4S1P, -1, -1, -1, 1110 .config_function = puc_config_sunix 1111 }, 1112 1113 { 0x5372, 0x6872, 0xffff, 0, 1114 "Feasso PCI FPP-02 2S1P", 1115 DEFAULT_RCLK, 1116 PUC_PORT_2S1P, 0x10, 4, 0, 1117 }, 1118 1119 { 0x5372, 0x6873, 0xffff, 0, 1120 "Sun 1040 PCI Quad Serial", 1121 DEFAULT_RCLK, 1122 PUC_PORT_4S, 0x10, 4, 0, 1123 }, 1124 1125 { 0x6666, 0x0001, 0xffff, 0, 1126 "Decision Computer Inc, PCCOM 4-port serial", 1127 DEFAULT_RCLK, 1128 PUC_PORT_4S, 0x1c, 0, 8, 1129 }, 1130 1131 { 0x6666, 0x0002, 0xffff, 0, 1132 "Decision Computer Inc, PCCOM 8-port serial", 1133 DEFAULT_RCLK, 1134 PUC_PORT_8S, 0x1c, 0, 8, 1135 }, 1136 1137 { 0x6666, 0x0004, 0xffff, 0, 1138 "PCCOM dual port RS232/422/485", 1139 DEFAULT_RCLK, 1140 PUC_PORT_2S, 0x1c, 0, 8, 1141 }, 1142 1143 { 0x9710, 0x9815, 0xffff, 0, 1144 "NetMos NM9815 Dual 1284 Printer port", 1145 0, 1146 PUC_PORT_2P, 0x10, 8, 0, 1147 }, 1148 1149 /* 1150 * This is more specific than the generic NM9835 entry, and is placed 1151 * here to _prevent_ puc(4) from claiming this single port card. 1152 * 1153 * uart(4) will claim this device. 1154 */ 1155 { 0x9710, 0x9835, 0x1000, 1, 1156 "NetMos NM9835 based 1-port serial", 1157 DEFAULT_RCLK, 1158 PUC_PORT_1S, 0x10, 4, 0, 1159 }, 1160 1161 { 0x9710, 0x9835, 0x1000, 2, 1162 "NetMos NM9835 based 2-port serial", 1163 DEFAULT_RCLK, 1164 PUC_PORT_2S, 0x10, 4, 0, 1165 }, 1166 1167 { 0x9710, 0x9835, 0xffff, 0, 1168 "NetMos NM9835 Dual UART and 1284 Printer port", 1169 DEFAULT_RCLK, 1170 PUC_PORT_2S1P, 0x10, 4, 0, 1171 }, 1172 1173 { 0x9710, 0x9845, 0x1000, 0x0006, 1174 "NetMos NM9845 6 Port UART", 1175 DEFAULT_RCLK, 1176 PUC_PORT_6S, 0x10, 4, 0, 1177 }, 1178 1179 { 0x9710, 0x9845, 0xffff, 0, 1180 "NetMos NM9845 Quad UART and 1284 Printer port", 1181 DEFAULT_RCLK, 1182 PUC_PORT_4S1P, 0x10, 4, 0, 1183 }, 1184 1185 { 0x9710, 0x9865, 0xa000, 0x3002, 1186 "NetMos NM9865 Dual UART", 1187 DEFAULT_RCLK, 1188 PUC_PORT_2S, 0x10, 4, 0, 1189 }, 1190 1191 { 0x9710, 0x9865, 0xa000, 0x3003, 1192 "NetMos NM9865 Triple UART", 1193 DEFAULT_RCLK, 1194 PUC_PORT_3S, 0x10, 4, 0, 1195 }, 1196 1197 { 0x9710, 0x9865, 0xa000, 0x3004, 1198 "NetMos NM9865 Quad UART", 1199 DEFAULT_RCLK, 1200 PUC_PORT_4S, 0x10, 4, 0, 1201 }, 1202 1203 { 0x9710, 0x9865, 0xa000, 0x3011, 1204 "NetMos NM9865 Single UART and 1284 Printer port", 1205 DEFAULT_RCLK, 1206 PUC_PORT_1S1P, 0x10, 4, 0, 1207 }, 1208 1209 { 0x9710, 0x9865, 0xa000, 0x3012, 1210 "NetMos NM9865 Dual UART and 1284 Printer port", 1211 DEFAULT_RCLK, 1212 PUC_PORT_2S1P, 0x10, 4, 0, 1213 }, 1214 1215 { 0x9710, 0x9865, 0xa000, 0x3020, 1216 "NetMos NM9865 Dual 1284 Printer port", 1217 DEFAULT_RCLK, 1218 PUC_PORT_2P, 0x10, 4, 0, 1219 }, 1220 1221 { 0xb00c, 0x021c, 0xffff, 0, 1222 "IC Book Labs Gunboat x4 Lite", 1223 DEFAULT_RCLK, 1224 PUC_PORT_4S, 0x10, 0, 8, 1225 .config_function = puc_config_icbook 1226 }, 1227 1228 { 0xb00c, 0x031c, 0xffff, 0, 1229 "IC Book Labs Gunboat x4 Pro", 1230 DEFAULT_RCLK, 1231 PUC_PORT_4S, 0x10, 0, 8, 1232 .config_function = puc_config_icbook 1233 }, 1234 1235 { 0xb00c, 0x041c, 0xffff, 0, 1236 "IC Book Labs Ironclad x8 Lite", 1237 DEFAULT_RCLK, 1238 PUC_PORT_8S, 0x10, 0, 8, 1239 .config_function = puc_config_icbook 1240 }, 1241 1242 { 0xb00c, 0x051c, 0xffff, 0, 1243 "IC Book Labs Ironclad x8 Pro", 1244 DEFAULT_RCLK, 1245 PUC_PORT_8S, 0x10, 0, 8, 1246 .config_function = puc_config_icbook 1247 }, 1248 1249 { 0xb00c, 0x081c, 0xffff, 0, 1250 "IC Book Labs Dreadnought x16 Pro", 1251 DEFAULT_RCLK * 8, 1252 PUC_PORT_16S, 0x10, 0, 8, 1253 .config_function = puc_config_icbook 1254 }, 1255 1256 { 0xb00c, 0x091c, 0xffff, 0, 1257 "IC Book Labs Dreadnought x16 Lite", 1258 DEFAULT_RCLK, 1259 PUC_PORT_16S, 0x10, 0, 8, 1260 .config_function = puc_config_icbook 1261 }, 1262 1263 { 0xb00c, 0x0a1c, 0xffff, 0, 1264 "IC Book Labs Gunboat x2 Low Profile", 1265 DEFAULT_RCLK, 1266 PUC_PORT_2S, 0x10, 0, 8, 1267 }, 1268 1269 { 0xb00c, 0x0b1c, 0xffff, 0, 1270 "IC Book Labs Gunboat x4 Low Profile", 1271 DEFAULT_RCLK, 1272 PUC_PORT_4S, 0x10, 0, 8, 1273 .config_function = puc_config_icbook 1274 }, 1275 1276 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1277 }; 1278 1279 static int 1280 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1281 intptr_t *res __unused) 1282 { 1283 const struct puc_cfg *cfg; 1284 struct resource *cres; 1285 struct puc_bar *bar; 1286 device_t cdev, dev; 1287 bus_size_t off; 1288 int base, crtype, fixed, high, i, oxpcie; 1289 uint8_t acr, func, mask; 1290 1291 if (cmd != PUC_CFG_SETUP) 1292 return (ENXIO); 1293 1294 base = fixed = oxpcie = 0; 1295 crtype = SYS_RES_IOPORT; 1296 acr = mask = 0x0; 1297 func = high = 1; 1298 off = 0x60; 1299 1300 cfg = sc->sc_cfg; 1301 switch (cfg->subvendor) { 1302 case 0x13fe: 1303 switch (cfg->device) { 1304 case 0xa102: 1305 high = 0; 1306 break; 1307 default: 1308 break; 1309 } 1310 default: 1311 break; 1312 } 1313 if (fixed == 1) 1314 goto setup; 1315 1316 dev = sc->sc_dev; 1317 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1318 pci_get_slot(dev), func); 1319 if (cdev == NULL) { 1320 device_printf(dev, "could not find config function\n"); 1321 return (ENXIO); 1322 } 1323 1324 i = PCIR_BAR(0); 1325 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE); 1326 if (cres == NULL) { 1327 device_printf(dev, "could not allocate config resource\n"); 1328 return (ENXIO); 1329 } 1330 1331 if (oxpcie == 0) { 1332 mask = bus_read_1(cres, off); 1333 if (pci_get_function(dev) == 1) 1334 base = 4; 1335 } 1336 1337 setup: 1338 for (i = 0; i < sc->sc_nports; ++i) { 1339 device_printf(dev, "port %d: ", i); 1340 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); 1341 if (bar == NULL) { 1342 printf("could not get BAR\n"); 1343 continue; 1344 } 1345 1346 if (fixed == 0) { 1347 if ((mask & (1 << (base + i))) == 0) { 1348 acr = 0; 1349 printf("RS-232\n"); 1350 } else { 1351 acr = (high == 1 ? 0x18 : 0x10); 1352 printf("RS-422/RS-485, active-%s auto-DTR\n", 1353 high == 1 ? "high" : "low"); 1354 } 1355 } 1356 1357 bus_write_1(bar->b_res, REG_SPR, REG_ACR); 1358 bus_write_1(bar->b_res, REG_ICR, acr); 1359 } 1360 1361 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres); 1362 return (0); 1363 } 1364 1365 static int 1366 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port, 1367 intptr_t *res) 1368 { 1369 1370 switch (cmd) { 1371 case PUC_CFG_GET_OFS: 1372 *res = 8 * (port & 1); 1373 return (0); 1374 case PUC_CFG_GET_RID: 1375 *res = 0x14 + (port >> 1) * 4; 1376 return (0); 1377 default: 1378 break; 1379 } 1380 return (ENXIO); 1381 } 1382 1383 static int 1384 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1385 intptr_t *res) 1386 { 1387 const struct puc_cfg *cfg = sc->sc_cfg; 1388 1389 if (cmd == PUC_CFG_GET_OFS) { 1390 if (cfg->subdevice == 0x1282) /* Everest SP */ 1391 port <<= 1; 1392 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1393 port = (port == 3) ? 4 : port; 1394 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1395 return (0); 1396 } 1397 return (ENXIO); 1398 } 1399 1400 static int 1401 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1402 int port, intptr_t *res) 1403 { 1404 1405 if (cmd == PUC_CFG_GET_OFS) { 1406 *res = port * 0x200; 1407 return (0); 1408 } 1409 return (ENXIO); 1410 } 1411 1412 static int 1413 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1414 int port, intptr_t *res) 1415 { 1416 1417 if (cmd == PUC_CFG_GET_OFS) { 1418 *res = port * 0x400; 1419 return (0); 1420 } 1421 return (ENXIO); 1422 } 1423 1424 static int 1425 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1426 int port __unused, intptr_t *res) 1427 { 1428 1429 if (cmd == PUC_CFG_GET_ILR) { 1430 *res = PUC_ILR_DIGI; 1431 return (0); 1432 } 1433 return (ENXIO); 1434 } 1435 1436 static int 1437 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1438 intptr_t *res) 1439 { 1440 const struct puc_cfg *cfg = sc->sc_cfg; 1441 1442 if (cmd == PUC_CFG_GET_OFS) { 1443 if (port == 3 && (cfg->device == 0x1045 || 1444 cfg->device == 0x1144)) 1445 port = 7; 1446 *res = port * 0x200; 1447 1448 return 0; 1449 } 1450 return (ENXIO); 1451 } 1452 1453 static int 1454 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1455 int port __unused, intptr_t *res) 1456 { 1457 const struct puc_cfg *cfg = sc->sc_cfg; 1458 struct puc_bar *bar; 1459 uint8_t v0, v1; 1460 1461 switch (cmd) { 1462 case PUC_CFG_SETUP: 1463 /* 1464 * Check if the scratchpad register is enabled or if the 1465 * interrupt status and options registers are active. 1466 */ 1467 bar = puc_get_bar(sc, cfg->rid); 1468 if (bar == NULL) 1469 return (ENXIO); 1470 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); 1471 bus_write_1(bar->b_res, REG_SPR, 0); 1472 v0 = bus_read_1(bar->b_res, REG_SPR); 1473 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); 1474 v1 = bus_read_1(bar->b_res, REG_SPR); 1475 bus_write_1(bar->b_res, REG_LCR, 0); 1476 sc->sc_cfg_data = (v0 << 8) | v1; 1477 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1478 /* 1479 * The SPR register echoed the two values written 1480 * by us. This means that the SPAD jumper is set. 1481 */ 1482 device_printf(sc->sc_dev, "warning: extra features " 1483 "not usable -- SPAD compatibility enabled\n"); 1484 return (0); 1485 } 1486 if (v0 != 0) { 1487 /* 1488 * The first value doesn't match. This can only mean 1489 * that the SPAD jumper is not set and that a non- 1490 * standard fixed clock multiplier jumper is set. 1491 */ 1492 if (bootverbose) 1493 device_printf(sc->sc_dev, "fixed clock rate " 1494 "multiplier of %d\n", 1 << v0); 1495 if (v0 < -cfg->clock) 1496 device_printf(sc->sc_dev, "warning: " 1497 "suboptimal fixed clock rate multiplier " 1498 "setting\n"); 1499 return (0); 1500 } 1501 /* 1502 * The first value matched, but the second didn't. We know 1503 * that the SPAD jumper is not set. We also know that the 1504 * clock rate multiplier is software controlled *and* that 1505 * we just programmed it to the maximum allowed. 1506 */ 1507 if (bootverbose) 1508 device_printf(sc->sc_dev, "clock rate multiplier of " 1509 "%d selected\n", 1 << -cfg->clock); 1510 return (0); 1511 case PUC_CFG_GET_CLOCK: 1512 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1513 v1 = sc->sc_cfg_data & 0xff; 1514 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1515 /* 1516 * XXX With the SPAD jumper applied, there's no 1517 * easy way of knowing if there's also a clock 1518 * rate multiplier jumper installed. Let's hope 1519 * not ... 1520 */ 1521 *res = DEFAULT_RCLK; 1522 } else if (v0 == 0) { 1523 /* 1524 * No clock rate multiplier jumper installed, 1525 * so we programmed the board with the maximum 1526 * multiplier allowed as given to us in the 1527 * clock field of the config record (negated). 1528 */ 1529 *res = DEFAULT_RCLK << -cfg->clock; 1530 } else 1531 *res = DEFAULT_RCLK << v0; 1532 return (0); 1533 case PUC_CFG_GET_ILR: 1534 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1535 v1 = sc->sc_cfg_data & 0xff; 1536 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? 1537 PUC_ILR_NONE : PUC_ILR_QUATECH; 1538 return (0); 1539 default: 1540 break; 1541 } 1542 return (ENXIO); 1543 } 1544 1545 static int 1546 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1547 intptr_t *res) 1548 { 1549 static int base[] = { 0x251, 0x3f0, 0 }; 1550 const struct puc_cfg *cfg = sc->sc_cfg; 1551 struct puc_bar *bar; 1552 int efir, idx, ofs; 1553 uint8_t v; 1554 1555 switch (cmd) { 1556 case PUC_CFG_SETUP: 1557 bar = puc_get_bar(sc, cfg->rid); 1558 if (bar == NULL) 1559 return (ENXIO); 1560 1561 /* configure both W83877TFs */ 1562 bus_write_1(bar->b_res, 0x250, 0x89); 1563 bus_write_1(bar->b_res, 0x3f0, 0x87); 1564 bus_write_1(bar->b_res, 0x3f0, 0x87); 1565 idx = 0; 1566 while (base[idx] != 0) { 1567 efir = base[idx]; 1568 bus_write_1(bar->b_res, efir, 0x09); 1569 v = bus_read_1(bar->b_res, efir + 1); 1570 if ((v & 0x0f) != 0x0c) 1571 return (ENXIO); 1572 bus_write_1(bar->b_res, efir, 0x16); 1573 v = bus_read_1(bar->b_res, efir + 1); 1574 bus_write_1(bar->b_res, efir, 0x16); 1575 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1576 bus_write_1(bar->b_res, efir, 0x16); 1577 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1578 ofs = base[idx] & 0x300; 1579 bus_write_1(bar->b_res, efir, 0x23); 1580 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1581 bus_write_1(bar->b_res, efir, 0x24); 1582 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1583 bus_write_1(bar->b_res, efir, 0x25); 1584 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1585 bus_write_1(bar->b_res, efir, 0x17); 1586 bus_write_1(bar->b_res, efir + 1, 0x03); 1587 bus_write_1(bar->b_res, efir, 0x28); 1588 bus_write_1(bar->b_res, efir + 1, 0x43); 1589 idx++; 1590 } 1591 bus_write_1(bar->b_res, 0x250, 0xaa); 1592 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1593 return (0); 1594 case PUC_CFG_GET_OFS: 1595 switch (port) { 1596 case 0: 1597 *res = 0x2f8; 1598 return (0); 1599 case 1: 1600 *res = 0x2e8; 1601 return (0); 1602 case 2: 1603 *res = 0x3f8; 1604 return (0); 1605 case 3: 1606 *res = 0x3e8; 1607 return (0); 1608 case 4: 1609 *res = 0x278; 1610 return (0); 1611 } 1612 break; 1613 default: 1614 break; 1615 } 1616 return (ENXIO); 1617 } 1618 1619 static int 1620 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1621 intptr_t *res) 1622 { 1623 const struct puc_cfg *cfg = sc->sc_cfg; 1624 1625 switch (cmd) { 1626 case PUC_CFG_GET_OFS: 1627 if (cfg->ports == PUC_PORT_8S) { 1628 *res = (port > 4) ? 8 * (port - 4) : 0; 1629 return (0); 1630 } 1631 break; 1632 case PUC_CFG_GET_RID: 1633 if (cfg->ports == PUC_PORT_8S) { 1634 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1635 return (0); 1636 } 1637 if (cfg->ports == PUC_PORT_2S1P) { 1638 switch (port) { 1639 case 0: *res = 0x10; return (0); 1640 case 1: *res = 0x14; return (0); 1641 case 2: *res = 0x1c; return (0); 1642 } 1643 } 1644 break; 1645 default: 1646 break; 1647 } 1648 return (ENXIO); 1649 } 1650 1651 static int 1652 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1653 intptr_t *res) 1654 { 1655 static const uint16_t dual[] = { 1656 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1657 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1658 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1659 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1660 0xD079, 0 1661 }; 1662 static const uint16_t quad[] = { 1663 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1664 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1665 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1666 0xB157, 0 1667 }; 1668 static const uint16_t octa[] = { 1669 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1670 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1671 }; 1672 static const struct { 1673 int ports; 1674 const uint16_t *ids; 1675 } subdevs[] = { 1676 { 2, dual }, 1677 { 4, quad }, 1678 { 8, octa }, 1679 { 0, NULL } 1680 }; 1681 static char desc[64]; 1682 int dev, id; 1683 uint16_t subdev; 1684 1685 switch (cmd) { 1686 case PUC_CFG_GET_CLOCK: 1687 if (port < 2) 1688 *res = DEFAULT_RCLK * 8; 1689 else 1690 *res = DEFAULT_RCLK; 1691 return (0); 1692 case PUC_CFG_GET_DESC: 1693 snprintf(desc, sizeof(desc), 1694 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1695 *res = (intptr_t)desc; 1696 return (0); 1697 case PUC_CFG_GET_NPORTS: 1698 subdev = pci_get_subdevice(sc->sc_dev); 1699 dev = 0; 1700 while (subdevs[dev].ports != 0) { 1701 id = 0; 1702 while (subdevs[dev].ids[id] != 0) { 1703 if (subdev == subdevs[dev].ids[id]) { 1704 sc->sc_cfg_data = subdevs[dev].ports; 1705 *res = sc->sc_cfg_data; 1706 return (0); 1707 } 1708 id++; 1709 } 1710 dev++; 1711 } 1712 return (ENXIO); 1713 case PUC_CFG_GET_OFS: 1714 *res = (port == 1 || port == 3) ? 8 : 0; 1715 return (0); 1716 case PUC_CFG_GET_RID: 1717 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1718 return (0); 1719 case PUC_CFG_GET_TYPE: 1720 *res = PUC_TYPE_SERIAL; 1721 return (0); 1722 default: 1723 break; 1724 } 1725 return (ENXIO); 1726 } 1727 1728 static int 1729 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1730 int port __unused, intptr_t *res) 1731 { 1732 1733 switch (cmd) { 1734 case PUC_CFG_GET_CLOCK: 1735 /* 1736 * OXu16PCI954 use a 14.7456 MHz clock by default while 1737 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1738 */ 1739 if (pci_get_revid(sc->sc_dev) == 1) 1740 *res = DEFAULT_RCLK * 8; 1741 else 1742 *res = DEFAULT_RCLK; 1743 return (0); 1744 default: 1745 break; 1746 } 1747 return (ENXIO); 1748 } 1749 1750 static int 1751 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1752 intptr_t *res) 1753 { 1754 const struct puc_cfg *cfg = sc->sc_cfg; 1755 int idx; 1756 struct puc_bar *bar; 1757 uint8_t value; 1758 1759 switch (cmd) { 1760 case PUC_CFG_SETUP: 1761 device_printf(sc->sc_dev, "%d UARTs detected\n", 1762 sc->sc_nports); 1763 1764 /* Set UARTs to enhanced mode */ 1765 bar = puc_get_bar(sc, cfg->rid); 1766 if (bar == NULL) 1767 return (ENXIO); 1768 for (idx = 0; idx < sc->sc_nports; idx++) { 1769 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1770 0x92); 1771 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1772 value | 0x10); 1773 } 1774 return (0); 1775 case PUC_CFG_GET_LEN: 1776 *res = 0x200; 1777 return (0); 1778 case PUC_CFG_GET_NPORTS: 1779 /* 1780 * Check if we are being called from puc_bfe_attach() 1781 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1782 * puc_get_bar(), so we return a value of 16. This has 1783 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, 1784 * sc->sc_cfg_data will not contain the true number of 1785 * ports in PUC_CFG_GET_DESC, but we are not implementing 1786 * that call for this device family anyway. 1787 * 1788 * The check is for initialization of sc->sc_bar[idx], 1789 * which is only done in puc_bfe_attach(). 1790 */ 1791 idx = 0; 1792 do { 1793 if (sc->sc_bar[idx++].b_rid != -1) { 1794 sc->sc_cfg_data = 16; 1795 *res = sc->sc_cfg_data; 1796 return (0); 1797 } 1798 } while (idx < PUC_PCI_BARS); 1799 1800 bar = puc_get_bar(sc, cfg->rid); 1801 if (bar == NULL) 1802 return (ENXIO); 1803 1804 value = bus_read_1(bar->b_res, 0x04); 1805 if (value == 0) 1806 return (ENXIO); 1807 1808 sc->sc_cfg_data = value; 1809 *res = sc->sc_cfg_data; 1810 return (0); 1811 case PUC_CFG_GET_OFS: 1812 *res = 0x1000 + (port << 9); 1813 return (0); 1814 case PUC_CFG_GET_TYPE: 1815 *res = PUC_TYPE_SERIAL; 1816 return (0); 1817 default: 1818 break; 1819 } 1820 return (ENXIO); 1821 } 1822 1823 static int 1824 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1825 intptr_t *res) 1826 { 1827 int error; 1828 1829 switch (cmd) { 1830 case PUC_CFG_GET_OFS: 1831 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1832 if (error != 0) 1833 return (error); 1834 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1835 return (0); 1836 case PUC_CFG_GET_RID: 1837 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1838 if (error != 0) 1839 return (error); 1840 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1841 return (0); 1842 default: 1843 break; 1844 } 1845 return (ENXIO); 1846 } 1847 1848 static int 1849 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1850 int port, intptr_t *res) 1851 { 1852 1853 switch (cmd) { 1854 case PUC_CFG_GET_OFS: 1855 *res = (port < 3) ? 0 : (port - 2) << 3; 1856 return (0); 1857 case PUC_CFG_GET_RID: 1858 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1859 return (0); 1860 default: 1861 break; 1862 } 1863 return (ENXIO); 1864 } 1865