1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_exar; 53 static puc_config_f puc_config_exar_pcie; 54 static puc_config_f puc_config_icbook; 55 static puc_config_f puc_config_moxa; 56 static puc_config_f puc_config_oxford_pcie; 57 static puc_config_f puc_config_quatech; 58 static puc_config_f puc_config_syba; 59 static puc_config_f puc_config_siig; 60 static puc_config_f puc_config_timedia; 61 static puc_config_f puc_config_titan; 62 63 const struct puc_cfg puc_pci_devices[] = { 64 65 { 0x0009, 0x7168, 0xffff, 0, 66 "Sunix SUN1889", 67 DEFAULT_RCLK * 8, 68 PUC_PORT_2S, 0x10, 0, 8, 69 }, 70 71 { 0x103c, 0x1048, 0x103c, 0x1049, 72 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 73 DEFAULT_RCLK, 74 PUC_PORT_3S, 0x10, 0, -1, 75 .config_function = puc_config_diva 76 }, 77 78 { 0x103c, 0x1048, 0x103c, 0x104a, 79 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 80 DEFAULT_RCLK, 81 PUC_PORT_2S, 0x10, 0, -1, 82 .config_function = puc_config_diva 83 }, 84 85 { 0x103c, 0x1048, 0x103c, 0x104b, 86 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 87 DEFAULT_RCLK, 88 PUC_PORT_4S, 0x10, 0, -1, 89 .config_function = puc_config_diva 90 }, 91 92 { 0x103c, 0x1048, 0x103c, 0x1223, 93 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 94 DEFAULT_RCLK, 95 PUC_PORT_3S, 0x10, 0, -1, 96 .config_function = puc_config_diva 97 }, 98 99 { 0x103c, 0x1048, 0x103c, 0x1226, 100 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 101 DEFAULT_RCLK, 102 PUC_PORT_3S, 0x10, 0, -1, 103 .config_function = puc_config_diva 104 }, 105 106 { 0x103c, 0x1048, 0x103c, 0x1282, 107 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 108 DEFAULT_RCLK, 109 PUC_PORT_3S, 0x10, 0, -1, 110 .config_function = puc_config_diva 111 }, 112 113 { 0x10b5, 0x1076, 0x10b5, 0x1076, 114 "VScom PCI-800", 115 DEFAULT_RCLK * 8, 116 PUC_PORT_8S, 0x18, 0, 8, 117 }, 118 119 { 0x10b5, 0x1077, 0x10b5, 0x1077, 120 "VScom PCI-400", 121 DEFAULT_RCLK * 8, 122 PUC_PORT_4S, 0x18, 0, 8, 123 }, 124 125 { 0x10b5, 0x1103, 0x10b5, 0x1103, 126 "VScom PCI-200", 127 DEFAULT_RCLK * 8, 128 PUC_PORT_2S, 0x18, 4, 0, 129 }, 130 131 /* 132 * Boca Research Turbo Serial 658 (8 serial port) card. 133 * Appears to be the same as Chase Research PLC PCI-FAST8 134 * and Perle PCI-FAST8 Multi-Port serial cards. 135 */ 136 { 0x10b5, 0x9050, 0x12e0, 0x0021, 137 "Boca Research Turbo Serial 658", 138 DEFAULT_RCLK * 4, 139 PUC_PORT_8S, 0x18, 0, 8, 140 }, 141 142 { 0x10b5, 0x9050, 0x12e0, 0x0031, 143 "Boca Research Turbo Serial 654", 144 DEFAULT_RCLK * 4, 145 PUC_PORT_4S, 0x18, 0, 8, 146 }, 147 148 /* 149 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 150 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 151 * into the subsystem fields, and claims that it's a 152 * network/misc (0x02/0x80) device. 153 */ 154 { 0x10b5, 0x9050, 0xd84d, 0x6808, 155 "Dolphin Peripherals 4035", 156 DEFAULT_RCLK, 157 PUC_PORT_2S, 0x18, 4, 0, 158 }, 159 160 /* 161 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 162 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 163 * into the subsystem fields, and claims that it's a 164 * network/misc (0x02/0x80) device. 165 */ 166 { 0x10b5, 0x9050, 0xd84d, 0x6810, 167 "Dolphin Peripherals 4014", 168 0, 169 PUC_PORT_2P, 0x20, 4, 0, 170 }, 171 172 { 0x10e8, 0x818e, 0xffff, 0, 173 "Applied Micro Circuits 8 Port UART", 174 DEFAULT_RCLK, 175 PUC_PORT_8S, 0x14, -1, -1, 176 .config_function = puc_config_amc 177 }, 178 179 { 0x11fe, 0x8010, 0xffff, 0, 180 "Comtrol RocketPort 550/8 RJ11 part A", 181 DEFAULT_RCLK * 4, 182 PUC_PORT_4S, 0x10, 0, 8, 183 }, 184 185 { 0x11fe, 0x8011, 0xffff, 0, 186 "Comtrol RocketPort 550/8 RJ11 part B", 187 DEFAULT_RCLK * 4, 188 PUC_PORT_4S, 0x10, 0, 8, 189 }, 190 191 { 0x11fe, 0x8012, 0xffff, 0, 192 "Comtrol RocketPort 550/8 Octa part A", 193 DEFAULT_RCLK * 4, 194 PUC_PORT_4S, 0x10, 0, 8, 195 }, 196 197 { 0x11fe, 0x8013, 0xffff, 0, 198 "Comtrol RocketPort 550/8 Octa part B", 199 DEFAULT_RCLK * 4, 200 PUC_PORT_4S, 0x10, 0, 8, 201 }, 202 203 { 0x11fe, 0x8014, 0xffff, 0, 204 "Comtrol RocketPort 550/4 RJ45", 205 DEFAULT_RCLK * 4, 206 PUC_PORT_4S, 0x10, 0, 8, 207 }, 208 209 { 0x11fe, 0x8015, 0xffff, 0, 210 "Comtrol RocketPort 550/Quad", 211 DEFAULT_RCLK * 4, 212 PUC_PORT_4S, 0x10, 0, 8, 213 }, 214 215 { 0x11fe, 0x8016, 0xffff, 0, 216 "Comtrol RocketPort 550/16 part A", 217 DEFAULT_RCLK * 4, 218 PUC_PORT_4S, 0x10, 0, 8, 219 }, 220 221 { 0x11fe, 0x8017, 0xffff, 0, 222 "Comtrol RocketPort 550/16 part B", 223 DEFAULT_RCLK * 4, 224 PUC_PORT_12S, 0x10, 0, 8, 225 }, 226 227 { 0x11fe, 0x8018, 0xffff, 0, 228 "Comtrol RocketPort 550/8 part A", 229 DEFAULT_RCLK * 4, 230 PUC_PORT_4S, 0x10, 0, 8, 231 }, 232 233 { 0x11fe, 0x8019, 0xffff, 0, 234 "Comtrol RocketPort 550/8 part B", 235 DEFAULT_RCLK * 4, 236 PUC_PORT_4S, 0x10, 0, 8, 237 }, 238 239 /* 240 * IBM SurePOS 300 Series (481033H) serial ports 241 * Details can be found on the IBM RSS websites 242 */ 243 244 { 0x1014, 0x0297, 0xffff, 0, 245 "IBM SurePOS 300 Series (481033H) serial ports", 246 DEFAULT_RCLK, 247 PUC_PORT_4S, 0x10, 4, 0 248 }, 249 250 /* 251 * SIIG Boards. 252 * 253 * SIIG provides documentation for their boards at: 254 * <URL:http://www.siig.com/downloads.asp> 255 */ 256 257 { 0x131f, 0x1010, 0xffff, 0, 258 "SIIG Cyber I/O PCI 16C550 (10x family)", 259 DEFAULT_RCLK, 260 PUC_PORT_1S1P, 0x18, 4, 0, 261 }, 262 263 { 0x131f, 0x1011, 0xffff, 0, 264 "SIIG Cyber I/O PCI 16C650 (10x family)", 265 DEFAULT_RCLK, 266 PUC_PORT_1S1P, 0x18, 4, 0, 267 }, 268 269 { 0x131f, 0x1012, 0xffff, 0, 270 "SIIG Cyber I/O PCI 16C850 (10x family)", 271 DEFAULT_RCLK, 272 PUC_PORT_1S1P, 0x18, 4, 0, 273 }, 274 275 { 0x131f, 0x1021, 0xffff, 0, 276 "SIIG Cyber Parallel Dual PCI (10x family)", 277 0, 278 PUC_PORT_2P, 0x18, 8, 0, 279 }, 280 281 { 0x131f, 0x1030, 0xffff, 0, 282 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 283 DEFAULT_RCLK, 284 PUC_PORT_2S, 0x18, 4, 0, 285 }, 286 287 { 0x131f, 0x1031, 0xffff, 0, 288 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 289 DEFAULT_RCLK, 290 PUC_PORT_2S, 0x18, 4, 0, 291 }, 292 293 { 0x131f, 0x1032, 0xffff, 0, 294 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 295 DEFAULT_RCLK, 296 PUC_PORT_2S, 0x18, 4, 0, 297 }, 298 299 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 300 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 301 DEFAULT_RCLK, 302 PUC_PORT_2S1P, 0x18, 4, 0, 303 }, 304 305 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 306 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 307 DEFAULT_RCLK, 308 PUC_PORT_2S1P, 0x18, 4, 0, 309 }, 310 311 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 312 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 313 DEFAULT_RCLK, 314 PUC_PORT_2S1P, 0x18, 4, 0, 315 }, 316 317 { 0x131f, 0x1050, 0xffff, 0, 318 "SIIG Cyber 4S PCI 16C550 (10x family)", 319 DEFAULT_RCLK, 320 PUC_PORT_4S, 0x18, 4, 0, 321 }, 322 323 { 0x131f, 0x1051, 0xffff, 0, 324 "SIIG Cyber 4S PCI 16C650 (10x family)", 325 DEFAULT_RCLK, 326 PUC_PORT_4S, 0x18, 4, 0, 327 }, 328 329 { 0x131f, 0x1052, 0xffff, 0, 330 "SIIG Cyber 4S PCI 16C850 (10x family)", 331 DEFAULT_RCLK, 332 PUC_PORT_4S, 0x18, 4, 0, 333 }, 334 335 { 0x131f, 0x2010, 0xffff, 0, 336 "SIIG Cyber I/O PCI 16C550 (20x family)", 337 DEFAULT_RCLK, 338 PUC_PORT_1S1P, 0x10, 4, 0, 339 }, 340 341 { 0x131f, 0x2011, 0xffff, 0, 342 "SIIG Cyber I/O PCI 16C650 (20x family)", 343 DEFAULT_RCLK, 344 PUC_PORT_1S1P, 0x10, 4, 0, 345 }, 346 347 { 0x131f, 0x2012, 0xffff, 0, 348 "SIIG Cyber I/O PCI 16C850 (20x family)", 349 DEFAULT_RCLK, 350 PUC_PORT_1S1P, 0x10, 4, 0, 351 }, 352 353 { 0x131f, 0x2021, 0xffff, 0, 354 "SIIG Cyber Parallel Dual PCI (20x family)", 355 0, 356 PUC_PORT_2P, 0x10, 8, 0, 357 }, 358 359 { 0x131f, 0x2030, 0xffff, 0, 360 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 361 DEFAULT_RCLK, 362 PUC_PORT_2S, 0x10, 4, 0, 363 }, 364 365 { 0x131f, 0x2031, 0xffff, 0, 366 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 367 DEFAULT_RCLK, 368 PUC_PORT_2S, 0x10, 4, 0, 369 }, 370 371 { 0x131f, 0x2032, 0xffff, 0, 372 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 373 DEFAULT_RCLK, 374 PUC_PORT_2S, 0x10, 4, 0, 375 }, 376 377 { 0x131f, 0x2040, 0xffff, 0, 378 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 379 DEFAULT_RCLK, 380 PUC_PORT_1S2P, 0x10, -1, 0, 381 .config_function = puc_config_siig 382 }, 383 384 { 0x131f, 0x2041, 0xffff, 0, 385 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 386 DEFAULT_RCLK, 387 PUC_PORT_1S2P, 0x10, -1, 0, 388 .config_function = puc_config_siig 389 }, 390 391 { 0x131f, 0x2042, 0xffff, 0, 392 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 393 DEFAULT_RCLK, 394 PUC_PORT_1S2P, 0x10, -1, 0, 395 .config_function = puc_config_siig 396 }, 397 398 { 0x131f, 0x2050, 0xffff, 0, 399 "SIIG Cyber 4S PCI 16C550 (20x family)", 400 DEFAULT_RCLK, 401 PUC_PORT_4S, 0x10, 4, 0, 402 }, 403 404 { 0x131f, 0x2051, 0xffff, 0, 405 "SIIG Cyber 4S PCI 16C650 (20x family)", 406 DEFAULT_RCLK, 407 PUC_PORT_4S, 0x10, 4, 0, 408 }, 409 410 { 0x131f, 0x2052, 0xffff, 0, 411 "SIIG Cyber 4S PCI 16C850 (20x family)", 412 DEFAULT_RCLK, 413 PUC_PORT_4S, 0x10, 4, 0, 414 }, 415 416 { 0x131f, 0x2060, 0xffff, 0, 417 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 418 DEFAULT_RCLK, 419 PUC_PORT_2S1P, 0x10, 4, 0, 420 }, 421 422 { 0x131f, 0x2061, 0xffff, 0, 423 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 424 DEFAULT_RCLK, 425 PUC_PORT_2S1P, 0x10, 4, 0, 426 }, 427 428 { 0x131f, 0x2062, 0xffff, 0, 429 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 430 DEFAULT_RCLK, 431 PUC_PORT_2S1P, 0x10, 4, 0, 432 }, 433 434 { 0x131f, 0x2081, 0xffff, 0, 435 "SIIG PS8000 8S PCI 16C650 (20x family)", 436 DEFAULT_RCLK, 437 PUC_PORT_8S, 0x10, -1, -1, 438 .config_function = puc_config_siig 439 }, 440 441 { 0x135c, 0x0010, 0xffff, 0, 442 "Quatech QSC-100", 443 -3, /* max 8x clock rate */ 444 PUC_PORT_4S, 0x14, 0, 8, 445 .config_function = puc_config_quatech 446 }, 447 448 { 0x135c, 0x0020, 0xffff, 0, 449 "Quatech DSC-100", 450 -1, /* max 2x clock rate */ 451 PUC_PORT_2S, 0x14, 0, 8, 452 .config_function = puc_config_quatech 453 }, 454 455 { 0x135c, 0x0030, 0xffff, 0, 456 "Quatech DSC-200/300", 457 -1, /* max 2x clock rate */ 458 PUC_PORT_2S, 0x14, 0, 8, 459 .config_function = puc_config_quatech 460 }, 461 462 { 0x135c, 0x0040, 0xffff, 0, 463 "Quatech QSC-200/300", 464 -3, /* max 8x clock rate */ 465 PUC_PORT_4S, 0x14, 0, 8, 466 .config_function = puc_config_quatech 467 }, 468 469 { 0x135c, 0x0050, 0xffff, 0, 470 "Quatech ESC-100D", 471 -3, /* max 8x clock rate */ 472 PUC_PORT_8S, 0x14, 0, 8, 473 .config_function = puc_config_quatech 474 }, 475 476 { 0x135c, 0x0060, 0xffff, 0, 477 "Quatech ESC-100M", 478 -3, /* max 8x clock rate */ 479 PUC_PORT_8S, 0x14, 0, 8, 480 .config_function = puc_config_quatech 481 }, 482 483 { 0x135c, 0x0170, 0xffff, 0, 484 "Quatech QSCLP-100", 485 -1, /* max 2x clock rate */ 486 PUC_PORT_4S, 0x18, 0, 8, 487 .config_function = puc_config_quatech 488 }, 489 490 { 0x135c, 0x0180, 0xffff, 0, 491 "Quatech DSCLP-100", 492 -1, /* max 3x clock rate */ 493 PUC_PORT_2S, 0x18, 0, 8, 494 .config_function = puc_config_quatech 495 }, 496 497 { 0x135c, 0x01b0, 0xffff, 0, 498 "Quatech DSCLP-200/300", 499 -1, /* max 2x clock rate */ 500 PUC_PORT_2S, 0x18, 0, 8, 501 .config_function = puc_config_quatech 502 }, 503 504 { 0x135c, 0x01e0, 0xffff, 0, 505 "Quatech ESCLP-100", 506 -3, /* max 8x clock rate */ 507 PUC_PORT_8S, 0x10, 0, 8, 508 .config_function = puc_config_quatech 509 }, 510 511 { 0x1393, 0x1024, 0xffff, 0, 512 "Moxa Technologies, Smartio CP-102E/PCIe", 513 DEFAULT_RCLK * 8, 514 PUC_PORT_2S, 0x14, 0, -1, 515 .config_function = puc_config_moxa 516 }, 517 518 { 0x1393, 0x1025, 0xffff, 0, 519 "Moxa Technologies, Smartio CP-102EL/PCIe", 520 DEFAULT_RCLK * 8, 521 PUC_PORT_2S, 0x14, 0, -1, 522 .config_function = puc_config_moxa 523 }, 524 525 { 0x1393, 0x1040, 0xffff, 0, 526 "Moxa Technologies, Smartio C104H/PCI", 527 DEFAULT_RCLK * 8, 528 PUC_PORT_4S, 0x18, 0, 8, 529 }, 530 531 { 0x1393, 0x1041, 0xffff, 0, 532 "Moxa Technologies, Smartio CP-104UL/PCI", 533 DEFAULT_RCLK * 8, 534 PUC_PORT_4S, 0x18, 0, 8, 535 }, 536 537 { 0x1393, 0x1042, 0xffff, 0, 538 "Moxa Technologies, Smartio CP-104JU/PCI", 539 DEFAULT_RCLK * 8, 540 PUC_PORT_4S, 0x18, 0, 8, 541 }, 542 543 { 0x1393, 0x1043, 0xffff, 0, 544 "Moxa Technologies, Smartio CP-104EL/PCIe", 545 DEFAULT_RCLK * 8, 546 PUC_PORT_4S, 0x18, 0, 8, 547 }, 548 549 { 0x1393, 0x1045, 0xffff, 0, 550 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 551 DEFAULT_RCLK * 8, 552 PUC_PORT_4S, 0x14, 0, -1, 553 .config_function = puc_config_moxa 554 }, 555 556 { 0x1393, 0x1120, 0xffff, 0, 557 "Moxa Technologies, CP-112UL", 558 DEFAULT_RCLK * 8, 559 PUC_PORT_2S, 0x18, 0, 8, 560 }, 561 562 { 0x1393, 0x1141, 0xffff, 0, 563 "Moxa Technologies, Industio CP-114", 564 DEFAULT_RCLK * 8, 565 PUC_PORT_4S, 0x18, 0, 8, 566 }, 567 568 { 0x1393, 0x1144, 0xffff, 0, 569 "Moxa Technologies, Smartio CP-114EL/PCIe", 570 DEFAULT_RCLK * 8, 571 PUC_PORT_4S, 0x14, 0, -1, 572 .config_function = puc_config_moxa 573 }, 574 575 { 0x1393, 0x1182, 0xffff, 0, 576 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 577 DEFAULT_RCLK * 8, 578 PUC_PORT_8S, 0x14, 0, -1, 579 .config_function = puc_config_moxa 580 }, 581 582 { 0x1393, 0x1680, 0xffff, 0, 583 "Moxa Technologies, C168H/PCI", 584 DEFAULT_RCLK * 8, 585 PUC_PORT_8S, 0x18, 0, 8, 586 }, 587 588 { 0x1393, 0x1681, 0xffff, 0, 589 "Moxa Technologies, C168U/PCI", 590 DEFAULT_RCLK * 8, 591 PUC_PORT_8S, 0x18, 0, 8, 592 }, 593 594 { 0x1393, 0x1682, 0xffff, 0, 595 "Moxa Technologies, CP-168EL/PCIe", 596 DEFAULT_RCLK * 8, 597 PUC_PORT_8S, 0x18, 0, 8, 598 }, 599 600 { 0x1393, 0x1683, 0xffff, 0, 601 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 602 DEFAULT_RCLK * 8, 603 PUC_PORT_8S, 0x14, 0, -1, 604 .config_function = puc_config_moxa 605 }, 606 607 { 0x13a8, 0x0152, 0xffff, 0, 608 "Exar XR17C/D152", 609 DEFAULT_RCLK * 8, 610 PUC_PORT_2S, 0x10, 0, -1, 611 .config_function = puc_config_exar 612 }, 613 614 { 0x13a8, 0x0154, 0xffff, 0, 615 "Exar XR17C154", 616 DEFAULT_RCLK * 8, 617 PUC_PORT_4S, 0x10, 0, -1, 618 .config_function = puc_config_exar 619 }, 620 621 { 0x13a8, 0x0158, 0xffff, 0, 622 "Exar XR17C158", 623 DEFAULT_RCLK * 8, 624 PUC_PORT_8S, 0x10, 0, -1, 625 .config_function = puc_config_exar 626 }, 627 628 { 0x13a8, 0x0258, 0xffff, 0, 629 "Exar XR17V258IV", 630 DEFAULT_RCLK * 8, 631 PUC_PORT_8S, 0x10, 0, -1, 632 }, 633 634 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 635 { 0x13a8, 0x0358, 0xffff, 0, 636 "Exar XR17V358", 637 125000000, 638 PUC_PORT_8S, 0x10, 0, -1, 639 .config_function = puc_config_exar_pcie 640 }, 641 642 { 0x13fe, 0x1600, 0x1602, 0x0002, 643 "Advantech PCI-1602", 644 DEFAULT_RCLK * 8, 645 PUC_PORT_2S, 0x10, 0, 8, 646 }, 647 648 { 0x1407, 0x0100, 0xffff, 0, 649 "Lava Computers Dual Serial", 650 DEFAULT_RCLK, 651 PUC_PORT_2S, 0x10, 4, 0, 652 }, 653 654 { 0x1407, 0x0101, 0xffff, 0, 655 "Lava Computers Quatro A", 656 DEFAULT_RCLK, 657 PUC_PORT_2S, 0x10, 4, 0, 658 }, 659 660 { 0x1407, 0x0102, 0xffff, 0, 661 "Lava Computers Quatro B", 662 DEFAULT_RCLK, 663 PUC_PORT_2S, 0x10, 4, 0, 664 }, 665 666 { 0x1407, 0x0120, 0xffff, 0, 667 "Lava Computers Quattro-PCI A", 668 DEFAULT_RCLK, 669 PUC_PORT_2S, 0x10, 4, 0, 670 }, 671 672 { 0x1407, 0x0121, 0xffff, 0, 673 "Lava Computers Quattro-PCI B", 674 DEFAULT_RCLK, 675 PUC_PORT_2S, 0x10, 4, 0, 676 }, 677 678 { 0x1407, 0x0180, 0xffff, 0, 679 "Lava Computers Octo A", 680 DEFAULT_RCLK, 681 PUC_PORT_4S, 0x10, 4, 0, 682 }, 683 684 { 0x1407, 0x0181, 0xffff, 0, 685 "Lava Computers Octo B", 686 DEFAULT_RCLK, 687 PUC_PORT_4S, 0x10, 4, 0, 688 }, 689 690 { 0x1409, 0x7268, 0xffff, 0, 691 "Sunix SUN1888", 692 0, 693 PUC_PORT_2P, 0x10, 0, 8, 694 }, 695 696 { 0x1409, 0x7168, 0xffff, 0, 697 NULL, 698 DEFAULT_RCLK * 8, 699 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 700 .config_function = puc_config_timedia 701 }, 702 703 /* 704 * Boards with an Oxford Semiconductor chip. 705 * 706 * Oxford Semiconductor provides documentation for their chip at: 707 * <URL:http://www.plxtech.com/products/uart/> 708 * 709 * As sold by Kouwell <URL:http://www.kouwell.com/>. 710 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 711 */ 712 { 713 0x1415, 0x9501, 0x10fc ,0xc070, 714 "I-O DATA RSA-PCI2/R", 715 DEFAULT_RCLK * 8, 716 PUC_PORT_2S, 0x10, 0, 8, 717 }, 718 719 { 0x1415, 0x9501, 0x131f, 0x2050, 720 "SIIG Cyber 4 PCI 16550", 721 DEFAULT_RCLK * 10, 722 PUC_PORT_4S, 0x10, 0, 8, 723 }, 724 725 { 0x1415, 0x9501, 0x131f, 0x2051, 726 "SIIG Cyber 4S PCI 16C650 (20x family)", 727 DEFAULT_RCLK * 10, 728 PUC_PORT_4S, 0x10, 0, 8, 729 }, 730 731 { 0x1415, 0x9501, 0x131f, 0x2052, 732 "SIIG Quartet Serial 850", 733 DEFAULT_RCLK * 10, 734 PUC_PORT_4S, 0x10, 0, 8, 735 }, 736 737 { 0x1415, 0x9501, 0x14db, 0x2150, 738 "Kuroutoshikou SERIAL4P-LPPCI2", 739 DEFAULT_RCLK * 10, 740 PUC_PORT_4S, 0x10, 0, 8, 741 }, 742 743 { 0x1415, 0x9501, 0xffff, 0, 744 "Oxford Semiconductor OX16PCI954 UARTs", 745 DEFAULT_RCLK, 746 PUC_PORT_4S, 0x10, 0, 8, 747 }, 748 749 { 0x1415, 0x950a, 0x131f, 0x2030, 750 "SIIG Cyber 2S PCIe", 751 DEFAULT_RCLK * 10, 752 PUC_PORT_2S, 0x10, 0, 8, 753 }, 754 755 { 0x1415, 0x950a, 0x131f, 0x2032, 756 "SIIG Cyber Serial Dual PCI 16C850", 757 DEFAULT_RCLK * 10, 758 PUC_PORT_4S, 0x10, 0, 8, 759 }, 760 761 { 0x1415, 0x950a, 0xffff, 0, 762 "Oxford Semiconductor OX16PCI954 UARTs", 763 DEFAULT_RCLK, 764 PUC_PORT_4S, 0x10, 0, 8, 765 }, 766 767 { 0x1415, 0x9511, 0xffff, 0, 768 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 769 DEFAULT_RCLK, 770 PUC_PORT_4S, 0x10, 0, 8, 771 }, 772 773 { 0x1415, 0x9521, 0xffff, 0, 774 "Oxford Semiconductor OX16PCI952 UARTs", 775 DEFAULT_RCLK, 776 PUC_PORT_2S, 0x10, 4, 0, 777 }, 778 779 { 0x1415, 0x9538, 0xffff, 0, 780 "Oxford Semiconductor OX16PCI958 UARTs", 781 DEFAULT_RCLK, 782 PUC_PORT_8S, 0x18, 0, 8, 783 }, 784 785 /* 786 * Perle boards use Oxford Semiconductor chips, but they store the 787 * Oxford Semiconductor device ID as a subvendor device ID and use 788 * their own device IDs. 789 */ 790 791 { 0x155f, 0x0331, 0xffff, 0, 792 "Perle Ultraport4 Express", 793 DEFAULT_RCLK * 8, 794 PUC_PORT_4S, 0x10, 0, 8, 795 }, 796 797 { 0x155f, 0xB012, 0xffff, 0, 798 "Perle Speed2 LE", 799 DEFAULT_RCLK * 8, 800 PUC_PORT_2S, 0x10, 0, 8, 801 }, 802 803 { 0x155f, 0xB022, 0xffff, 0, 804 "Perle Speed2 LE", 805 DEFAULT_RCLK * 8, 806 PUC_PORT_2S, 0x10, 0, 8, 807 }, 808 809 { 0x155f, 0xB004, 0xffff, 0, 810 "Perle Speed4 LE", 811 DEFAULT_RCLK * 8, 812 PUC_PORT_4S, 0x10, 0, 8, 813 }, 814 815 { 0x155f, 0xB008, 0xffff, 0, 816 "Perle Speed8 LE", 817 DEFAULT_RCLK * 8, 818 PUC_PORT_8S, 0x10, 0, 8, 819 }, 820 821 822 /* 823 * Oxford Semiconductor PCI Express Expresso family 824 * 825 * Found in many 'native' PCI Express serial boards such as: 826 * 827 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 828 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 829 * 830 * Lindy 51189 (4 port) 831 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 832 * 833 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 834 * <URL:http://www.startech.com> 835 */ 836 837 { 0x1415, 0xc138, 0xffff, 0, 838 "Oxford Semiconductor OXPCIe952 UARTs", 839 DEFAULT_RCLK * 0x22, 840 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 841 .config_function = puc_config_oxford_pcie 842 }, 843 844 { 0x1415, 0xc158, 0xffff, 0, 845 "Oxford Semiconductor OXPCIe952 UARTs", 846 DEFAULT_RCLK * 0x22, 847 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 848 .config_function = puc_config_oxford_pcie 849 }, 850 851 { 0x1415, 0xc15d, 0xffff, 0, 852 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 853 DEFAULT_RCLK * 0x22, 854 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 855 .config_function = puc_config_oxford_pcie 856 }, 857 858 { 0x1415, 0xc208, 0xffff, 0, 859 "Oxford Semiconductor OXPCIe954 UARTs", 860 DEFAULT_RCLK * 0x22, 861 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 862 .config_function = puc_config_oxford_pcie 863 }, 864 865 { 0x1415, 0xc20d, 0xffff, 0, 866 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 867 DEFAULT_RCLK * 0x22, 868 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 869 .config_function = puc_config_oxford_pcie 870 }, 871 872 { 0x1415, 0xc308, 0xffff, 0, 873 "Oxford Semiconductor OXPCIe958 UARTs", 874 DEFAULT_RCLK * 0x22, 875 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 876 .config_function = puc_config_oxford_pcie 877 }, 878 879 { 0x1415, 0xc30d, 0xffff, 0, 880 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 881 DEFAULT_RCLK * 0x22, 882 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 883 .config_function = puc_config_oxford_pcie 884 }, 885 886 { 0x14d2, 0x8010, 0xffff, 0, 887 "VScom PCI-100L", 888 DEFAULT_RCLK * 8, 889 PUC_PORT_1S, 0x14, 0, 0, 890 }, 891 892 { 0x14d2, 0x8020, 0xffff, 0, 893 "VScom PCI-200L", 894 DEFAULT_RCLK * 8, 895 PUC_PORT_2S, 0x14, 4, 0, 896 }, 897 898 { 0x14d2, 0x8028, 0xffff, 0, 899 "VScom 200Li", 900 DEFAULT_RCLK, 901 PUC_PORT_2S, 0x20, 0, 8, 902 }, 903 904 /* 905 * VScom (Titan?) PCI-800L. More modern variant of the 906 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 907 * two of them obviously implemented as macro cells in 908 * the ASIC. This causes the weird port access pattern 909 * below, where two of the IO port ranges each access 910 * one of the ASIC UARTs, and a block of IO addresses 911 * access the external UARTs. 912 */ 913 { 0x14d2, 0x8080, 0xffff, 0, 914 "Titan VScom PCI-800L", 915 DEFAULT_RCLK * 8, 916 PUC_PORT_8S, 0x14, -1, -1, 917 .config_function = puc_config_titan 918 }, 919 920 /* 921 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 922 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 923 * device ID 3 and PCI device 1 device ID 4. 924 */ 925 { 0x14d2, 0xa003, 0xffff, 0, 926 "Titan PCI-800H", 927 DEFAULT_RCLK * 8, 928 PUC_PORT_4S, 0x10, 0, 8, 929 }, 930 931 { 0x14d2, 0xa004, 0xffff, 0, 932 "Titan PCI-800H", 933 DEFAULT_RCLK * 8, 934 PUC_PORT_4S, 0x10, 0, 8, 935 }, 936 937 { 0x14d2, 0xa005, 0xffff, 0, 938 "Titan PCI-200H", 939 DEFAULT_RCLK * 8, 940 PUC_PORT_2S, 0x10, 0, 8, 941 }, 942 943 { 0x14d2, 0xe020, 0xffff, 0, 944 "Titan VScom PCI-200HV2", 945 DEFAULT_RCLK * 8, 946 PUC_PORT_2S, 0x10, 4, 0, 947 }, 948 949 { 0x14d2, 0xa007, 0xffff, 0, 950 "Titan VScom PCIex-800H", 951 DEFAULT_RCLK * 8, 952 PUC_PORT_4S, 0x10, 0, 8, 953 }, 954 955 { 0x14d2, 0xa008, 0xffff, 0, 956 "Titan VScom PCIex-800H", 957 DEFAULT_RCLK * 8, 958 PUC_PORT_4S, 0x10, 0, 8, 959 }, 960 961 { 0x14db, 0x2130, 0xffff, 0, 962 "Avlab Technology, PCI IO 2S", 963 DEFAULT_RCLK, 964 PUC_PORT_2S, 0x10, 4, 0, 965 }, 966 967 { 0x14db, 0x2150, 0xffff, 0, 968 "Avlab Low Profile PCI 4 Serial", 969 DEFAULT_RCLK, 970 PUC_PORT_4S, 0x10, 4, 0, 971 }, 972 973 { 0x14db, 0x2152, 0xffff, 0, 974 "Avlab Low Profile PCI 4 Serial", 975 DEFAULT_RCLK, 976 PUC_PORT_4S, 0x10, 4, 0, 977 }, 978 979 { 0x1592, 0x0781, 0xffff, 0, 980 "Syba Tech Ltd. PCI-4S2P-550-ECP", 981 DEFAULT_RCLK, 982 PUC_PORT_4S1P, 0x10, 0, -1, 983 .config_function = puc_config_syba 984 }, 985 986 { 0x1fd4, 0x1999, 0xffff, 0, 987 "Sunix SER5437A", 988 DEFAULT_RCLK * 8, 989 PUC_PORT_2S, 0x10, 0, 8, 990 }, 991 992 { 0x5372, 0x6873, 0xffff, 0, 993 "Sun 1040 PCI Quad Serial", 994 DEFAULT_RCLK, 995 PUC_PORT_4S, 0x10, 4, 0, 996 }, 997 998 { 0x6666, 0x0001, 0xffff, 0, 999 "Decision Computer Inc, PCCOM 4-port serial", 1000 DEFAULT_RCLK, 1001 PUC_PORT_4S, 0x1c, 0, 8, 1002 }, 1003 1004 { 0x6666, 0x0002, 0xffff, 0, 1005 "Decision Computer Inc, PCCOM 8-port serial", 1006 DEFAULT_RCLK, 1007 PUC_PORT_8S, 0x1c, 0, 8, 1008 }, 1009 1010 { 0x6666, 0x0004, 0xffff, 0, 1011 "PCCOM dual port RS232/422/485", 1012 DEFAULT_RCLK, 1013 PUC_PORT_2S, 0x1c, 0, 8, 1014 }, 1015 1016 { 0x9710, 0x9815, 0xffff, 0, 1017 "NetMos NM9815 Dual 1284 Printer port", 1018 0, 1019 PUC_PORT_2P, 0x10, 8, 0, 1020 }, 1021 1022 /* 1023 * This is more specific than the generic NM9835 entry that follows, and 1024 * is placed here to _prevent_ puc from claiming this single port card. 1025 * 1026 * uart(4) will claim this device. 1027 */ 1028 { 0x9710, 0x9835, 0x1000, 1, 1029 "NetMos NM9835 based 1-port serial", 1030 DEFAULT_RCLK, 1031 PUC_PORT_1S, 0x10, 4, 0, 1032 }, 1033 1034 { 0x9710, 0x9835, 0x1000, 2, 1035 "NetMos NM9835 based 2-port serial", 1036 DEFAULT_RCLK, 1037 PUC_PORT_2S, 0x10, 4, 0, 1038 }, 1039 1040 { 0x9710, 0x9835, 0xffff, 0, 1041 "NetMos NM9835 Dual UART and 1284 Printer port", 1042 DEFAULT_RCLK, 1043 PUC_PORT_2S1P, 0x10, 4, 0, 1044 }, 1045 1046 { 0x9710, 0x9845, 0x1000, 0x0006, 1047 "NetMos NM9845 6 Port UART", 1048 DEFAULT_RCLK, 1049 PUC_PORT_6S, 0x10, 4, 0, 1050 }, 1051 1052 { 0x9710, 0x9845, 0xffff, 0, 1053 "NetMos NM9845 Quad UART and 1284 Printer port", 1054 DEFAULT_RCLK, 1055 PUC_PORT_4S1P, 0x10, 4, 0, 1056 }, 1057 1058 { 0x9710, 0x9865, 0xa000, 0x3002, 1059 "NetMos NM9865 Dual UART", 1060 DEFAULT_RCLK, 1061 PUC_PORT_2S, 0x10, 4, 0, 1062 }, 1063 1064 { 0x9710, 0x9865, 0xa000, 0x3003, 1065 "NetMos NM9865 Triple UART", 1066 DEFAULT_RCLK, 1067 PUC_PORT_3S, 0x10, 4, 0, 1068 }, 1069 1070 { 0x9710, 0x9865, 0xa000, 0x3004, 1071 "NetMos NM9865 Quad UART", 1072 DEFAULT_RCLK, 1073 PUC_PORT_4S, 0x10, 4, 0, 1074 }, 1075 1076 { 0x9710, 0x9865, 0xa000, 0x3011, 1077 "NetMos NM9865 Single UART and 1284 Printer port", 1078 DEFAULT_RCLK, 1079 PUC_PORT_1S1P, 0x10, 4, 0, 1080 }, 1081 1082 { 0x9710, 0x9865, 0xa000, 0x3012, 1083 "NetMos NM9865 Dual UART and 1284 Printer port", 1084 DEFAULT_RCLK, 1085 PUC_PORT_2S1P, 0x10, 4, 0, 1086 }, 1087 1088 { 0x9710, 0x9865, 0xa000, 0x3020, 1089 "NetMos NM9865 Dual 1284 Printer port", 1090 DEFAULT_RCLK, 1091 PUC_PORT_2P, 0x10, 4, 0, 1092 }, 1093 1094 { 0xb00c, 0x021c, 0xffff, 0, 1095 "IC Book Labs Gunboat x4 Lite", 1096 DEFAULT_RCLK, 1097 PUC_PORT_4S, 0x10, 0, 8, 1098 .config_function = puc_config_icbook 1099 }, 1100 1101 { 0xb00c, 0x031c, 0xffff, 0, 1102 "IC Book Labs Gunboat x4 Pro", 1103 DEFAULT_RCLK, 1104 PUC_PORT_4S, 0x10, 0, 8, 1105 .config_function = puc_config_icbook 1106 }, 1107 1108 { 0xb00c, 0x041c, 0xffff, 0, 1109 "IC Book Labs Ironclad x8 Lite", 1110 DEFAULT_RCLK, 1111 PUC_PORT_8S, 0x10, 0, 8, 1112 .config_function = puc_config_icbook 1113 }, 1114 1115 { 0xb00c, 0x051c, 0xffff, 0, 1116 "IC Book Labs Ironclad x8 Pro", 1117 DEFAULT_RCLK, 1118 PUC_PORT_8S, 0x10, 0, 8, 1119 .config_function = puc_config_icbook 1120 }, 1121 1122 { 0xb00c, 0x081c, 0xffff, 0, 1123 "IC Book Labs Dreadnought x16 Pro", 1124 DEFAULT_RCLK * 8, 1125 PUC_PORT_16S, 0x10, 0, 8, 1126 .config_function = puc_config_icbook 1127 }, 1128 1129 { 0xb00c, 0x091c, 0xffff, 0, 1130 "IC Book Labs Dreadnought x16 Lite", 1131 DEFAULT_RCLK, 1132 PUC_PORT_16S, 0x10, 0, 8, 1133 .config_function = puc_config_icbook 1134 }, 1135 1136 { 0xb00c, 0x0a1c, 0xffff, 0, 1137 "IC Book Labs Gunboat x2 Low Profile", 1138 DEFAULT_RCLK, 1139 PUC_PORT_2S, 0x10, 0, 8, 1140 }, 1141 1142 { 0xb00c, 0x0b1c, 0xffff, 0, 1143 "IC Book Labs Gunboat x4 Low Profile", 1144 DEFAULT_RCLK, 1145 PUC_PORT_4S, 0x10, 0, 8, 1146 .config_function = puc_config_icbook 1147 }, 1148 1149 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1150 }; 1151 1152 static int 1153 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1154 intptr_t *res) 1155 { 1156 switch (cmd) { 1157 case PUC_CFG_GET_OFS: 1158 *res = 8 * (port & 1); 1159 return (0); 1160 case PUC_CFG_GET_RID: 1161 *res = 0x14 + (port >> 1) * 4; 1162 return (0); 1163 default: 1164 break; 1165 } 1166 return (ENXIO); 1167 } 1168 1169 static int 1170 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1171 intptr_t *res) 1172 { 1173 const struct puc_cfg *cfg = sc->sc_cfg; 1174 1175 if (cmd == PUC_CFG_GET_OFS) { 1176 if (cfg->subdevice == 0x1282) /* Everest SP */ 1177 port <<= 1; 1178 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1179 port = (port == 3) ? 4 : port; 1180 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1181 return (0); 1182 } 1183 return (ENXIO); 1184 } 1185 1186 static int 1187 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1188 intptr_t *res) 1189 { 1190 if (cmd == PUC_CFG_GET_OFS) { 1191 *res = port * 0x200; 1192 return (0); 1193 } 1194 return (ENXIO); 1195 } 1196 1197 static int 1198 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1199 intptr_t *res) 1200 { 1201 if (cmd == PUC_CFG_GET_OFS) { 1202 *res = port * 0x400; 1203 return (0); 1204 } 1205 return (ENXIO); 1206 } 1207 1208 static int 1209 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1210 intptr_t *res) 1211 { 1212 if (cmd == PUC_CFG_GET_ILR) { 1213 *res = PUC_ILR_DIGI; 1214 return (0); 1215 } 1216 return (ENXIO); 1217 } 1218 1219 static int 1220 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1221 intptr_t *res) 1222 { 1223 if (cmd == PUC_CFG_GET_OFS) { 1224 const struct puc_cfg *cfg = sc->sc_cfg; 1225 1226 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1227 port = 7; 1228 *res = port * 0x200; 1229 1230 return 0; 1231 } 1232 return (ENXIO); 1233 } 1234 1235 static int 1236 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1237 intptr_t *res) 1238 { 1239 const struct puc_cfg *cfg = sc->sc_cfg; 1240 struct puc_bar *bar; 1241 uint8_t v0, v1; 1242 1243 switch (cmd) { 1244 case PUC_CFG_SETUP: 1245 /* 1246 * Check if the scratchpad register is enabled or if the 1247 * interrupt status and options registers are active. 1248 */ 1249 bar = puc_get_bar(sc, cfg->rid); 1250 if (bar == NULL) 1251 return (ENXIO); 1252 /* Set DLAB in the LCR register of UART 0. */ 1253 bus_write_1(bar->b_res, 3, 0x80); 1254 /* Write 0 to the SPR register of UART 0. */ 1255 bus_write_1(bar->b_res, 7, 0); 1256 /* Read back the contents of the SPR register of UART 0. */ 1257 v0 = bus_read_1(bar->b_res, 7); 1258 /* Write a specific value to the SPR register of UART 0. */ 1259 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1260 /* Read back the contents of the SPR register of UART 0. */ 1261 v1 = bus_read_1(bar->b_res, 7); 1262 /* Clear DLAB in the LCR register of UART 0. */ 1263 bus_write_1(bar->b_res, 3, 0); 1264 /* Save the two values read-back from the SPR register. */ 1265 sc->sc_cfg_data = (v0 << 8) | v1; 1266 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1267 /* 1268 * The SPR register echoed the two values written 1269 * by us. This means that the SPAD jumper is set. 1270 */ 1271 device_printf(sc->sc_dev, "warning: extra features " 1272 "not usable -- SPAD compatibility enabled\n"); 1273 return (0); 1274 } 1275 if (v0 != 0) { 1276 /* 1277 * The first value doesn't match. This can only mean 1278 * that the SPAD jumper is not set and that a non- 1279 * standard fixed clock multiplier jumper is set. 1280 */ 1281 if (bootverbose) 1282 device_printf(sc->sc_dev, "fixed clock rate " 1283 "multiplier of %d\n", 1 << v0); 1284 if (v0 < -cfg->clock) 1285 device_printf(sc->sc_dev, "warning: " 1286 "suboptimal fixed clock rate multiplier " 1287 "setting\n"); 1288 return (0); 1289 } 1290 /* 1291 * The first value matched, but the second didn't. We know 1292 * that the SPAD jumper is not set. We also know that the 1293 * clock rate multiplier is software controlled *and* that 1294 * we just programmed it to the maximum allowed. 1295 */ 1296 if (bootverbose) 1297 device_printf(sc->sc_dev, "clock rate multiplier of " 1298 "%d selected\n", 1 << -cfg->clock); 1299 return (0); 1300 case PUC_CFG_GET_CLOCK: 1301 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1302 v1 = sc->sc_cfg_data & 0xff; 1303 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1304 /* 1305 * XXX With the SPAD jumper applied, there's no 1306 * easy way of knowing if there's also a clock 1307 * rate multiplier jumper installed. Let's hope 1308 * not... 1309 */ 1310 *res = DEFAULT_RCLK; 1311 } else if (v0 == 0) { 1312 /* 1313 * No clock rate multiplier jumper installed, 1314 * so we programmed the board with the maximum 1315 * multiplier allowed as given to us in the 1316 * clock field of the config record (negated). 1317 */ 1318 *res = DEFAULT_RCLK << -cfg->clock; 1319 } else 1320 *res = DEFAULT_RCLK << v0; 1321 return (0); 1322 case PUC_CFG_GET_ILR: 1323 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1324 v1 = sc->sc_cfg_data & 0xff; 1325 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1326 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1327 return (0); 1328 default: 1329 break; 1330 } 1331 return (ENXIO); 1332 } 1333 1334 static int 1335 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1336 intptr_t *res) 1337 { 1338 static int base[] = { 0x251, 0x3f0, 0 }; 1339 const struct puc_cfg *cfg = sc->sc_cfg; 1340 struct puc_bar *bar; 1341 int efir, idx, ofs; 1342 uint8_t v; 1343 1344 switch (cmd) { 1345 case PUC_CFG_SETUP: 1346 bar = puc_get_bar(sc, cfg->rid); 1347 if (bar == NULL) 1348 return (ENXIO); 1349 1350 /* configure both W83877TFs */ 1351 bus_write_1(bar->b_res, 0x250, 0x89); 1352 bus_write_1(bar->b_res, 0x3f0, 0x87); 1353 bus_write_1(bar->b_res, 0x3f0, 0x87); 1354 idx = 0; 1355 while (base[idx] != 0) { 1356 efir = base[idx]; 1357 bus_write_1(bar->b_res, efir, 0x09); 1358 v = bus_read_1(bar->b_res, efir + 1); 1359 if ((v & 0x0f) != 0x0c) 1360 return (ENXIO); 1361 bus_write_1(bar->b_res, efir, 0x16); 1362 v = bus_read_1(bar->b_res, efir + 1); 1363 bus_write_1(bar->b_res, efir, 0x16); 1364 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1365 bus_write_1(bar->b_res, efir, 0x16); 1366 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1367 ofs = base[idx] & 0x300; 1368 bus_write_1(bar->b_res, efir, 0x23); 1369 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1370 bus_write_1(bar->b_res, efir, 0x24); 1371 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1372 bus_write_1(bar->b_res, efir, 0x25); 1373 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1374 bus_write_1(bar->b_res, efir, 0x17); 1375 bus_write_1(bar->b_res, efir + 1, 0x03); 1376 bus_write_1(bar->b_res, efir, 0x28); 1377 bus_write_1(bar->b_res, efir + 1, 0x43); 1378 idx++; 1379 } 1380 bus_write_1(bar->b_res, 0x250, 0xaa); 1381 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1382 return (0); 1383 case PUC_CFG_GET_OFS: 1384 switch (port) { 1385 case 0: 1386 *res = 0x2f8; 1387 return (0); 1388 case 1: 1389 *res = 0x2e8; 1390 return (0); 1391 case 2: 1392 *res = 0x3f8; 1393 return (0); 1394 case 3: 1395 *res = 0x3e8; 1396 return (0); 1397 case 4: 1398 *res = 0x278; 1399 return (0); 1400 } 1401 break; 1402 default: 1403 break; 1404 } 1405 return (ENXIO); 1406 } 1407 1408 static int 1409 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1410 intptr_t *res) 1411 { 1412 const struct puc_cfg *cfg = sc->sc_cfg; 1413 1414 switch (cmd) { 1415 case PUC_CFG_GET_OFS: 1416 if (cfg->ports == PUC_PORT_8S) { 1417 *res = (port > 4) ? 8 * (port - 4) : 0; 1418 return (0); 1419 } 1420 break; 1421 case PUC_CFG_GET_RID: 1422 if (cfg->ports == PUC_PORT_8S) { 1423 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1424 return (0); 1425 } 1426 if (cfg->ports == PUC_PORT_2S1P) { 1427 switch (port) { 1428 case 0: *res = 0x10; return (0); 1429 case 1: *res = 0x14; return (0); 1430 case 2: *res = 0x1c; return (0); 1431 } 1432 } 1433 break; 1434 default: 1435 break; 1436 } 1437 return (ENXIO); 1438 } 1439 1440 static int 1441 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1442 intptr_t *res) 1443 { 1444 static const uint16_t dual[] = { 1445 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1446 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1447 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1448 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1449 0xD079, 0 1450 }; 1451 static const uint16_t quad[] = { 1452 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1453 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1454 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1455 0xB157, 0 1456 }; 1457 static const uint16_t octa[] = { 1458 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1459 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1460 }; 1461 static const struct { 1462 int ports; 1463 const uint16_t *ids; 1464 } subdevs[] = { 1465 { 2, dual }, 1466 { 4, quad }, 1467 { 8, octa }, 1468 { 0, NULL } 1469 }; 1470 static char desc[64]; 1471 int dev, id; 1472 uint16_t subdev; 1473 1474 switch (cmd) { 1475 case PUC_CFG_GET_CLOCK: 1476 if (port < 2) 1477 *res = DEFAULT_RCLK * 8; 1478 else 1479 *res = DEFAULT_RCLK; 1480 return (0); 1481 case PUC_CFG_GET_DESC: 1482 snprintf(desc, sizeof(desc), 1483 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1484 *res = (intptr_t)desc; 1485 return (0); 1486 case PUC_CFG_GET_NPORTS: 1487 subdev = pci_get_subdevice(sc->sc_dev); 1488 dev = 0; 1489 while (subdevs[dev].ports != 0) { 1490 id = 0; 1491 while (subdevs[dev].ids[id] != 0) { 1492 if (subdev == subdevs[dev].ids[id]) { 1493 sc->sc_cfg_data = subdevs[dev].ports; 1494 *res = sc->sc_cfg_data; 1495 return (0); 1496 } 1497 id++; 1498 } 1499 dev++; 1500 } 1501 return (ENXIO); 1502 case PUC_CFG_GET_OFS: 1503 *res = (port == 1 || port == 3) ? 8 : 0; 1504 return (0); 1505 case PUC_CFG_GET_RID: 1506 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1507 return (0); 1508 case PUC_CFG_GET_TYPE: 1509 *res = PUC_TYPE_SERIAL; 1510 return (0); 1511 default: 1512 break; 1513 } 1514 return (ENXIO); 1515 } 1516 1517 static int 1518 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1519 intptr_t *res) 1520 { 1521 const struct puc_cfg *cfg = sc->sc_cfg; 1522 int idx; 1523 struct puc_bar *bar; 1524 uint8_t value; 1525 1526 switch (cmd) { 1527 case PUC_CFG_SETUP: 1528 device_printf(sc->sc_dev, "%d UARTs detected\n", 1529 sc->sc_nports); 1530 1531 /* Set UARTs to enhanced mode */ 1532 bar = puc_get_bar(sc, cfg->rid); 1533 if (bar == NULL) 1534 return (ENXIO); 1535 for (idx = 0; idx < sc->sc_nports; idx++) { 1536 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1537 0x92); 1538 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1539 value | 0x10); 1540 } 1541 return (0); 1542 case PUC_CFG_GET_LEN: 1543 *res = 0x200; 1544 return (0); 1545 case PUC_CFG_GET_NPORTS: 1546 /* 1547 * Check if we are being called from puc_bfe_attach() 1548 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1549 * puc_get_bar(), so we return a value of 16. This has cosmetic 1550 * side-effects at worst; in PUC_CFG_GET_DESC, 1551 * (int)sc->sc_cfg_data will not contain the true number of 1552 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1553 * call for this device family anyway. 1554 * 1555 * The check is for initialisation of sc->sc_bar[idx], which is 1556 * only done in puc_bfe_attach(). 1557 */ 1558 idx = 0; 1559 do { 1560 if (sc->sc_bar[idx++].b_rid != -1) { 1561 sc->sc_cfg_data = 16; 1562 *res = sc->sc_cfg_data; 1563 return (0); 1564 } 1565 } while (idx < PUC_PCI_BARS); 1566 1567 bar = puc_get_bar(sc, cfg->rid); 1568 if (bar == NULL) 1569 return (ENXIO); 1570 1571 value = bus_read_1(bar->b_res, 0x04); 1572 if (value == 0) 1573 return (ENXIO); 1574 1575 sc->sc_cfg_data = value; 1576 *res = sc->sc_cfg_data; 1577 return (0); 1578 case PUC_CFG_GET_OFS: 1579 *res = 0x1000 + (port << 9); 1580 return (0); 1581 case PUC_CFG_GET_TYPE: 1582 *res = PUC_TYPE_SERIAL; 1583 return (0); 1584 default: 1585 break; 1586 } 1587 return (ENXIO); 1588 } 1589 1590 static int 1591 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1592 intptr_t *res) 1593 { 1594 switch (cmd) { 1595 case PUC_CFG_GET_OFS: 1596 *res = (port < 3) ? 0 : (port - 2) << 3; 1597 return (0); 1598 case PUC_CFG_GET_RID: 1599 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1600 return (0); 1601 default: 1602 break; 1603 } 1604 return (ENXIO); 1605 } 1606