1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_exar; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_moxa; 55 static puc_config_f puc_config_oxford_pcie; 56 static puc_config_f puc_config_quatech; 57 static puc_config_f puc_config_syba; 58 static puc_config_f puc_config_siig; 59 static puc_config_f puc_config_timedia; 60 static puc_config_f puc_config_titan; 61 62 const struct puc_cfg puc_pci_devices[] = { 63 64 { 0x0009, 0x7168, 0xffff, 0, 65 "Sunix SUN1889", 66 DEFAULT_RCLK * 8, 67 PUC_PORT_2S, 0x10, 0, 8, 68 }, 69 70 { 0x103c, 0x1048, 0x103c, 0x1049, 71 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 72 DEFAULT_RCLK, 73 PUC_PORT_3S, 0x10, 0, -1, 74 .config_function = puc_config_diva 75 }, 76 77 { 0x103c, 0x1048, 0x103c, 0x104a, 78 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 79 DEFAULT_RCLK, 80 PUC_PORT_2S, 0x10, 0, -1, 81 .config_function = puc_config_diva 82 }, 83 84 { 0x103c, 0x1048, 0x103c, 0x104b, 85 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 86 DEFAULT_RCLK, 87 PUC_PORT_4S, 0x10, 0, -1, 88 .config_function = puc_config_diva 89 }, 90 91 { 0x103c, 0x1048, 0x103c, 0x1223, 92 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 93 DEFAULT_RCLK, 94 PUC_PORT_3S, 0x10, 0, -1, 95 .config_function = puc_config_diva 96 }, 97 98 { 0x103c, 0x1048, 0x103c, 0x1226, 99 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 100 DEFAULT_RCLK, 101 PUC_PORT_3S, 0x10, 0, -1, 102 .config_function = puc_config_diva 103 }, 104 105 { 0x103c, 0x1048, 0x103c, 0x1282, 106 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 107 DEFAULT_RCLK, 108 PUC_PORT_3S, 0x10, 0, -1, 109 .config_function = puc_config_diva 110 }, 111 112 { 0x10b5, 0x1076, 0x10b5, 0x1076, 113 "VScom PCI-800", 114 DEFAULT_RCLK * 8, 115 PUC_PORT_8S, 0x18, 0, 8, 116 }, 117 118 { 0x10b5, 0x1077, 0x10b5, 0x1077, 119 "VScom PCI-400", 120 DEFAULT_RCLK * 8, 121 PUC_PORT_4S, 0x18, 0, 8, 122 }, 123 124 { 0x10b5, 0x1103, 0x10b5, 0x1103, 125 "VScom PCI-200", 126 DEFAULT_RCLK * 8, 127 PUC_PORT_2S, 0x18, 4, 0, 128 }, 129 130 /* 131 * Boca Research Turbo Serial 658 (8 serial port) card. 132 * Appears to be the same as Chase Research PLC PCI-FAST8 133 * and Perle PCI-FAST8 Multi-Port serial cards. 134 */ 135 { 0x10b5, 0x9050, 0x12e0, 0x0021, 136 "Boca Research Turbo Serial 658", 137 DEFAULT_RCLK * 4, 138 PUC_PORT_8S, 0x18, 0, 8, 139 }, 140 141 { 0x10b5, 0x9050, 0x12e0, 0x0031, 142 "Boca Research Turbo Serial 654", 143 DEFAULT_RCLK * 4, 144 PUC_PORT_4S, 0x18, 0, 8, 145 }, 146 147 /* 148 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 149 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 150 * into the subsystem fields, and claims that it's a 151 * network/misc (0x02/0x80) device. 152 */ 153 { 0x10b5, 0x9050, 0xd84d, 0x6808, 154 "Dolphin Peripherals 4035", 155 DEFAULT_RCLK, 156 PUC_PORT_2S, 0x18, 4, 0, 157 }, 158 159 /* 160 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 161 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 162 * into the subsystem fields, and claims that it's a 163 * network/misc (0x02/0x80) device. 164 */ 165 { 0x10b5, 0x9050, 0xd84d, 0x6810, 166 "Dolphin Peripherals 4014", 167 0, 168 PUC_PORT_2P, 0x20, 4, 0, 169 }, 170 171 { 0x10e8, 0x818e, 0xffff, 0, 172 "Applied Micro Circuits 8 Port UART", 173 DEFAULT_RCLK, 174 PUC_PORT_8S, 0x14, -1, -1, 175 .config_function = puc_config_amc 176 }, 177 178 { 0x11fe, 0x8010, 0xffff, 0, 179 "Comtrol RocketPort 550/8 RJ11 part A", 180 DEFAULT_RCLK * 4, 181 PUC_PORT_4S, 0x10, 0, 8, 182 }, 183 184 { 0x11fe, 0x8011, 0xffff, 0, 185 "Comtrol RocketPort 550/8 RJ11 part B", 186 DEFAULT_RCLK * 4, 187 PUC_PORT_4S, 0x10, 0, 8, 188 }, 189 190 { 0x11fe, 0x8012, 0xffff, 0, 191 "Comtrol RocketPort 550/8 Octa part A", 192 DEFAULT_RCLK * 4, 193 PUC_PORT_4S, 0x10, 0, 8, 194 }, 195 196 { 0x11fe, 0x8013, 0xffff, 0, 197 "Comtrol RocketPort 550/8 Octa part B", 198 DEFAULT_RCLK * 4, 199 PUC_PORT_4S, 0x10, 0, 8, 200 }, 201 202 { 0x11fe, 0x8014, 0xffff, 0, 203 "Comtrol RocketPort 550/4 RJ45", 204 DEFAULT_RCLK * 4, 205 PUC_PORT_4S, 0x10, 0, 8, 206 }, 207 208 { 0x11fe, 0x8015, 0xffff, 0, 209 "Comtrol RocketPort 550/Quad", 210 DEFAULT_RCLK * 4, 211 PUC_PORT_4S, 0x10, 0, 8, 212 }, 213 214 { 0x11fe, 0x8016, 0xffff, 0, 215 "Comtrol RocketPort 550/16 part A", 216 DEFAULT_RCLK * 4, 217 PUC_PORT_4S, 0x10, 0, 8, 218 }, 219 220 { 0x11fe, 0x8017, 0xffff, 0, 221 "Comtrol RocketPort 550/16 part B", 222 DEFAULT_RCLK * 4, 223 PUC_PORT_12S, 0x10, 0, 8, 224 }, 225 226 { 0x11fe, 0x8018, 0xffff, 0, 227 "Comtrol RocketPort 550/8 part A", 228 DEFAULT_RCLK * 4, 229 PUC_PORT_4S, 0x10, 0, 8, 230 }, 231 232 { 0x11fe, 0x8019, 0xffff, 0, 233 "Comtrol RocketPort 550/8 part B", 234 DEFAULT_RCLK * 4, 235 PUC_PORT_4S, 0x10, 0, 8, 236 }, 237 238 /* 239 * IBM SurePOS 300 Series (481033H) serial ports 240 * Details can be found on the IBM RSS websites 241 */ 242 243 { 0x1014, 0x0297, 0xffff, 0, 244 "IBM SurePOS 300 Series (481033H) serial ports", 245 DEFAULT_RCLK, 246 PUC_PORT_4S, 0x10, 4, 0 247 }, 248 249 /* 250 * SIIG Boards. 251 * 252 * SIIG provides documentation for their boards at: 253 * <URL:http://www.siig.com/downloads.asp> 254 */ 255 256 { 0x131f, 0x1010, 0xffff, 0, 257 "SIIG Cyber I/O PCI 16C550 (10x family)", 258 DEFAULT_RCLK, 259 PUC_PORT_1S1P, 0x18, 4, 0, 260 }, 261 262 { 0x131f, 0x1011, 0xffff, 0, 263 "SIIG Cyber I/O PCI 16C650 (10x family)", 264 DEFAULT_RCLK, 265 PUC_PORT_1S1P, 0x18, 4, 0, 266 }, 267 268 { 0x131f, 0x1012, 0xffff, 0, 269 "SIIG Cyber I/O PCI 16C850 (10x family)", 270 DEFAULT_RCLK, 271 PUC_PORT_1S1P, 0x18, 4, 0, 272 }, 273 274 { 0x131f, 0x1021, 0xffff, 0, 275 "SIIG Cyber Parallel Dual PCI (10x family)", 276 0, 277 PUC_PORT_2P, 0x18, 8, 0, 278 }, 279 280 { 0x131f, 0x1030, 0xffff, 0, 281 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 282 DEFAULT_RCLK, 283 PUC_PORT_2S, 0x18, 4, 0, 284 }, 285 286 { 0x131f, 0x1031, 0xffff, 0, 287 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 288 DEFAULT_RCLK, 289 PUC_PORT_2S, 0x18, 4, 0, 290 }, 291 292 { 0x131f, 0x1032, 0xffff, 0, 293 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 294 DEFAULT_RCLK, 295 PUC_PORT_2S, 0x18, 4, 0, 296 }, 297 298 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 299 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 300 DEFAULT_RCLK, 301 PUC_PORT_2S1P, 0x18, 4, 0, 302 }, 303 304 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 305 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 306 DEFAULT_RCLK, 307 PUC_PORT_2S1P, 0x18, 4, 0, 308 }, 309 310 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 311 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 312 DEFAULT_RCLK, 313 PUC_PORT_2S1P, 0x18, 4, 0, 314 }, 315 316 { 0x131f, 0x1050, 0xffff, 0, 317 "SIIG Cyber 4S PCI 16C550 (10x family)", 318 DEFAULT_RCLK, 319 PUC_PORT_4S, 0x18, 4, 0, 320 }, 321 322 { 0x131f, 0x1051, 0xffff, 0, 323 "SIIG Cyber 4S PCI 16C650 (10x family)", 324 DEFAULT_RCLK, 325 PUC_PORT_4S, 0x18, 4, 0, 326 }, 327 328 { 0x131f, 0x1052, 0xffff, 0, 329 "SIIG Cyber 4S PCI 16C850 (10x family)", 330 DEFAULT_RCLK, 331 PUC_PORT_4S, 0x18, 4, 0, 332 }, 333 334 { 0x131f, 0x2010, 0xffff, 0, 335 "SIIG Cyber I/O PCI 16C550 (20x family)", 336 DEFAULT_RCLK, 337 PUC_PORT_1S1P, 0x10, 4, 0, 338 }, 339 340 { 0x131f, 0x2011, 0xffff, 0, 341 "SIIG Cyber I/O PCI 16C650 (20x family)", 342 DEFAULT_RCLK, 343 PUC_PORT_1S1P, 0x10, 4, 0, 344 }, 345 346 { 0x131f, 0x2012, 0xffff, 0, 347 "SIIG Cyber I/O PCI 16C850 (20x family)", 348 DEFAULT_RCLK, 349 PUC_PORT_1S1P, 0x10, 4, 0, 350 }, 351 352 { 0x131f, 0x2021, 0xffff, 0, 353 "SIIG Cyber Parallel Dual PCI (20x family)", 354 0, 355 PUC_PORT_2P, 0x10, 8, 0, 356 }, 357 358 { 0x131f, 0x2030, 0xffff, 0, 359 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 360 DEFAULT_RCLK, 361 PUC_PORT_2S, 0x10, 4, 0, 362 }, 363 364 { 0x131f, 0x2031, 0xffff, 0, 365 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 366 DEFAULT_RCLK, 367 PUC_PORT_2S, 0x10, 4, 0, 368 }, 369 370 { 0x131f, 0x2032, 0xffff, 0, 371 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 372 DEFAULT_RCLK, 373 PUC_PORT_2S, 0x10, 4, 0, 374 }, 375 376 { 0x131f, 0x2040, 0xffff, 0, 377 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 378 DEFAULT_RCLK, 379 PUC_PORT_1S2P, 0x10, -1, 0, 380 .config_function = puc_config_siig 381 }, 382 383 { 0x131f, 0x2041, 0xffff, 0, 384 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 385 DEFAULT_RCLK, 386 PUC_PORT_1S2P, 0x10, -1, 0, 387 .config_function = puc_config_siig 388 }, 389 390 { 0x131f, 0x2042, 0xffff, 0, 391 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_1S2P, 0x10, -1, 0, 394 .config_function = puc_config_siig 395 }, 396 397 { 0x131f, 0x2050, 0xffff, 0, 398 "SIIG Cyber 4S PCI 16C550 (20x family)", 399 DEFAULT_RCLK, 400 PUC_PORT_4S, 0x10, 4, 0, 401 }, 402 403 { 0x131f, 0x2051, 0xffff, 0, 404 "SIIG Cyber 4S PCI 16C650 (20x family)", 405 DEFAULT_RCLK, 406 PUC_PORT_4S, 0x10, 4, 0, 407 }, 408 409 { 0x131f, 0x2052, 0xffff, 0, 410 "SIIG Cyber 4S PCI 16C850 (20x family)", 411 DEFAULT_RCLK, 412 PUC_PORT_4S, 0x10, 4, 0, 413 }, 414 415 { 0x131f, 0x2060, 0xffff, 0, 416 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 417 DEFAULT_RCLK, 418 PUC_PORT_2S1P, 0x10, 4, 0, 419 }, 420 421 { 0x131f, 0x2061, 0xffff, 0, 422 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 423 DEFAULT_RCLK, 424 PUC_PORT_2S1P, 0x10, 4, 0, 425 }, 426 427 { 0x131f, 0x2062, 0xffff, 0, 428 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 429 DEFAULT_RCLK, 430 PUC_PORT_2S1P, 0x10, 4, 0, 431 }, 432 433 { 0x131f, 0x2081, 0xffff, 0, 434 "SIIG PS8000 8S PCI 16C650 (20x family)", 435 DEFAULT_RCLK, 436 PUC_PORT_8S, 0x10, -1, -1, 437 .config_function = puc_config_siig 438 }, 439 440 { 0x135c, 0x0010, 0xffff, 0, 441 "Quatech QSC-100", 442 -3, /* max 8x clock rate */ 443 PUC_PORT_4S, 0x14, 0, 8, 444 .config_function = puc_config_quatech 445 }, 446 447 { 0x135c, 0x0020, 0xffff, 0, 448 "Quatech DSC-100", 449 -1, /* max 2x clock rate */ 450 PUC_PORT_2S, 0x14, 0, 8, 451 .config_function = puc_config_quatech 452 }, 453 454 { 0x135c, 0x0030, 0xffff, 0, 455 "Quatech DSC-200/300", 456 -1, /* max 2x clock rate */ 457 PUC_PORT_2S, 0x14, 0, 8, 458 .config_function = puc_config_quatech 459 }, 460 461 { 0x135c, 0x0040, 0xffff, 0, 462 "Quatech QSC-200/300", 463 -3, /* max 8x clock rate */ 464 PUC_PORT_4S, 0x14, 0, 8, 465 .config_function = puc_config_quatech 466 }, 467 468 { 0x135c, 0x0050, 0xffff, 0, 469 "Quatech ESC-100D", 470 -3, /* max 8x clock rate */ 471 PUC_PORT_8S, 0x14, 0, 8, 472 .config_function = puc_config_quatech 473 }, 474 475 { 0x135c, 0x0060, 0xffff, 0, 476 "Quatech ESC-100M", 477 -3, /* max 8x clock rate */ 478 PUC_PORT_8S, 0x14, 0, 8, 479 .config_function = puc_config_quatech 480 }, 481 482 { 0x135c, 0x0170, 0xffff, 0, 483 "Quatech QSCLP-100", 484 -1, /* max 2x clock rate */ 485 PUC_PORT_4S, 0x18, 0, 8, 486 .config_function = puc_config_quatech 487 }, 488 489 { 0x135c, 0x0180, 0xffff, 0, 490 "Quatech DSCLP-100", 491 -1, /* max 3x clock rate */ 492 PUC_PORT_2S, 0x18, 0, 8, 493 .config_function = puc_config_quatech 494 }, 495 496 { 0x135c, 0x01b0, 0xffff, 0, 497 "Quatech DSCLP-200/300", 498 -1, /* max 2x clock rate */ 499 PUC_PORT_2S, 0x18, 0, 8, 500 .config_function = puc_config_quatech 501 }, 502 503 { 0x135c, 0x01e0, 0xffff, 0, 504 "Quatech ESCLP-100", 505 -3, /* max 8x clock rate */ 506 PUC_PORT_8S, 0x10, 0, 8, 507 .config_function = puc_config_quatech 508 }, 509 510 { 0x1393, 0x1024, 0xffff, 0, 511 "Moxa Technologies, Smartio CP-102E/PCIe", 512 DEFAULT_RCLK * 8, 513 PUC_PORT_2S, 0x14, 0, -1, 514 .config_function = puc_config_moxa 515 }, 516 517 { 0x1393, 0x1025, 0xffff, 0, 518 "Moxa Technologies, Smartio CP-102EL/PCIe", 519 DEFAULT_RCLK * 8, 520 PUC_PORT_2S, 0x14, 0, -1, 521 .config_function = puc_config_moxa 522 }, 523 524 { 0x1393, 0x1040, 0xffff, 0, 525 "Moxa Technologies, Smartio C104H/PCI", 526 DEFAULT_RCLK * 8, 527 PUC_PORT_4S, 0x18, 0, 8, 528 }, 529 530 { 0x1393, 0x1041, 0xffff, 0, 531 "Moxa Technologies, Smartio CP-104UL/PCI", 532 DEFAULT_RCLK * 8, 533 PUC_PORT_4S, 0x18, 0, 8, 534 }, 535 536 { 0x1393, 0x1042, 0xffff, 0, 537 "Moxa Technologies, Smartio CP-104JU/PCI", 538 DEFAULT_RCLK * 8, 539 PUC_PORT_4S, 0x18, 0, 8, 540 }, 541 542 { 0x1393, 0x1043, 0xffff, 0, 543 "Moxa Technologies, Smartio CP-104EL/PCIe", 544 DEFAULT_RCLK * 8, 545 PUC_PORT_4S, 0x18, 0, 8, 546 }, 547 548 { 0x1393, 0x1045, 0xffff, 0, 549 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 550 DEFAULT_RCLK * 8, 551 PUC_PORT_4S, 0x14, 0, -1, 552 .config_function = puc_config_moxa 553 }, 554 555 { 0x1393, 0x1120, 0xffff, 0, 556 "Moxa Technologies, CP-112UL", 557 DEFAULT_RCLK * 8, 558 PUC_PORT_2S, 0x18, 0, 8, 559 }, 560 561 { 0x1393, 0x1141, 0xffff, 0, 562 "Moxa Technologies, Industio CP-114", 563 DEFAULT_RCLK * 8, 564 PUC_PORT_4S, 0x18, 0, 8, 565 }, 566 567 { 0x1393, 0x1144, 0xffff, 0, 568 "Moxa Technologies, Smartio CP-114EL/PCIe", 569 DEFAULT_RCLK * 8, 570 PUC_PORT_4S, 0x14, 0, -1, 571 .config_function = puc_config_moxa 572 }, 573 574 { 0x1393, 0x1182, 0xffff, 0, 575 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 576 DEFAULT_RCLK * 8, 577 PUC_PORT_8S, 0x14, 0, -1, 578 .config_function = puc_config_moxa 579 }, 580 581 { 0x1393, 0x1680, 0xffff, 0, 582 "Moxa Technologies, C168H/PCI", 583 DEFAULT_RCLK * 8, 584 PUC_PORT_8S, 0x18, 0, 8, 585 }, 586 587 { 0x1393, 0x1681, 0xffff, 0, 588 "Moxa Technologies, C168U/PCI", 589 DEFAULT_RCLK * 8, 590 PUC_PORT_8S, 0x18, 0, 8, 591 }, 592 593 { 0x1393, 0x1682, 0xffff, 0, 594 "Moxa Technologies, CP-168EL/PCIe", 595 DEFAULT_RCLK * 8, 596 PUC_PORT_8S, 0x18, 0, 8, 597 }, 598 599 { 0x1393, 0x1683, 0xffff, 0, 600 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 601 DEFAULT_RCLK * 8, 602 PUC_PORT_8S, 0x14, 0, -1, 603 .config_function = puc_config_moxa 604 }, 605 606 { 0x13a8, 0x0152, 0xffff, 0, 607 "Exar XR17C/D152", 608 DEFAULT_RCLK * 8, 609 PUC_PORT_2S, 0x10, 0, -1, 610 .config_function = puc_config_exar 611 }, 612 613 { 0x13a8, 0x0154, 0xffff, 0, 614 "Exar XR17C154", 615 DEFAULT_RCLK * 8, 616 PUC_PORT_4S, 0x10, 0, -1, 617 .config_function = puc_config_exar 618 }, 619 620 { 0x13a8, 0x0158, 0xffff, 0, 621 "Exar XR17C158", 622 DEFAULT_RCLK * 8, 623 PUC_PORT_8S, 0x10, 0, -1, 624 .config_function = puc_config_exar 625 }, 626 627 { 0x13a8, 0x0258, 0xffff, 0, 628 "Exar XR17V258IV", 629 DEFAULT_RCLK * 8, 630 PUC_PORT_8S, 0x10, 0, -1, 631 }, 632 633 { 0x13fe, 0x1600, 0x1602, 0x0002, 634 "Advantech PCI-1602", 635 DEFAULT_RCLK * 8, 636 PUC_PORT_2S, 0x10, 0, 8, 637 }, 638 639 { 0x1407, 0x0100, 0xffff, 0, 640 "Lava Computers Dual Serial", 641 DEFAULT_RCLK, 642 PUC_PORT_2S, 0x10, 4, 0, 643 }, 644 645 { 0x1407, 0x0101, 0xffff, 0, 646 "Lava Computers Quatro A", 647 DEFAULT_RCLK, 648 PUC_PORT_2S, 0x10, 4, 0, 649 }, 650 651 { 0x1407, 0x0102, 0xffff, 0, 652 "Lava Computers Quatro B", 653 DEFAULT_RCLK, 654 PUC_PORT_2S, 0x10, 4, 0, 655 }, 656 657 { 0x1407, 0x0120, 0xffff, 0, 658 "Lava Computers Quattro-PCI A", 659 DEFAULT_RCLK, 660 PUC_PORT_2S, 0x10, 4, 0, 661 }, 662 663 { 0x1407, 0x0121, 0xffff, 0, 664 "Lava Computers Quattro-PCI B", 665 DEFAULT_RCLK, 666 PUC_PORT_2S, 0x10, 4, 0, 667 }, 668 669 { 0x1407, 0x0180, 0xffff, 0, 670 "Lava Computers Octo A", 671 DEFAULT_RCLK, 672 PUC_PORT_4S, 0x10, 4, 0, 673 }, 674 675 { 0x1407, 0x0181, 0xffff, 0, 676 "Lava Computers Octo B", 677 DEFAULT_RCLK, 678 PUC_PORT_4S, 0x10, 4, 0, 679 }, 680 681 { 0x1409, 0x7268, 0xffff, 0, 682 "Sunix SUN1888", 683 0, 684 PUC_PORT_2P, 0x10, 0, 8, 685 }, 686 687 { 0x1409, 0x7168, 0xffff, 0, 688 NULL, 689 DEFAULT_RCLK * 8, 690 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 691 .config_function = puc_config_timedia 692 }, 693 694 /* 695 * Boards with an Oxford Semiconductor chip. 696 * 697 * Oxford Semiconductor provides documentation for their chip at: 698 * <URL:http://www.plxtech.com/products/uart/> 699 * 700 * As sold by Kouwell <URL:http://www.kouwell.com/>. 701 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 702 */ 703 { 704 0x1415, 0x9501, 0x10fc ,0xc070, 705 "I-O DATA RSA-PCI2/R", 706 DEFAULT_RCLK * 8, 707 PUC_PORT_2S, 0x10, 0, 8, 708 }, 709 710 { 0x1415, 0x9501, 0x131f, 0x2050, 711 "SIIG Cyber 4 PCI 16550", 712 DEFAULT_RCLK * 10, 713 PUC_PORT_4S, 0x10, 0, 8, 714 }, 715 716 { 0x1415, 0x9501, 0x131f, 0x2051, 717 "SIIG Cyber 4S PCI 16C650 (20x family)", 718 DEFAULT_RCLK * 10, 719 PUC_PORT_4S, 0x10, 0, 8, 720 }, 721 722 { 0x1415, 0x9501, 0x131f, 0x2052, 723 "SIIG Quartet Serial 850", 724 DEFAULT_RCLK * 10, 725 PUC_PORT_4S, 0x10, 0, 8, 726 }, 727 728 { 0x1415, 0x9501, 0x14db, 0x2150, 729 "Kuroutoshikou SERIAL4P-LPPCI2", 730 DEFAULT_RCLK * 10, 731 PUC_PORT_4S, 0x10, 0, 8, 732 }, 733 734 { 0x1415, 0x9501, 0xffff, 0, 735 "Oxford Semiconductor OX16PCI954 UARTs", 736 DEFAULT_RCLK, 737 PUC_PORT_4S, 0x10, 0, 8, 738 }, 739 740 { 0x1415, 0x950a, 0x131f, 0x2030, 741 "SIIG Cyber 2S PCIe", 742 DEFAULT_RCLK * 10, 743 PUC_PORT_2S, 0x10, 0, 8, 744 }, 745 746 { 0x1415, 0x950a, 0x131f, 0x2032, 747 "SIIG Cyber Serial Dual PCI 16C850", 748 DEFAULT_RCLK * 10, 749 PUC_PORT_4S, 0x10, 0, 8, 750 }, 751 752 { 0x1415, 0x950a, 0xffff, 0, 753 "Oxford Semiconductor OX16PCI954 UARTs", 754 DEFAULT_RCLK, 755 PUC_PORT_4S, 0x10, 0, 8, 756 }, 757 758 { 0x1415, 0x9511, 0xffff, 0, 759 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 760 DEFAULT_RCLK, 761 PUC_PORT_4S, 0x10, 0, 8, 762 }, 763 764 { 0x1415, 0x9521, 0xffff, 0, 765 "Oxford Semiconductor OX16PCI952 UARTs", 766 DEFAULT_RCLK, 767 PUC_PORT_2S, 0x10, 4, 0, 768 }, 769 770 { 0x1415, 0x9538, 0xffff, 0, 771 "Oxford Semiconductor OX16PCI958 UARTs", 772 DEFAULT_RCLK * 10, 773 PUC_PORT_8S, 0x18, 0, 8, 774 }, 775 776 /* 777 * Perle boards use Oxford Semiconductor chips, but they store the 778 * Oxford Semiconductor device ID as a subvendor device ID and use 779 * their own device IDs. 780 */ 781 782 { 0x155f, 0x0331, 0xffff, 0, 783 "Perle Ultraport4 Express", 784 DEFAULT_RCLK * 8, 785 PUC_PORT_4S, 0x10, 0, 8, 786 }, 787 788 { 0x155f, 0xB012, 0xffff, 0, 789 "Perle Speed2 LE", 790 DEFAULT_RCLK * 8, 791 PUC_PORT_2S, 0x10, 0, 8, 792 }, 793 794 { 0x155f, 0xB022, 0xffff, 0, 795 "Perle Speed2 LE", 796 DEFAULT_RCLK * 8, 797 PUC_PORT_2S, 0x10, 0, 8, 798 }, 799 800 { 0x155f, 0xB004, 0xffff, 0, 801 "Perle Speed4 LE", 802 DEFAULT_RCLK * 8, 803 PUC_PORT_4S, 0x10, 0, 8, 804 }, 805 806 { 0x155f, 0xB008, 0xffff, 0, 807 "Perle Speed8 LE", 808 DEFAULT_RCLK * 8, 809 PUC_PORT_8S, 0x10, 0, 8, 810 }, 811 812 813 /* 814 * Oxford Semiconductor PCI Express Expresso family 815 * 816 * Found in many 'native' PCI Express serial boards such as: 817 * 818 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 819 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 820 * 821 * Lindy 51189 (4 port) 822 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 823 * 824 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 825 * <URL:http://www.startech.com> 826 */ 827 828 { 0x1415, 0xc138, 0xffff, 0, 829 "Oxford Semiconductor OXPCIe952 UARTs", 830 DEFAULT_RCLK * 0x22, 831 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 832 .config_function = puc_config_oxford_pcie 833 }, 834 835 { 0x1415, 0xc158, 0xffff, 0, 836 "Oxford Semiconductor OXPCIe952 UARTs", 837 DEFAULT_RCLK * 0x22, 838 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 839 .config_function = puc_config_oxford_pcie 840 }, 841 842 { 0x1415, 0xc15d, 0xffff, 0, 843 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 844 DEFAULT_RCLK * 0x22, 845 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 846 .config_function = puc_config_oxford_pcie 847 }, 848 849 { 0x1415, 0xc208, 0xffff, 0, 850 "Oxford Semiconductor OXPCIe954 UARTs", 851 DEFAULT_RCLK * 0x22, 852 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 853 .config_function = puc_config_oxford_pcie 854 }, 855 856 { 0x1415, 0xc20d, 0xffff, 0, 857 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 858 DEFAULT_RCLK * 0x22, 859 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 860 .config_function = puc_config_oxford_pcie 861 }, 862 863 { 0x1415, 0xc308, 0xffff, 0, 864 "Oxford Semiconductor OXPCIe958 UARTs", 865 DEFAULT_RCLK * 0x22, 866 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 867 .config_function = puc_config_oxford_pcie 868 }, 869 870 { 0x1415, 0xc30d, 0xffff, 0, 871 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 872 DEFAULT_RCLK * 0x22, 873 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 874 .config_function = puc_config_oxford_pcie 875 }, 876 877 { 0x14d2, 0x8010, 0xffff, 0, 878 "VScom PCI-100L", 879 DEFAULT_RCLK * 8, 880 PUC_PORT_1S, 0x14, 0, 0, 881 }, 882 883 { 0x14d2, 0x8020, 0xffff, 0, 884 "VScom PCI-200L", 885 DEFAULT_RCLK * 8, 886 PUC_PORT_2S, 0x14, 4, 0, 887 }, 888 889 { 0x14d2, 0x8028, 0xffff, 0, 890 "VScom 200Li", 891 DEFAULT_RCLK, 892 PUC_PORT_2S, 0x20, 0, 8, 893 }, 894 895 /* 896 * VScom (Titan?) PCI-800L. More modern variant of the 897 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 898 * two of them obviously implemented as macro cells in 899 * the ASIC. This causes the weird port access pattern 900 * below, where two of the IO port ranges each access 901 * one of the ASIC UARTs, and a block of IO addresses 902 * access the external UARTs. 903 */ 904 { 0x14d2, 0x8080, 0xffff, 0, 905 "Titan VScom PCI-800L", 906 DEFAULT_RCLK * 8, 907 PUC_PORT_8S, 0x14, -1, -1, 908 .config_function = puc_config_titan 909 }, 910 911 /* 912 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 913 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 914 * device ID 3 and PCI device 1 device ID 4. 915 */ 916 { 0x14d2, 0xa003, 0xffff, 0, 917 "Titan PCI-800H", 918 DEFAULT_RCLK * 8, 919 PUC_PORT_4S, 0x10, 0, 8, 920 }, 921 { 0x14d2, 0xa004, 0xffff, 0, 922 "Titan PCI-800H", 923 DEFAULT_RCLK * 8, 924 PUC_PORT_4S, 0x10, 0, 8, 925 }, 926 927 { 0x14d2, 0xa005, 0xffff, 0, 928 "Titan PCI-200H", 929 DEFAULT_RCLK * 8, 930 PUC_PORT_2S, 0x10, 0, 8, 931 }, 932 933 { 0x14d2, 0xe020, 0xffff, 0, 934 "Titan VScom PCI-200HV2", 935 DEFAULT_RCLK * 8, 936 PUC_PORT_2S, 0x10, 4, 0, 937 }, 938 939 { 0x14d2, 0xa007, 0xffff, 0, 940 "Titan VScom PCIex-800H", 941 DEFAULT_RCLK * 8, 942 PUC_PORT_4S, 0x10, 0, 8, 943 }, 944 945 { 0x14d2, 0xa008, 0xffff, 0, 946 "Titan VScom PCIex-800H", 947 DEFAULT_RCLK * 8, 948 PUC_PORT_4S, 0x10, 0, 8, 949 }, 950 951 { 0x14db, 0x2130, 0xffff, 0, 952 "Avlab Technology, PCI IO 2S", 953 DEFAULT_RCLK, 954 PUC_PORT_2S, 0x10, 4, 0, 955 }, 956 957 { 0x14db, 0x2150, 0xffff, 0, 958 "Avlab Low Profile PCI 4 Serial", 959 DEFAULT_RCLK, 960 PUC_PORT_4S, 0x10, 4, 0, 961 }, 962 963 { 0x14db, 0x2152, 0xffff, 0, 964 "Avlab Low Profile PCI 4 Serial", 965 DEFAULT_RCLK, 966 PUC_PORT_4S, 0x10, 4, 0, 967 }, 968 969 { 0x1592, 0x0781, 0xffff, 0, 970 "Syba Tech Ltd. PCI-4S2P-550-ECP", 971 DEFAULT_RCLK, 972 PUC_PORT_4S1P, 0x10, 0, -1, 973 .config_function = puc_config_syba 974 }, 975 976 { 0x1fd4, 0x1999, 0xffff, 0, 977 "Sunix SER5437A", 978 DEFAULT_RCLK * 8, 979 PUC_PORT_2S, 0x10, 0, 8, 980 }, 981 982 { 0x5372, 0x6873, 0xffff, 0, 983 "Sun 1040 PCI Quad Serial", 984 DEFAULT_RCLK, 985 PUC_PORT_4S, 0x10, 4, 0, 986 }, 987 988 { 0x6666, 0x0001, 0xffff, 0, 989 "Decision Computer Inc, PCCOM 4-port serial", 990 DEFAULT_RCLK, 991 PUC_PORT_4S, 0x1c, 0, 8, 992 }, 993 994 { 0x6666, 0x0002, 0xffff, 0, 995 "Decision Computer Inc, PCCOM 8-port serial", 996 DEFAULT_RCLK, 997 PUC_PORT_8S, 0x1c, 0, 8, 998 }, 999 1000 { 0x6666, 0x0004, 0xffff, 0, 1001 "PCCOM dual port RS232/422/485", 1002 DEFAULT_RCLK, 1003 PUC_PORT_2S, 0x1c, 0, 8, 1004 }, 1005 1006 { 0x9710, 0x9815, 0xffff, 0, 1007 "NetMos NM9815 Dual 1284 Printer port", 1008 0, 1009 PUC_PORT_2P, 0x10, 8, 0, 1010 }, 1011 1012 /* 1013 * This is more specific than the generic NM9835 entry that follows, and 1014 * is placed here to _prevent_ puc from claiming this single port card. 1015 * 1016 * uart(4) will claim this device. 1017 */ 1018 { 0x9710, 0x9835, 0x1000, 1, 1019 "NetMos NM9835 based 1-port serial", 1020 DEFAULT_RCLK, 1021 PUC_PORT_1S, 0x10, 4, 0, 1022 }, 1023 1024 { 0x9710, 0x9835, 0x1000, 2, 1025 "NetMos NM9835 based 2-port serial", 1026 DEFAULT_RCLK, 1027 PUC_PORT_2S, 0x10, 4, 0, 1028 }, 1029 1030 { 0x9710, 0x9835, 0xffff, 0, 1031 "NetMos NM9835 Dual UART and 1284 Printer port", 1032 DEFAULT_RCLK, 1033 PUC_PORT_2S1P, 0x10, 4, 0, 1034 }, 1035 1036 { 0x9710, 0x9845, 0x1000, 0x0006, 1037 "NetMos NM9845 6 Port UART", 1038 DEFAULT_RCLK, 1039 PUC_PORT_6S, 0x10, 4, 0, 1040 }, 1041 1042 { 0x9710, 0x9845, 0xffff, 0, 1043 "NetMos NM9845 Quad UART and 1284 Printer port", 1044 DEFAULT_RCLK, 1045 PUC_PORT_4S1P, 0x10, 4, 0, 1046 }, 1047 1048 { 0x9710, 0x9865, 0xa000, 0x3002, 1049 "NetMos NM9865 Dual UART", 1050 DEFAULT_RCLK, 1051 PUC_PORT_2S, 0x10, 4, 0, 1052 }, 1053 1054 { 0x9710, 0x9865, 0xa000, 0x3003, 1055 "NetMos NM9865 Triple UART", 1056 DEFAULT_RCLK, 1057 PUC_PORT_3S, 0x10, 4, 0, 1058 }, 1059 1060 { 0x9710, 0x9865, 0xa000, 0x3004, 1061 "NetMos NM9865 Quad UART", 1062 DEFAULT_RCLK, 1063 PUC_PORT_4S, 0x10, 4, 0,0 1064 }, 1065 1066 { 0x9710, 0x9865, 0xa000, 0x3011, 1067 "NetMos NM9865 Single UART and 1284 Printer port", 1068 DEFAULT_RCLK, 1069 PUC_PORT_1S1P, 0x10, 4, 0, 1070 }, 1071 1072 { 0x9710, 0x9865, 0xa000, 0x3012, 1073 "NetMos NM9865 Dual UART and 1284 Printer port", 1074 DEFAULT_RCLK, 1075 PUC_PORT_2S1P, 0x10, 4, 0, 1076 }, 1077 1078 { 0x9710, 0x9865, 0xa000, 0x3020, 1079 "NetMos NM9865 Dual 1284 Printer port", 1080 DEFAULT_RCLK, 1081 PUC_PORT_2P, 0x10, 4, 0, 1082 }, 1083 1084 { 0xb00c, 0x021c, 0xffff, 0, 1085 "IC Book Labs Gunboat x4 Lite", 1086 DEFAULT_RCLK, 1087 PUC_PORT_4S, 0x10, 0, 8, 1088 .config_function = puc_config_icbook 1089 }, 1090 1091 { 0xb00c, 0x031c, 0xffff, 0, 1092 "IC Book Labs Gunboat x4 Pro", 1093 DEFAULT_RCLK, 1094 PUC_PORT_4S, 0x10, 0, 8, 1095 .config_function = puc_config_icbook 1096 }, 1097 1098 { 0xb00c, 0x041c, 0xffff, 0, 1099 "IC Book Labs Ironclad x8 Lite", 1100 DEFAULT_RCLK, 1101 PUC_PORT_8S, 0x10, 0, 8, 1102 .config_function = puc_config_icbook 1103 }, 1104 1105 { 0xb00c, 0x051c, 0xffff, 0, 1106 "IC Book Labs Ironclad x8 Pro", 1107 DEFAULT_RCLK, 1108 PUC_PORT_8S, 0x10, 0, 8, 1109 .config_function = puc_config_icbook 1110 }, 1111 1112 { 0xb00c, 0x081c, 0xffff, 0, 1113 "IC Book Labs Dreadnought x16 Pro", 1114 DEFAULT_RCLK * 8, 1115 PUC_PORT_16S, 0x10, 0, 8, 1116 .config_function = puc_config_icbook 1117 }, 1118 1119 { 0xb00c, 0x091c, 0xffff, 0, 1120 "IC Book Labs Dreadnought x16 Lite", 1121 DEFAULT_RCLK, 1122 PUC_PORT_16S, 0x10, 0, 8, 1123 .config_function = puc_config_icbook 1124 }, 1125 1126 { 0xb00c, 0x0a1c, 0xffff, 0, 1127 "IC Book Labs Gunboat x2 Low Profile", 1128 DEFAULT_RCLK, 1129 PUC_PORT_2S, 0x10, 0, 8, 1130 }, 1131 1132 { 0xb00c, 0x0b1c, 0xffff, 0, 1133 "IC Book Labs Gunboat x4 Low Profile", 1134 DEFAULT_RCLK, 1135 PUC_PORT_4S, 0x10, 0, 8, 1136 .config_function = puc_config_icbook 1137 }, 1138 1139 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1140 }; 1141 1142 static int 1143 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1144 intptr_t *res) 1145 { 1146 switch (cmd) { 1147 case PUC_CFG_GET_OFS: 1148 *res = 8 * (port & 1); 1149 return (0); 1150 case PUC_CFG_GET_RID: 1151 *res = 0x14 + (port >> 1) * 4; 1152 return (0); 1153 default: 1154 break; 1155 } 1156 return (ENXIO); 1157 } 1158 1159 static int 1160 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1161 intptr_t *res) 1162 { 1163 const struct puc_cfg *cfg = sc->sc_cfg; 1164 1165 if (cmd == PUC_CFG_GET_OFS) { 1166 if (cfg->subdevice == 0x1282) /* Everest SP */ 1167 port <<= 1; 1168 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1169 port = (port == 3) ? 4 : port; 1170 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1171 return (0); 1172 } 1173 return (ENXIO); 1174 } 1175 1176 static int 1177 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1178 intptr_t *res) 1179 { 1180 if (cmd == PUC_CFG_GET_OFS) { 1181 *res = port * 0x200; 1182 return (0); 1183 } 1184 return (ENXIO); 1185 } 1186 1187 static int 1188 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1189 intptr_t *res) 1190 { 1191 if (cmd == PUC_CFG_GET_ILR) { 1192 *res = PUC_ILR_DIGI; 1193 return (0); 1194 } 1195 return (ENXIO); 1196 } 1197 1198 static int 1199 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1200 intptr_t *res) 1201 { 1202 if (cmd == PUC_CFG_GET_OFS) { 1203 const struct puc_cfg *cfg = sc->sc_cfg; 1204 1205 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1206 port = 7; 1207 *res = port * 0x200; 1208 1209 return 0; 1210 } 1211 return (ENXIO); 1212 } 1213 1214 static int 1215 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1216 intptr_t *res) 1217 { 1218 const struct puc_cfg *cfg = sc->sc_cfg; 1219 struct puc_bar *bar; 1220 uint8_t v0, v1; 1221 1222 switch (cmd) { 1223 case PUC_CFG_SETUP: 1224 /* 1225 * Check if the scratchpad register is enabled or if the 1226 * interrupt status and options registers are active. 1227 */ 1228 bar = puc_get_bar(sc, cfg->rid); 1229 if (bar == NULL) 1230 return (ENXIO); 1231 /* Set DLAB in the LCR register of UART 0. */ 1232 bus_write_1(bar->b_res, 3, 0x80); 1233 /* Write 0 to the SPR register of UART 0. */ 1234 bus_write_1(bar->b_res, 7, 0); 1235 /* Read back the contents of the SPR register of UART 0. */ 1236 v0 = bus_read_1(bar->b_res, 7); 1237 /* Write a specific value to the SPR register of UART 0. */ 1238 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1239 /* Read back the contents of the SPR register of UART 0. */ 1240 v1 = bus_read_1(bar->b_res, 7); 1241 /* Clear DLAB in the LCR register of UART 0. */ 1242 bus_write_1(bar->b_res, 3, 0); 1243 /* Save the two values read-back from the SPR register. */ 1244 sc->sc_cfg_data = (v0 << 8) | v1; 1245 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1246 /* 1247 * The SPR register echoed the two values written 1248 * by us. This means that the SPAD jumper is set. 1249 */ 1250 device_printf(sc->sc_dev, "warning: extra features " 1251 "not usable -- SPAD compatibility enabled\n"); 1252 return (0); 1253 } 1254 if (v0 != 0) { 1255 /* 1256 * The first value doesn't match. This can only mean 1257 * that the SPAD jumper is not set and that a non- 1258 * standard fixed clock multiplier jumper is set. 1259 */ 1260 if (bootverbose) 1261 device_printf(sc->sc_dev, "fixed clock rate " 1262 "multiplier of %d\n", 1 << v0); 1263 if (v0 < -cfg->clock) 1264 device_printf(sc->sc_dev, "warning: " 1265 "suboptimal fixed clock rate multiplier " 1266 "setting\n"); 1267 return (0); 1268 } 1269 /* 1270 * The first value matched, but the second didn't. We know 1271 * that the SPAD jumper is not set. We also know that the 1272 * clock rate multiplier is software controlled *and* that 1273 * we just programmed it to the maximum allowed. 1274 */ 1275 if (bootverbose) 1276 device_printf(sc->sc_dev, "clock rate multiplier of " 1277 "%d selected\n", 1 << -cfg->clock); 1278 return (0); 1279 case PUC_CFG_GET_CLOCK: 1280 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1281 v1 = sc->sc_cfg_data & 0xff; 1282 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1283 /* 1284 * XXX With the SPAD jumper applied, there's no 1285 * easy way of knowing if there's also a clock 1286 * rate multiplier jumper installed. Let's hope 1287 * not... 1288 */ 1289 *res = DEFAULT_RCLK; 1290 } else if (v0 == 0) { 1291 /* 1292 * No clock rate multiplier jumper installed, 1293 * so we programmed the board with the maximum 1294 * multiplier allowed as given to us in the 1295 * clock field of the config record (negated). 1296 */ 1297 *res = DEFAULT_RCLK << -cfg->clock; 1298 } else 1299 *res = DEFAULT_RCLK << v0; 1300 return (0); 1301 case PUC_CFG_GET_ILR: 1302 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1303 v1 = sc->sc_cfg_data & 0xff; 1304 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1305 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1306 return (0); 1307 default: 1308 break; 1309 } 1310 return (ENXIO); 1311 } 1312 1313 static int 1314 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1315 intptr_t *res) 1316 { 1317 static int base[] = { 0x251, 0x3f0, 0 }; 1318 const struct puc_cfg *cfg = sc->sc_cfg; 1319 struct puc_bar *bar; 1320 int efir, idx, ofs; 1321 uint8_t v; 1322 1323 switch (cmd) { 1324 case PUC_CFG_SETUP: 1325 bar = puc_get_bar(sc, cfg->rid); 1326 if (bar == NULL) 1327 return (ENXIO); 1328 1329 /* configure both W83877TFs */ 1330 bus_write_1(bar->b_res, 0x250, 0x89); 1331 bus_write_1(bar->b_res, 0x3f0, 0x87); 1332 bus_write_1(bar->b_res, 0x3f0, 0x87); 1333 idx = 0; 1334 while (base[idx] != 0) { 1335 efir = base[idx]; 1336 bus_write_1(bar->b_res, efir, 0x09); 1337 v = bus_read_1(bar->b_res, efir + 1); 1338 if ((v & 0x0f) != 0x0c) 1339 return (ENXIO); 1340 bus_write_1(bar->b_res, efir, 0x16); 1341 v = bus_read_1(bar->b_res, efir + 1); 1342 bus_write_1(bar->b_res, efir, 0x16); 1343 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1344 bus_write_1(bar->b_res, efir, 0x16); 1345 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1346 ofs = base[idx] & 0x300; 1347 bus_write_1(bar->b_res, efir, 0x23); 1348 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1349 bus_write_1(bar->b_res, efir, 0x24); 1350 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1351 bus_write_1(bar->b_res, efir, 0x25); 1352 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1353 bus_write_1(bar->b_res, efir, 0x17); 1354 bus_write_1(bar->b_res, efir + 1, 0x03); 1355 bus_write_1(bar->b_res, efir, 0x28); 1356 bus_write_1(bar->b_res, efir + 1, 0x43); 1357 idx++; 1358 } 1359 bus_write_1(bar->b_res, 0x250, 0xaa); 1360 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1361 return (0); 1362 case PUC_CFG_GET_OFS: 1363 switch (port) { 1364 case 0: 1365 *res = 0x2f8; 1366 return (0); 1367 case 1: 1368 *res = 0x2e8; 1369 return (0); 1370 case 2: 1371 *res = 0x3f8; 1372 return (0); 1373 case 3: 1374 *res = 0x3e8; 1375 return (0); 1376 case 4: 1377 *res = 0x278; 1378 return (0); 1379 } 1380 break; 1381 default: 1382 break; 1383 } 1384 return (ENXIO); 1385 } 1386 1387 static int 1388 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1389 intptr_t *res) 1390 { 1391 const struct puc_cfg *cfg = sc->sc_cfg; 1392 1393 switch (cmd) { 1394 case PUC_CFG_GET_OFS: 1395 if (cfg->ports == PUC_PORT_8S) { 1396 *res = (port > 4) ? 8 * (port - 4) : 0; 1397 return (0); 1398 } 1399 break; 1400 case PUC_CFG_GET_RID: 1401 if (cfg->ports == PUC_PORT_8S) { 1402 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1403 return (0); 1404 } 1405 if (cfg->ports == PUC_PORT_2S1P) { 1406 switch (port) { 1407 case 0: *res = 0x10; return (0); 1408 case 1: *res = 0x14; return (0); 1409 case 2: *res = 0x1c; return (0); 1410 } 1411 } 1412 break; 1413 default: 1414 break; 1415 } 1416 return (ENXIO); 1417 } 1418 1419 static int 1420 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1421 intptr_t *res) 1422 { 1423 static uint16_t dual[] = { 1424 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1425 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1426 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1427 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1428 0xD079, 0 1429 }; 1430 static uint16_t quad[] = { 1431 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1432 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1433 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1434 0xB157, 0 1435 }; 1436 static uint16_t octa[] = { 1437 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1438 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1439 }; 1440 static struct { 1441 int ports; 1442 uint16_t *ids; 1443 } subdevs[] = { 1444 { 2, dual }, 1445 { 4, quad }, 1446 { 8, octa }, 1447 { 0, NULL } 1448 }; 1449 static char desc[64]; 1450 int dev, id; 1451 uint16_t subdev; 1452 1453 switch (cmd) { 1454 case PUC_CFG_GET_CLOCK: 1455 if (port < 2) 1456 *res = DEFAULT_RCLK * 8; 1457 else 1458 *res = DEFAULT_RCLK; 1459 return (0); 1460 case PUC_CFG_GET_DESC: 1461 snprintf(desc, sizeof(desc), 1462 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1463 *res = (intptr_t)desc; 1464 return (0); 1465 case PUC_CFG_GET_NPORTS: 1466 subdev = pci_get_subdevice(sc->sc_dev); 1467 dev = 0; 1468 while (subdevs[dev].ports != 0) { 1469 id = 0; 1470 while (subdevs[dev].ids[id] != 0) { 1471 if (subdev == subdevs[dev].ids[id]) { 1472 sc->sc_cfg_data = subdevs[dev].ports; 1473 *res = sc->sc_cfg_data; 1474 return (0); 1475 } 1476 id++; 1477 } 1478 dev++; 1479 } 1480 return (ENXIO); 1481 case PUC_CFG_GET_OFS: 1482 *res = (port == 1 || port == 3) ? 8 : 0; 1483 return (0); 1484 case PUC_CFG_GET_RID: 1485 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1486 return (0); 1487 case PUC_CFG_GET_TYPE: 1488 *res = PUC_TYPE_SERIAL; 1489 return (0); 1490 default: 1491 break; 1492 } 1493 return (ENXIO); 1494 } 1495 1496 static int 1497 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1498 intptr_t *res) 1499 { 1500 const struct puc_cfg *cfg = sc->sc_cfg; 1501 int idx; 1502 struct puc_bar *bar; 1503 uint8_t value; 1504 1505 switch (cmd) { 1506 case PUC_CFG_SETUP: 1507 device_printf(sc->sc_dev, "%d UARTs detected\n", 1508 sc->sc_nports); 1509 1510 /* Set UARTs to enhanced mode */ 1511 bar = puc_get_bar(sc, cfg->rid); 1512 if (bar == NULL) 1513 return (ENXIO); 1514 for (idx = 0; idx < sc->sc_nports; idx++) { 1515 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1516 0x92); 1517 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1518 value | 0x10); 1519 } 1520 return (0); 1521 case PUC_CFG_GET_LEN: 1522 *res = 0x200; 1523 return (0); 1524 case PUC_CFG_GET_NPORTS: 1525 /* 1526 * Check if we are being called from puc_bfe_attach() 1527 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1528 * puc_get_bar(), so we return a value of 16. This has cosmetic 1529 * side-effects at worst; in PUC_CFG_GET_DESC, 1530 * (int)sc->sc_cfg_data will not contain the true number of 1531 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1532 * call for this device family anyway. 1533 * 1534 * The check is for initialisation of sc->sc_bar[idx], which is 1535 * only done in puc_bfe_attach(). 1536 */ 1537 idx = 0; 1538 do { 1539 if (sc->sc_bar[idx++].b_rid != -1) { 1540 sc->sc_cfg_data = 16; 1541 *res = sc->sc_cfg_data; 1542 return (0); 1543 } 1544 } while (idx < PUC_PCI_BARS); 1545 1546 bar = puc_get_bar(sc, cfg->rid); 1547 if (bar == NULL) 1548 return (ENXIO); 1549 1550 value = bus_read_1(bar->b_res, 0x04); 1551 if (value == 0) 1552 return (ENXIO); 1553 1554 sc->sc_cfg_data = value; 1555 *res = sc->sc_cfg_data; 1556 return (0); 1557 case PUC_CFG_GET_OFS: 1558 *res = 0x1000 + (port << 9); 1559 return (0); 1560 case PUC_CFG_GET_TYPE: 1561 *res = PUC_TYPE_SERIAL; 1562 return (0); 1563 default: 1564 break; 1565 } 1566 return (ENXIO); 1567 } 1568 1569 static int 1570 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1571 intptr_t *res) 1572 { 1573 switch (cmd) { 1574 case PUC_CFG_GET_OFS: 1575 *res = (port < 3) ? 0 : (port - 2) << 3; 1576 return (0); 1577 case PUC_CFG_GET_RID: 1578 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1579 return (0); 1580 default: 1581 break; 1582 } 1583 return (ENXIO); 1584 } 1585