1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_exar; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_moxa; 55 static puc_config_f puc_config_oxford_pcie; 56 static puc_config_f puc_config_quatech; 57 static puc_config_f puc_config_syba; 58 static puc_config_f puc_config_siig; 59 static puc_config_f puc_config_timedia; 60 static puc_config_f puc_config_titan; 61 62 const struct puc_cfg puc_pci_devices[] = { 63 64 { 0x0009, 0x7168, 0xffff, 0, 65 "Sunix SUN1889", 66 DEFAULT_RCLK * 8, 67 PUC_PORT_2S, 0x10, 0, 8, 68 }, 69 70 { 0x103c, 0x1048, 0x103c, 0x1049, 71 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 72 DEFAULT_RCLK, 73 PUC_PORT_3S, 0x10, 0, -1, 74 .config_function = puc_config_diva 75 }, 76 77 { 0x103c, 0x1048, 0x103c, 0x104a, 78 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 79 DEFAULT_RCLK, 80 PUC_PORT_2S, 0x10, 0, -1, 81 .config_function = puc_config_diva 82 }, 83 84 { 0x103c, 0x1048, 0x103c, 0x104b, 85 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 86 DEFAULT_RCLK, 87 PUC_PORT_4S, 0x10, 0, -1, 88 .config_function = puc_config_diva 89 }, 90 91 { 0x103c, 0x1048, 0x103c, 0x1223, 92 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 93 DEFAULT_RCLK, 94 PUC_PORT_3S, 0x10, 0, -1, 95 .config_function = puc_config_diva 96 }, 97 98 { 0x103c, 0x1048, 0x103c, 0x1226, 99 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 100 DEFAULT_RCLK, 101 PUC_PORT_3S, 0x10, 0, -1, 102 .config_function = puc_config_diva 103 }, 104 105 { 0x103c, 0x1048, 0x103c, 0x1282, 106 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 107 DEFAULT_RCLK, 108 PUC_PORT_3S, 0x10, 0, -1, 109 .config_function = puc_config_diva 110 }, 111 112 { 0x10b5, 0x1076, 0x10b5, 0x1076, 113 "VScom PCI-800", 114 DEFAULT_RCLK * 8, 115 PUC_PORT_8S, 0x18, 0, 8, 116 }, 117 118 { 0x10b5, 0x1077, 0x10b5, 0x1077, 119 "VScom PCI-400", 120 DEFAULT_RCLK * 8, 121 PUC_PORT_4S, 0x18, 0, 8, 122 }, 123 124 { 0x10b5, 0x1103, 0x10b5, 0x1103, 125 "VScom PCI-200", 126 DEFAULT_RCLK * 8, 127 PUC_PORT_2S, 0x18, 4, 0, 128 }, 129 130 /* 131 * Boca Research Turbo Serial 658 (8 serial port) card. 132 * Appears to be the same as Chase Research PLC PCI-FAST8 133 * and Perle PCI-FAST8 Multi-Port serial cards. 134 */ 135 { 0x10b5, 0x9050, 0x12e0, 0x0021, 136 "Boca Research Turbo Serial 658", 137 DEFAULT_RCLK * 4, 138 PUC_PORT_8S, 0x18, 0, 8, 139 }, 140 141 { 0x10b5, 0x9050, 0x12e0, 0x0031, 142 "Boca Research Turbo Serial 654", 143 DEFAULT_RCLK * 4, 144 PUC_PORT_4S, 0x18, 0, 8, 145 }, 146 147 /* 148 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 149 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 150 * into the subsystem fields, and claims that it's a 151 * network/misc (0x02/0x80) device. 152 */ 153 { 0x10b5, 0x9050, 0xd84d, 0x6808, 154 "Dolphin Peripherals 4035", 155 DEFAULT_RCLK, 156 PUC_PORT_2S, 0x18, 4, 0, 157 }, 158 159 /* 160 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 161 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 162 * into the subsystem fields, and claims that it's a 163 * network/misc (0x02/0x80) device. 164 */ 165 { 0x10b5, 0x9050, 0xd84d, 0x6810, 166 "Dolphin Peripherals 4014", 167 0, 168 PUC_PORT_2P, 0x20, 4, 0, 169 }, 170 171 { 0x10e8, 0x818e, 0xffff, 0, 172 "Applied Micro Circuits 8 Port UART", 173 DEFAULT_RCLK, 174 PUC_PORT_8S, 0x14, -1, -1, 175 .config_function = puc_config_amc 176 }, 177 178 { 0x11fe, 0x8010, 0xffff, 0, 179 "Comtrol RocketPort 550/8 RJ11 part A", 180 DEFAULT_RCLK * 4, 181 PUC_PORT_4S, 0x10, 0, 8, 182 }, 183 184 { 0x11fe, 0x8011, 0xffff, 0, 185 "Comtrol RocketPort 550/8 RJ11 part B", 186 DEFAULT_RCLK * 4, 187 PUC_PORT_4S, 0x10, 0, 8, 188 }, 189 190 { 0x11fe, 0x8012, 0xffff, 0, 191 "Comtrol RocketPort 550/8 Octa part A", 192 DEFAULT_RCLK * 4, 193 PUC_PORT_4S, 0x10, 0, 8, 194 }, 195 196 { 0x11fe, 0x8013, 0xffff, 0, 197 "Comtrol RocketPort 550/8 Octa part B", 198 DEFAULT_RCLK * 4, 199 PUC_PORT_4S, 0x10, 0, 8, 200 }, 201 202 { 0x11fe, 0x8014, 0xffff, 0, 203 "Comtrol RocketPort 550/4 RJ45", 204 DEFAULT_RCLK * 4, 205 PUC_PORT_4S, 0x10, 0, 8, 206 }, 207 208 { 0x11fe, 0x8015, 0xffff, 0, 209 "Comtrol RocketPort 550/Quad", 210 DEFAULT_RCLK * 4, 211 PUC_PORT_4S, 0x10, 0, 8, 212 }, 213 214 { 0x11fe, 0x8016, 0xffff, 0, 215 "Comtrol RocketPort 550/16 part A", 216 DEFAULT_RCLK * 4, 217 PUC_PORT_4S, 0x10, 0, 8, 218 }, 219 220 { 0x11fe, 0x8017, 0xffff, 0, 221 "Comtrol RocketPort 550/16 part B", 222 DEFAULT_RCLK * 4, 223 PUC_PORT_12S, 0x10, 0, 8, 224 }, 225 226 { 0x11fe, 0x8018, 0xffff, 0, 227 "Comtrol RocketPort 550/8 part A", 228 DEFAULT_RCLK * 4, 229 PUC_PORT_4S, 0x10, 0, 8, 230 }, 231 232 { 0x11fe, 0x8019, 0xffff, 0, 233 "Comtrol RocketPort 550/8 part B", 234 DEFAULT_RCLK * 4, 235 PUC_PORT_4S, 0x10, 0, 8, 236 }, 237 238 /* 239 * IBM SurePOS 300 Series (481033H) serial ports 240 * Details can be found on the IBM RSS websites 241 */ 242 243 { 0x1014, 0x0297, 0xffff, 0, 244 "IBM SurePOS 300 Series (481033H) serial ports", 245 DEFAULT_RCLK, 246 PUC_PORT_4S, 0x10, 4, 0 247 }, 248 249 /* 250 * SIIG Boards. 251 * 252 * SIIG provides documentation for their boards at: 253 * <URL:http://www.siig.com/downloads.asp> 254 */ 255 256 { 0x131f, 0x1010, 0xffff, 0, 257 "SIIG Cyber I/O PCI 16C550 (10x family)", 258 DEFAULT_RCLK, 259 PUC_PORT_1S1P, 0x18, 4, 0, 260 }, 261 262 { 0x131f, 0x1011, 0xffff, 0, 263 "SIIG Cyber I/O PCI 16C650 (10x family)", 264 DEFAULT_RCLK, 265 PUC_PORT_1S1P, 0x18, 4, 0, 266 }, 267 268 { 0x131f, 0x1012, 0xffff, 0, 269 "SIIG Cyber I/O PCI 16C850 (10x family)", 270 DEFAULT_RCLK, 271 PUC_PORT_1S1P, 0x18, 4, 0, 272 }, 273 274 { 0x131f, 0x1021, 0xffff, 0, 275 "SIIG Cyber Parallel Dual PCI (10x family)", 276 0, 277 PUC_PORT_2P, 0x18, 8, 0, 278 }, 279 280 { 0x131f, 0x1030, 0xffff, 0, 281 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 282 DEFAULT_RCLK, 283 PUC_PORT_2S, 0x18, 4, 0, 284 }, 285 286 { 0x131f, 0x1031, 0xffff, 0, 287 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 288 DEFAULT_RCLK, 289 PUC_PORT_2S, 0x18, 4, 0, 290 }, 291 292 { 0x131f, 0x1032, 0xffff, 0, 293 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 294 DEFAULT_RCLK, 295 PUC_PORT_2S, 0x18, 4, 0, 296 }, 297 298 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 299 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 300 DEFAULT_RCLK, 301 PUC_PORT_2S1P, 0x18, 4, 0, 302 }, 303 304 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 305 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 306 DEFAULT_RCLK, 307 PUC_PORT_2S1P, 0x18, 4, 0, 308 }, 309 310 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 311 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 312 DEFAULT_RCLK, 313 PUC_PORT_2S1P, 0x18, 4, 0, 314 }, 315 316 { 0x131f, 0x1050, 0xffff, 0, 317 "SIIG Cyber 4S PCI 16C550 (10x family)", 318 DEFAULT_RCLK, 319 PUC_PORT_4S, 0x18, 4, 0, 320 }, 321 322 { 0x131f, 0x1051, 0xffff, 0, 323 "SIIG Cyber 4S PCI 16C650 (10x family)", 324 DEFAULT_RCLK, 325 PUC_PORT_4S, 0x18, 4, 0, 326 }, 327 328 { 0x131f, 0x1052, 0xffff, 0, 329 "SIIG Cyber 4S PCI 16C850 (10x family)", 330 DEFAULT_RCLK, 331 PUC_PORT_4S, 0x18, 4, 0, 332 }, 333 334 { 0x131f, 0x2010, 0xffff, 0, 335 "SIIG Cyber I/O PCI 16C550 (20x family)", 336 DEFAULT_RCLK, 337 PUC_PORT_1S1P, 0x10, 4, 0, 338 }, 339 340 { 0x131f, 0x2011, 0xffff, 0, 341 "SIIG Cyber I/O PCI 16C650 (20x family)", 342 DEFAULT_RCLK, 343 PUC_PORT_1S1P, 0x10, 4, 0, 344 }, 345 346 { 0x131f, 0x2012, 0xffff, 0, 347 "SIIG Cyber I/O PCI 16C850 (20x family)", 348 DEFAULT_RCLK, 349 PUC_PORT_1S1P, 0x10, 4, 0, 350 }, 351 352 { 0x131f, 0x2021, 0xffff, 0, 353 "SIIG Cyber Parallel Dual PCI (20x family)", 354 0, 355 PUC_PORT_2P, 0x10, 8, 0, 356 }, 357 358 { 0x131f, 0x2030, 0xffff, 0, 359 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 360 DEFAULT_RCLK, 361 PUC_PORT_2S, 0x10, 4, 0, 362 }, 363 364 { 0x131f, 0x2031, 0xffff, 0, 365 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 366 DEFAULT_RCLK, 367 PUC_PORT_2S, 0x10, 4, 0, 368 }, 369 370 { 0x131f, 0x2032, 0xffff, 0, 371 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 372 DEFAULT_RCLK, 373 PUC_PORT_2S, 0x10, 4, 0, 374 }, 375 376 { 0x131f, 0x2040, 0xffff, 0, 377 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 378 DEFAULT_RCLK, 379 PUC_PORT_1S2P, 0x10, -1, 0, 380 .config_function = puc_config_siig 381 }, 382 383 { 0x131f, 0x2041, 0xffff, 0, 384 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 385 DEFAULT_RCLK, 386 PUC_PORT_1S2P, 0x10, -1, 0, 387 .config_function = puc_config_siig 388 }, 389 390 { 0x131f, 0x2042, 0xffff, 0, 391 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_1S2P, 0x10, -1, 0, 394 .config_function = puc_config_siig 395 }, 396 397 { 0x131f, 0x2050, 0xffff, 0, 398 "SIIG Cyber 4S PCI 16C550 (20x family)", 399 DEFAULT_RCLK, 400 PUC_PORT_4S, 0x10, 4, 0, 401 }, 402 403 { 0x131f, 0x2051, 0xffff, 0, 404 "SIIG Cyber 4S PCI 16C650 (20x family)", 405 DEFAULT_RCLK, 406 PUC_PORT_4S, 0x10, 4, 0, 407 }, 408 409 { 0x131f, 0x2052, 0xffff, 0, 410 "SIIG Cyber 4S PCI 16C850 (20x family)", 411 DEFAULT_RCLK, 412 PUC_PORT_4S, 0x10, 4, 0, 413 }, 414 415 { 0x131f, 0x2060, 0xffff, 0, 416 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 417 DEFAULT_RCLK, 418 PUC_PORT_2S1P, 0x10, 4, 0, 419 }, 420 421 { 0x131f, 0x2061, 0xffff, 0, 422 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 423 DEFAULT_RCLK, 424 PUC_PORT_2S1P, 0x10, 4, 0, 425 }, 426 427 { 0x131f, 0x2062, 0xffff, 0, 428 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 429 DEFAULT_RCLK, 430 PUC_PORT_2S1P, 0x10, 4, 0, 431 }, 432 433 { 0x131f, 0x2081, 0xffff, 0, 434 "SIIG PS8000 8S PCI 16C650 (20x family)", 435 DEFAULT_RCLK, 436 PUC_PORT_8S, 0x10, -1, -1, 437 .config_function = puc_config_siig 438 }, 439 440 { 0x135c, 0x0010, 0xffff, 0, 441 "Quatech QSC-100", 442 -3, /* max 8x clock rate */ 443 PUC_PORT_4S, 0x14, 0, 8, 444 .config_function = puc_config_quatech 445 }, 446 447 { 0x135c, 0x0020, 0xffff, 0, 448 "Quatech DSC-100", 449 -1, /* max 2x clock rate */ 450 PUC_PORT_2S, 0x14, 0, 8, 451 .config_function = puc_config_quatech 452 }, 453 454 { 0x135c, 0x0030, 0xffff, 0, 455 "Quatech DSC-200/300", 456 -1, /* max 2x clock rate */ 457 PUC_PORT_2S, 0x14, 0, 8, 458 .config_function = puc_config_quatech 459 }, 460 461 { 0x135c, 0x0040, 0xffff, 0, 462 "Quatech QSC-200/300", 463 -3, /* max 8x clock rate */ 464 PUC_PORT_4S, 0x14, 0, 8, 465 .config_function = puc_config_quatech 466 }, 467 468 { 0x135c, 0x0050, 0xffff, 0, 469 "Quatech ESC-100D", 470 -3, /* max 8x clock rate */ 471 PUC_PORT_8S, 0x14, 0, 8, 472 .config_function = puc_config_quatech 473 }, 474 475 { 0x135c, 0x0060, 0xffff, 0, 476 "Quatech ESC-100M", 477 -3, /* max 8x clock rate */ 478 PUC_PORT_8S, 0x14, 0, 8, 479 .config_function = puc_config_quatech 480 }, 481 482 { 0x135c, 0x0170, 0xffff, 0, 483 "Quatech QSCLP-100", 484 -1, /* max 2x clock rate */ 485 PUC_PORT_4S, 0x18, 0, 8, 486 .config_function = puc_config_quatech 487 }, 488 489 { 0x135c, 0x0180, 0xffff, 0, 490 "Quatech DSCLP-100", 491 -1, /* max 3x clock rate */ 492 PUC_PORT_2S, 0x18, 0, 8, 493 .config_function = puc_config_quatech 494 }, 495 496 { 0x135c, 0x01b0, 0xffff, 0, 497 "Quatech DSCLP-200/300", 498 -1, /* max 2x clock rate */ 499 PUC_PORT_2S, 0x18, 0, 8, 500 .config_function = puc_config_quatech 501 }, 502 503 { 0x135c, 0x01e0, 0xffff, 0, 504 "Quatech ESCLP-100", 505 -3, /* max 8x clock rate */ 506 PUC_PORT_8S, 0x10, 0, 8, 507 .config_function = puc_config_quatech 508 }, 509 510 { 0x1393, 0x1024, 0xffff, 0, 511 "Moxa Technologies, Smartio CP-102E/PCIe", 512 DEFAULT_RCLK * 8, 513 PUC_PORT_2S, 0x14, 0, -1, 514 .config_function = puc_config_moxa 515 }, 516 517 { 0x1393, 0x1025, 0xffff, 0, 518 "Moxa Technologies, Smartio CP-102EL/PCIe", 519 DEFAULT_RCLK * 8, 520 PUC_PORT_2S, 0x14, 0, -1, 521 .config_function = puc_config_moxa 522 }, 523 524 { 0x1393, 0x1040, 0xffff, 0, 525 "Moxa Technologies, Smartio C104H/PCI", 526 DEFAULT_RCLK * 8, 527 PUC_PORT_4S, 0x18, 0, 8, 528 }, 529 530 { 0x1393, 0x1041, 0xffff, 0, 531 "Moxa Technologies, Smartio CP-104UL/PCI", 532 DEFAULT_RCLK * 8, 533 PUC_PORT_4S, 0x18, 0, 8, 534 }, 535 536 { 0x1393, 0x1042, 0xffff, 0, 537 "Moxa Technologies, Smartio CP-104JU/PCI", 538 DEFAULT_RCLK * 8, 539 PUC_PORT_4S, 0x18, 0, 8, 540 }, 541 542 { 0x1393, 0x1043, 0xffff, 0, 543 "Moxa Technologies, Smartio CP-104EL/PCIe", 544 DEFAULT_RCLK * 8, 545 PUC_PORT_4S, 0x18, 0, 8, 546 }, 547 548 { 0x1393, 0x1045, 0xffff, 0, 549 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 550 DEFAULT_RCLK * 8, 551 PUC_PORT_4S, 0x14, 0, -1, 552 .config_function = puc_config_moxa 553 }, 554 555 { 0x1393, 0x1120, 0xffff, 0, 556 "Moxa Technologies, CP-112UL", 557 DEFAULT_RCLK * 8, 558 PUC_PORT_2S, 0x18, 0, 8, 559 }, 560 561 { 0x1393, 0x1141, 0xffff, 0, 562 "Moxa Technologies, Industio CP-114", 563 DEFAULT_RCLK * 8, 564 PUC_PORT_4S, 0x18, 0, 8, 565 }, 566 567 { 0x1393, 0x1144, 0xffff, 0, 568 "Moxa Technologies, Smartio CP-114EL/PCIe", 569 DEFAULT_RCLK * 8, 570 PUC_PORT_4S, 0x14, 0, -1, 571 .config_function = puc_config_moxa 572 }, 573 574 { 0x1393, 0x1182, 0xffff, 0, 575 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 576 DEFAULT_RCLK * 8, 577 PUC_PORT_8S, 0x14, 0, -1, 578 .config_function = puc_config_moxa 579 }, 580 581 { 0x1393, 0x1680, 0xffff, 0, 582 "Moxa Technologies, C168H/PCI", 583 DEFAULT_RCLK * 8, 584 PUC_PORT_8S, 0x18, 0, 8, 585 }, 586 587 { 0x1393, 0x1681, 0xffff, 0, 588 "Moxa Technologies, C168U/PCI", 589 DEFAULT_RCLK * 8, 590 PUC_PORT_8S, 0x18, 0, 8, 591 }, 592 593 { 0x1393, 0x1682, 0xffff, 0, 594 "Moxa Technologies, CP-168EL/PCIe", 595 DEFAULT_RCLK * 8, 596 PUC_PORT_8S, 0x18, 0, 8, 597 }, 598 599 { 0x1393, 0x1683, 0xffff, 0, 600 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 601 DEFAULT_RCLK * 8, 602 PUC_PORT_8S, 0x14, 0, -1, 603 .config_function = puc_config_moxa 604 }, 605 606 { 0x13a8, 0x0152, 0xffff, 0, 607 "Exar XR17C/D152", 608 DEFAULT_RCLK * 8, 609 PUC_PORT_2S, 0x10, 0, -1, 610 .config_function = puc_config_exar 611 }, 612 613 { 0x13a8, 0x0154, 0xffff, 0, 614 "Exar XR17C154", 615 DEFAULT_RCLK * 8, 616 PUC_PORT_4S, 0x10, 0, -1, 617 .config_function = puc_config_exar 618 }, 619 620 { 0x13a8, 0x0158, 0xffff, 0, 621 "Exar XR17C158", 622 DEFAULT_RCLK * 8, 623 PUC_PORT_8S, 0x10, 0, -1, 624 .config_function = puc_config_exar 625 }, 626 627 { 0x13a8, 0x0258, 0xffff, 0, 628 "Exar XR17V258IV", 629 DEFAULT_RCLK * 8, 630 PUC_PORT_8S, 0x10, 0, -1, 631 }, 632 633 { 0x1407, 0x0100, 0xffff, 0, 634 "Lava Computers Dual Serial", 635 DEFAULT_RCLK, 636 PUC_PORT_2S, 0x10, 4, 0, 637 }, 638 639 { 0x1407, 0x0101, 0xffff, 0, 640 "Lava Computers Quatro A", 641 DEFAULT_RCLK, 642 PUC_PORT_2S, 0x10, 4, 0, 643 }, 644 645 { 0x1407, 0x0102, 0xffff, 0, 646 "Lava Computers Quatro B", 647 DEFAULT_RCLK, 648 PUC_PORT_2S, 0x10, 4, 0, 649 }, 650 651 { 0x1407, 0x0120, 0xffff, 0, 652 "Lava Computers Quattro-PCI A", 653 DEFAULT_RCLK, 654 PUC_PORT_2S, 0x10, 4, 0, 655 }, 656 657 { 0x1407, 0x0121, 0xffff, 0, 658 "Lava Computers Quattro-PCI B", 659 DEFAULT_RCLK, 660 PUC_PORT_2S, 0x10, 4, 0, 661 }, 662 663 { 0x1407, 0x0180, 0xffff, 0, 664 "Lava Computers Octo A", 665 DEFAULT_RCLK, 666 PUC_PORT_4S, 0x10, 4, 0, 667 }, 668 669 { 0x1407, 0x0181, 0xffff, 0, 670 "Lava Computers Octo B", 671 DEFAULT_RCLK, 672 PUC_PORT_4S, 0x10, 4, 0, 673 }, 674 675 { 0x1409, 0x7268, 0xffff, 0, 676 "Sunix SUN1888", 677 0, 678 PUC_PORT_2P, 0x10, 0, 8, 679 }, 680 681 { 0x1409, 0x7168, 0xffff, 0, 682 NULL, 683 DEFAULT_RCLK * 8, 684 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 685 .config_function = puc_config_timedia 686 }, 687 688 /* 689 * Boards with an Oxford Semiconductor chip. 690 * 691 * Oxford Semiconductor provides documentation for their chip at: 692 * <URL:http://www.plxtech.com/products/uart/> 693 * 694 * As sold by Kouwell <URL:http://www.kouwell.com/>. 695 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 696 */ 697 { 698 0x1415, 0x9501, 0x10fc ,0xc070, 699 "I-O DATA RSA-PCI2/R", 700 DEFAULT_RCLK * 8, 701 PUC_PORT_2S, 0x10, 0, 8, 702 }, 703 704 { 0x1415, 0x9501, 0x131f, 0x2050, 705 "SIIG Cyber 4 PCI 16550", 706 DEFAULT_RCLK * 10, 707 PUC_PORT_4S, 0x10, 0, 8, 708 }, 709 710 { 0x1415, 0x9501, 0x131f, 0x2051, 711 "SIIG Cyber 4S PCI 16C650 (20x family)", 712 DEFAULT_RCLK * 10, 713 PUC_PORT_4S, 0x10, 0, 8, 714 }, 715 716 { 0x1415, 0x9501, 0x131f, 0x2052, 717 "SIIG Quartet Serial 850", 718 DEFAULT_RCLK * 10, 719 PUC_PORT_4S, 0x10, 0, 8, 720 }, 721 722 { 0x1415, 0x9501, 0x14db, 0x2150, 723 "Kuroutoshikou SERIAL4P-LPPCI2", 724 DEFAULT_RCLK * 10, 725 PUC_PORT_4S, 0x10, 0, 8, 726 }, 727 728 { 0x1415, 0x9501, 0xffff, 0, 729 "Oxford Semiconductor OX16PCI954 UARTs", 730 DEFAULT_RCLK, 731 PUC_PORT_4S, 0x10, 0, 8, 732 }, 733 734 { 0x1415, 0x950a, 0x131f, 0x2030, 735 "SIIG Cyber 2S PCIe", 736 DEFAULT_RCLK * 10, 737 PUC_PORT_2S, 0x10, 0, 8, 738 }, 739 740 { 0x1415, 0x950a, 0x131f, 0x2032, 741 "SIIG Cyber Serial Dual PCI 16C850", 742 DEFAULT_RCLK * 10, 743 PUC_PORT_4S, 0x10, 0, 8, 744 }, 745 746 { 0x1415, 0x950a, 0xffff, 0, 747 "Oxford Semiconductor OX16PCI954 UARTs", 748 DEFAULT_RCLK, 749 PUC_PORT_4S, 0x10, 0, 8, 750 }, 751 752 { 0x1415, 0x9511, 0xffff, 0, 753 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 754 DEFAULT_RCLK, 755 PUC_PORT_4S, 0x10, 0, 8, 756 }, 757 758 { 0x1415, 0x9521, 0xffff, 0, 759 "Oxford Semiconductor OX16PCI952 UARTs", 760 DEFAULT_RCLK, 761 PUC_PORT_2S, 0x10, 4, 0, 762 }, 763 764 { 0x1415, 0x9538, 0xffff, 0, 765 "Oxford Semiconductor OX16PCI958 UARTs", 766 DEFAULT_RCLK * 10, 767 PUC_PORT_8S, 0x18, 0, 8, 768 }, 769 770 /* 771 * Perle boards use Oxford Semiconductor chips, but they store the 772 * Oxford Semiconductor device ID as a subvendor device ID and use 773 * their own device IDs. 774 */ 775 776 { 0x155f, 0x0331, 0xffff, 0, 777 "Perle Ultraport4 Express", 778 DEFAULT_RCLK * 8, 779 PUC_PORT_4S, 0x10, 0, 8, 780 }, 781 782 { 0x155f, 0xB012, 0xffff, 0, 783 "Perle Speed2 LE", 784 DEFAULT_RCLK * 8, 785 PUC_PORT_2S, 0x10, 0, 8, 786 }, 787 788 { 0x155f, 0xB022, 0xffff, 0, 789 "Perle Speed2 LE", 790 DEFAULT_RCLK * 8, 791 PUC_PORT_2S, 0x10, 0, 8, 792 }, 793 794 { 0x155f, 0xB004, 0xffff, 0, 795 "Perle Speed4 LE", 796 DEFAULT_RCLK * 8, 797 PUC_PORT_4S, 0x10, 0, 8, 798 }, 799 800 { 0x155f, 0xB008, 0xffff, 0, 801 "Perle Speed8 LE", 802 DEFAULT_RCLK * 8, 803 PUC_PORT_8S, 0x10, 0, 8, 804 }, 805 806 807 /* 808 * Oxford Semiconductor PCI Express Expresso family 809 * 810 * Found in many 'native' PCI Express serial boards such as: 811 * 812 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 813 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 814 * 815 * Lindy 51189 (4 port) 816 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 817 * 818 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 819 * <URL:http://www.startech.com> 820 */ 821 822 { 0x1415, 0xc138, 0xffff, 0, 823 "Oxford Semiconductor OXPCIe952 UARTs", 824 DEFAULT_RCLK * 0x22, 825 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 826 .config_function = puc_config_oxford_pcie 827 }, 828 829 { 0x1415, 0xc158, 0xffff, 0, 830 "Oxford Semiconductor OXPCIe952 UARTs", 831 DEFAULT_RCLK * 0x22, 832 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 833 .config_function = puc_config_oxford_pcie 834 }, 835 836 { 0x1415, 0xc15d, 0xffff, 0, 837 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 838 DEFAULT_RCLK * 0x22, 839 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 840 .config_function = puc_config_oxford_pcie 841 }, 842 843 { 0x1415, 0xc208, 0xffff, 0, 844 "Oxford Semiconductor OXPCIe954 UARTs", 845 DEFAULT_RCLK * 0x22, 846 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 847 .config_function = puc_config_oxford_pcie 848 }, 849 850 { 0x1415, 0xc20d, 0xffff, 0, 851 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 852 DEFAULT_RCLK * 0x22, 853 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 854 .config_function = puc_config_oxford_pcie 855 }, 856 857 { 0x1415, 0xc308, 0xffff, 0, 858 "Oxford Semiconductor OXPCIe958 UARTs", 859 DEFAULT_RCLK * 0x22, 860 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 861 .config_function = puc_config_oxford_pcie 862 }, 863 864 { 0x1415, 0xc30d, 0xffff, 0, 865 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 866 DEFAULT_RCLK * 0x22, 867 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 868 .config_function = puc_config_oxford_pcie 869 }, 870 871 { 0x14d2, 0x8010, 0xffff, 0, 872 "VScom PCI-100L", 873 DEFAULT_RCLK * 8, 874 PUC_PORT_1S, 0x14, 0, 0, 875 }, 876 877 { 0x14d2, 0x8020, 0xffff, 0, 878 "VScom PCI-200L", 879 DEFAULT_RCLK * 8, 880 PUC_PORT_2S, 0x14, 4, 0, 881 }, 882 883 { 0x14d2, 0x8028, 0xffff, 0, 884 "VScom 200Li", 885 DEFAULT_RCLK, 886 PUC_PORT_2S, 0x20, 0, 8, 887 }, 888 889 /* 890 * VScom (Titan?) PCI-800L. More modern variant of the 891 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 892 * two of them obviously implemented as macro cells in 893 * the ASIC. This causes the weird port access pattern 894 * below, where two of the IO port ranges each access 895 * one of the ASIC UARTs, and a block of IO addresses 896 * access the external UARTs. 897 */ 898 { 0x14d2, 0x8080, 0xffff, 0, 899 "Titan VScom PCI-800L", 900 DEFAULT_RCLK * 8, 901 PUC_PORT_8S, 0x14, -1, -1, 902 .config_function = puc_config_titan 903 }, 904 905 /* 906 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 907 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 908 * device ID 3 and PCI device 1 device ID 4. 909 */ 910 { 0x14d2, 0xa003, 0xffff, 0, 911 "Titan PCI-800H", 912 DEFAULT_RCLK * 8, 913 PUC_PORT_4S, 0x10, 0, 8, 914 }, 915 { 0x14d2, 0xa004, 0xffff, 0, 916 "Titan PCI-800H", 917 DEFAULT_RCLK * 8, 918 PUC_PORT_4S, 0x10, 0, 8, 919 }, 920 921 { 0x14d2, 0xa005, 0xffff, 0, 922 "Titan PCI-200H", 923 DEFAULT_RCLK * 8, 924 PUC_PORT_2S, 0x10, 0, 8, 925 }, 926 927 { 0x14d2, 0xe020, 0xffff, 0, 928 "Titan VScom PCI-200HV2", 929 DEFAULT_RCLK * 8, 930 PUC_PORT_2S, 0x10, 4, 0, 931 }, 932 933 { 0x14d2, 0xa007, 0xffff, 0, 934 "Titan VScom PCIex-800H", 935 DEFAULT_RCLK * 8, 936 PUC_PORT_4S, 0x10, 0, 8, 937 }, 938 939 { 0x14d2, 0xa008, 0xffff, 0, 940 "Titan VScom PCIex-800H", 941 DEFAULT_RCLK * 8, 942 PUC_PORT_4S, 0x10, 0, 8, 943 }, 944 945 { 0x14db, 0x2130, 0xffff, 0, 946 "Avlab Technology, PCI IO 2S", 947 DEFAULT_RCLK, 948 PUC_PORT_2S, 0x10, 4, 0, 949 }, 950 951 { 0x14db, 0x2150, 0xffff, 0, 952 "Avlab Low Profile PCI 4 Serial", 953 DEFAULT_RCLK, 954 PUC_PORT_4S, 0x10, 4, 0, 955 }, 956 957 { 0x14db, 0x2152, 0xffff, 0, 958 "Avlab Low Profile PCI 4 Serial", 959 DEFAULT_RCLK, 960 PUC_PORT_4S, 0x10, 4, 0, 961 }, 962 963 { 0x1592, 0x0781, 0xffff, 0, 964 "Syba Tech Ltd. PCI-4S2P-550-ECP", 965 DEFAULT_RCLK, 966 PUC_PORT_4S1P, 0x10, 0, -1, 967 .config_function = puc_config_syba 968 }, 969 970 { 0x1fd4, 0x1999, 0xffff, 0, 971 "Sunix SER5437A", 972 DEFAULT_RCLK * 8, 973 PUC_PORT_2S, 0x10, 0, 8, 974 }, 975 976 { 0x5372, 0x6873, 0xffff, 0, 977 "Sun 1040 PCI Quad Serial", 978 DEFAULT_RCLK, 979 PUC_PORT_4S, 0x10, 4, 0, 980 }, 981 982 { 0x6666, 0x0001, 0xffff, 0, 983 "Decision Computer Inc, PCCOM 4-port serial", 984 DEFAULT_RCLK, 985 PUC_PORT_4S, 0x1c, 0, 8, 986 }, 987 988 { 0x6666, 0x0002, 0xffff, 0, 989 "Decision Computer Inc, PCCOM 8-port serial", 990 DEFAULT_RCLK, 991 PUC_PORT_8S, 0x1c, 0, 8, 992 }, 993 994 { 0x6666, 0x0004, 0xffff, 0, 995 "PCCOM dual port RS232/422/485", 996 DEFAULT_RCLK, 997 PUC_PORT_2S, 0x1c, 0, 8, 998 }, 999 1000 { 0x9710, 0x9815, 0xffff, 0, 1001 "NetMos NM9815 Dual 1284 Printer port", 1002 0, 1003 PUC_PORT_2P, 0x10, 8, 0, 1004 }, 1005 1006 /* 1007 * This is more specific than the generic NM9835 entry that follows, and 1008 * is placed here to _prevent_ puc from claiming this single port card. 1009 * 1010 * uart(4) will claim this device. 1011 */ 1012 { 0x9710, 0x9835, 0x1000, 1, 1013 "NetMos NM9835 based 1-port serial", 1014 DEFAULT_RCLK, 1015 PUC_PORT_1S, 0x10, 4, 0, 1016 }, 1017 1018 { 0x9710, 0x9835, 0x1000, 2, 1019 "NetMos NM9835 based 2-port serial", 1020 DEFAULT_RCLK, 1021 PUC_PORT_2S, 0x10, 4, 0, 1022 }, 1023 1024 { 0x9710, 0x9835, 0xffff, 0, 1025 "NetMos NM9835 Dual UART and 1284 Printer port", 1026 DEFAULT_RCLK, 1027 PUC_PORT_2S1P, 0x10, 4, 0, 1028 }, 1029 1030 { 0x9710, 0x9845, 0x1000, 0x0006, 1031 "NetMos NM9845 6 Port UART", 1032 DEFAULT_RCLK, 1033 PUC_PORT_6S, 0x10, 4, 0, 1034 }, 1035 1036 { 0x9710, 0x9845, 0xffff, 0, 1037 "NetMos NM9845 Quad UART and 1284 Printer port", 1038 DEFAULT_RCLK, 1039 PUC_PORT_4S1P, 0x10, 4, 0, 1040 }, 1041 1042 { 0x9710, 0x9865, 0xa000, 0x3002, 1043 "NetMos NM9865 Dual UART", 1044 DEFAULT_RCLK, 1045 PUC_PORT_2S, 0x10, 4, 0, 1046 }, 1047 1048 { 0x9710, 0x9865, 0xa000, 0x3003, 1049 "NetMos NM9865 Triple UART", 1050 DEFAULT_RCLK, 1051 PUC_PORT_3S, 0x10, 4, 0, 1052 }, 1053 1054 { 0x9710, 0x9865, 0xa000, 0x3004, 1055 "NetMos NM9865 Quad UART", 1056 DEFAULT_RCLK, 1057 PUC_PORT_4S, 0x10, 4, 0,0 1058 }, 1059 1060 { 0x9710, 0x9865, 0xa000, 0x3011, 1061 "NetMos NM9865 Single UART and 1284 Printer port", 1062 DEFAULT_RCLK, 1063 PUC_PORT_1S1P, 0x10, 4, 0, 1064 }, 1065 1066 { 0x9710, 0x9865, 0xa000, 0x3012, 1067 "NetMos NM9865 Dual UART and 1284 Printer port", 1068 DEFAULT_RCLK, 1069 PUC_PORT_2S1P, 0x10, 4, 0, 1070 }, 1071 1072 { 0x9710, 0x9865, 0xa000, 0x3020, 1073 "NetMos NM9865 Dual 1284 Printer port", 1074 DEFAULT_RCLK, 1075 PUC_PORT_2P, 0x10, 4, 0, 1076 }, 1077 1078 { 0xb00c, 0x021c, 0xffff, 0, 1079 "IC Book Labs Gunboat x4 Lite", 1080 DEFAULT_RCLK, 1081 PUC_PORT_4S, 0x10, 0, 8, 1082 .config_function = puc_config_icbook 1083 }, 1084 1085 { 0xb00c, 0x031c, 0xffff, 0, 1086 "IC Book Labs Gunboat x4 Pro", 1087 DEFAULT_RCLK, 1088 PUC_PORT_4S, 0x10, 0, 8, 1089 .config_function = puc_config_icbook 1090 }, 1091 1092 { 0xb00c, 0x041c, 0xffff, 0, 1093 "IC Book Labs Ironclad x8 Lite", 1094 DEFAULT_RCLK, 1095 PUC_PORT_8S, 0x10, 0, 8, 1096 .config_function = puc_config_icbook 1097 }, 1098 1099 { 0xb00c, 0x051c, 0xffff, 0, 1100 "IC Book Labs Ironclad x8 Pro", 1101 DEFAULT_RCLK, 1102 PUC_PORT_8S, 0x10, 0, 8, 1103 .config_function = puc_config_icbook 1104 }, 1105 1106 { 0xb00c, 0x081c, 0xffff, 0, 1107 "IC Book Labs Dreadnought x16 Pro", 1108 DEFAULT_RCLK * 8, 1109 PUC_PORT_16S, 0x10, 0, 8, 1110 .config_function = puc_config_icbook 1111 }, 1112 1113 { 0xb00c, 0x091c, 0xffff, 0, 1114 "IC Book Labs Dreadnought x16 Lite", 1115 DEFAULT_RCLK, 1116 PUC_PORT_16S, 0x10, 0, 8, 1117 .config_function = puc_config_icbook 1118 }, 1119 1120 { 0xb00c, 0x0a1c, 0xffff, 0, 1121 "IC Book Labs Gunboat x2 Low Profile", 1122 DEFAULT_RCLK, 1123 PUC_PORT_2S, 0x10, 0, 8, 1124 }, 1125 1126 { 0xb00c, 0x0b1c, 0xffff, 0, 1127 "IC Book Labs Gunboat x4 Low Profile", 1128 DEFAULT_RCLK, 1129 PUC_PORT_4S, 0x10, 0, 8, 1130 .config_function = puc_config_icbook 1131 }, 1132 1133 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1134 }; 1135 1136 static int 1137 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1138 intptr_t *res) 1139 { 1140 switch (cmd) { 1141 case PUC_CFG_GET_OFS: 1142 *res = 8 * (port & 1); 1143 return (0); 1144 case PUC_CFG_GET_RID: 1145 *res = 0x14 + (port >> 1) * 4; 1146 return (0); 1147 default: 1148 break; 1149 } 1150 return (ENXIO); 1151 } 1152 1153 static int 1154 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1155 intptr_t *res) 1156 { 1157 const struct puc_cfg *cfg = sc->sc_cfg; 1158 1159 if (cmd == PUC_CFG_GET_OFS) { 1160 if (cfg->subdevice == 0x1282) /* Everest SP */ 1161 port <<= 1; 1162 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1163 port = (port == 3) ? 4 : port; 1164 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1165 return (0); 1166 } 1167 return (ENXIO); 1168 } 1169 1170 static int 1171 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1172 intptr_t *res) 1173 { 1174 if (cmd == PUC_CFG_GET_OFS) { 1175 *res = port * 0x200; 1176 return (0); 1177 } 1178 return (ENXIO); 1179 } 1180 1181 static int 1182 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1183 intptr_t *res) 1184 { 1185 if (cmd == PUC_CFG_GET_ILR) { 1186 *res = PUC_ILR_DIGI; 1187 return (0); 1188 } 1189 return (ENXIO); 1190 } 1191 1192 static int 1193 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1194 intptr_t *res) 1195 { 1196 if (cmd == PUC_CFG_GET_OFS) { 1197 const struct puc_cfg *cfg = sc->sc_cfg; 1198 1199 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1200 port = 7; 1201 *res = port * 0x200; 1202 1203 return 0; 1204 } 1205 return (ENXIO); 1206 } 1207 1208 static int 1209 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1210 intptr_t *res) 1211 { 1212 const struct puc_cfg *cfg = sc->sc_cfg; 1213 struct puc_bar *bar; 1214 uint8_t v0, v1; 1215 1216 switch (cmd) { 1217 case PUC_CFG_SETUP: 1218 /* 1219 * Check if the scratchpad register is enabled or if the 1220 * interrupt status and options registers are active. 1221 */ 1222 bar = puc_get_bar(sc, cfg->rid); 1223 if (bar == NULL) 1224 return (ENXIO); 1225 /* Set DLAB in the LCR register of UART 0. */ 1226 bus_write_1(bar->b_res, 3, 0x80); 1227 /* Write 0 to the SPR register of UART 0. */ 1228 bus_write_1(bar->b_res, 7, 0); 1229 /* Read back the contents of the SPR register of UART 0. */ 1230 v0 = bus_read_1(bar->b_res, 7); 1231 /* Write a specific value to the SPR register of UART 0. */ 1232 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1233 /* Read back the contents of the SPR register of UART 0. */ 1234 v1 = bus_read_1(bar->b_res, 7); 1235 /* Clear DLAB in the LCR register of UART 0. */ 1236 bus_write_1(bar->b_res, 3, 0); 1237 /* Save the two values read-back from the SPR register. */ 1238 sc->sc_cfg_data = (v0 << 8) | v1; 1239 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1240 /* 1241 * The SPR register echoed the two values written 1242 * by us. This means that the SPAD jumper is set. 1243 */ 1244 device_printf(sc->sc_dev, "warning: extra features " 1245 "not usable -- SPAD compatibility enabled\n"); 1246 return (0); 1247 } 1248 if (v0 != 0) { 1249 /* 1250 * The first value doesn't match. This can only mean 1251 * that the SPAD jumper is not set and that a non- 1252 * standard fixed clock multiplier jumper is set. 1253 */ 1254 if (bootverbose) 1255 device_printf(sc->sc_dev, "fixed clock rate " 1256 "multiplier of %d\n", 1 << v0); 1257 if (v0 < -cfg->clock) 1258 device_printf(sc->sc_dev, "warning: " 1259 "suboptimal fixed clock rate multiplier " 1260 "setting\n"); 1261 return (0); 1262 } 1263 /* 1264 * The first value matched, but the second didn't. We know 1265 * that the SPAD jumper is not set. We also know that the 1266 * clock rate multiplier is software controlled *and* that 1267 * we just programmed it to the maximum allowed. 1268 */ 1269 if (bootverbose) 1270 device_printf(sc->sc_dev, "clock rate multiplier of " 1271 "%d selected\n", 1 << -cfg->clock); 1272 return (0); 1273 case PUC_CFG_GET_CLOCK: 1274 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1275 v1 = sc->sc_cfg_data & 0xff; 1276 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1277 /* 1278 * XXX With the SPAD jumper applied, there's no 1279 * easy way of knowing if there's also a clock 1280 * rate multiplier jumper installed. Let's hope 1281 * not... 1282 */ 1283 *res = DEFAULT_RCLK; 1284 } else if (v0 == 0) { 1285 /* 1286 * No clock rate multiplier jumper installed, 1287 * so we programmed the board with the maximum 1288 * multiplier allowed as given to us in the 1289 * clock field of the config record (negated). 1290 */ 1291 *res = DEFAULT_RCLK << -cfg->clock; 1292 } else 1293 *res = DEFAULT_RCLK << v0; 1294 return (0); 1295 case PUC_CFG_GET_ILR: 1296 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1297 v1 = sc->sc_cfg_data & 0xff; 1298 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1299 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1300 return (0); 1301 default: 1302 break; 1303 } 1304 return (ENXIO); 1305 } 1306 1307 static int 1308 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1309 intptr_t *res) 1310 { 1311 static int base[] = { 0x251, 0x3f0, 0 }; 1312 const struct puc_cfg *cfg = sc->sc_cfg; 1313 struct puc_bar *bar; 1314 int efir, idx, ofs; 1315 uint8_t v; 1316 1317 switch (cmd) { 1318 case PUC_CFG_SETUP: 1319 bar = puc_get_bar(sc, cfg->rid); 1320 if (bar == NULL) 1321 return (ENXIO); 1322 1323 /* configure both W83877TFs */ 1324 bus_write_1(bar->b_res, 0x250, 0x89); 1325 bus_write_1(bar->b_res, 0x3f0, 0x87); 1326 bus_write_1(bar->b_res, 0x3f0, 0x87); 1327 idx = 0; 1328 while (base[idx] != 0) { 1329 efir = base[idx]; 1330 bus_write_1(bar->b_res, efir, 0x09); 1331 v = bus_read_1(bar->b_res, efir + 1); 1332 if ((v & 0x0f) != 0x0c) 1333 return (ENXIO); 1334 bus_write_1(bar->b_res, efir, 0x16); 1335 v = bus_read_1(bar->b_res, efir + 1); 1336 bus_write_1(bar->b_res, efir, 0x16); 1337 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1338 bus_write_1(bar->b_res, efir, 0x16); 1339 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1340 ofs = base[idx] & 0x300; 1341 bus_write_1(bar->b_res, efir, 0x23); 1342 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1343 bus_write_1(bar->b_res, efir, 0x24); 1344 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1345 bus_write_1(bar->b_res, efir, 0x25); 1346 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1347 bus_write_1(bar->b_res, efir, 0x17); 1348 bus_write_1(bar->b_res, efir + 1, 0x03); 1349 bus_write_1(bar->b_res, efir, 0x28); 1350 bus_write_1(bar->b_res, efir + 1, 0x43); 1351 idx++; 1352 } 1353 bus_write_1(bar->b_res, 0x250, 0xaa); 1354 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1355 return (0); 1356 case PUC_CFG_GET_OFS: 1357 switch (port) { 1358 case 0: 1359 *res = 0x2f8; 1360 return (0); 1361 case 1: 1362 *res = 0x2e8; 1363 return (0); 1364 case 2: 1365 *res = 0x3f8; 1366 return (0); 1367 case 3: 1368 *res = 0x3e8; 1369 return (0); 1370 case 4: 1371 *res = 0x278; 1372 return (0); 1373 } 1374 break; 1375 default: 1376 break; 1377 } 1378 return (ENXIO); 1379 } 1380 1381 static int 1382 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1383 intptr_t *res) 1384 { 1385 const struct puc_cfg *cfg = sc->sc_cfg; 1386 1387 switch (cmd) { 1388 case PUC_CFG_GET_OFS: 1389 if (cfg->ports == PUC_PORT_8S) { 1390 *res = (port > 4) ? 8 * (port - 4) : 0; 1391 return (0); 1392 } 1393 break; 1394 case PUC_CFG_GET_RID: 1395 if (cfg->ports == PUC_PORT_8S) { 1396 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1397 return (0); 1398 } 1399 if (cfg->ports == PUC_PORT_2S1P) { 1400 switch (port) { 1401 case 0: *res = 0x10; return (0); 1402 case 1: *res = 0x14; return (0); 1403 case 2: *res = 0x1c; return (0); 1404 } 1405 } 1406 break; 1407 default: 1408 break; 1409 } 1410 return (ENXIO); 1411 } 1412 1413 static int 1414 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1415 intptr_t *res) 1416 { 1417 static uint16_t dual[] = { 1418 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1419 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1420 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1421 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1422 0xD079, 0 1423 }; 1424 static uint16_t quad[] = { 1425 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1426 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1427 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1428 0xB157, 0 1429 }; 1430 static uint16_t octa[] = { 1431 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1432 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1433 }; 1434 static struct { 1435 int ports; 1436 uint16_t *ids; 1437 } subdevs[] = { 1438 { 2, dual }, 1439 { 4, quad }, 1440 { 8, octa }, 1441 { 0, NULL } 1442 }; 1443 static char desc[64]; 1444 int dev, id; 1445 uint16_t subdev; 1446 1447 switch (cmd) { 1448 case PUC_CFG_GET_CLOCK: 1449 if (port < 2) 1450 *res = DEFAULT_RCLK * 8; 1451 else 1452 *res = DEFAULT_RCLK; 1453 return (0); 1454 case PUC_CFG_GET_DESC: 1455 snprintf(desc, sizeof(desc), 1456 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1457 *res = (intptr_t)desc; 1458 return (0); 1459 case PUC_CFG_GET_NPORTS: 1460 subdev = pci_get_subdevice(sc->sc_dev); 1461 dev = 0; 1462 while (subdevs[dev].ports != 0) { 1463 id = 0; 1464 while (subdevs[dev].ids[id] != 0) { 1465 if (subdev == subdevs[dev].ids[id]) { 1466 sc->sc_cfg_data = subdevs[dev].ports; 1467 *res = sc->sc_cfg_data; 1468 return (0); 1469 } 1470 id++; 1471 } 1472 dev++; 1473 } 1474 return (ENXIO); 1475 case PUC_CFG_GET_OFS: 1476 *res = (port == 1 || port == 3) ? 8 : 0; 1477 return (0); 1478 case PUC_CFG_GET_RID: 1479 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1480 return (0); 1481 case PUC_CFG_GET_TYPE: 1482 *res = PUC_TYPE_SERIAL; 1483 return (0); 1484 default: 1485 break; 1486 } 1487 return (ENXIO); 1488 } 1489 1490 static int 1491 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1492 intptr_t *res) 1493 { 1494 const struct puc_cfg *cfg = sc->sc_cfg; 1495 int idx; 1496 struct puc_bar *bar; 1497 uint8_t value; 1498 1499 switch (cmd) { 1500 case PUC_CFG_SETUP: 1501 device_printf(sc->sc_dev, "%d UARTs detected\n", 1502 sc->sc_nports); 1503 1504 /* Set UARTs to enhanced mode */ 1505 bar = puc_get_bar(sc, cfg->rid); 1506 if (bar == NULL) 1507 return (ENXIO); 1508 for (idx = 0; idx < sc->sc_nports; idx++) { 1509 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1510 0x92); 1511 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1512 value | 0x10); 1513 } 1514 return (0); 1515 case PUC_CFG_GET_LEN: 1516 *res = 0x200; 1517 return (0); 1518 case PUC_CFG_GET_NPORTS: 1519 /* 1520 * Check if we are being called from puc_bfe_attach() 1521 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1522 * puc_get_bar(), so we return a value of 16. This has cosmetic 1523 * side-effects at worst; in PUC_CFG_GET_DESC, 1524 * (int)sc->sc_cfg_data will not contain the true number of 1525 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1526 * call for this device family anyway. 1527 * 1528 * The check is for initialisation of sc->sc_bar[idx], which is 1529 * only done in puc_bfe_attach(). 1530 */ 1531 idx = 0; 1532 do { 1533 if (sc->sc_bar[idx++].b_rid != -1) { 1534 sc->sc_cfg_data = 16; 1535 *res = sc->sc_cfg_data; 1536 return (0); 1537 } 1538 } while (idx < PUC_PCI_BARS); 1539 1540 bar = puc_get_bar(sc, cfg->rid); 1541 if (bar == NULL) 1542 return (ENXIO); 1543 1544 value = bus_read_1(bar->b_res, 0x04); 1545 if (value == 0) 1546 return (ENXIO); 1547 1548 sc->sc_cfg_data = value; 1549 *res = sc->sc_cfg_data; 1550 return (0); 1551 case PUC_CFG_GET_OFS: 1552 *res = 0x1000 + (port << 9); 1553 return (0); 1554 case PUC_CFG_GET_TYPE: 1555 *res = PUC_TYPE_SERIAL; 1556 return (0); 1557 default: 1558 break; 1559 } 1560 return (ENXIO); 1561 } 1562 1563 static int 1564 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1565 intptr_t *res) 1566 { 1567 switch (cmd) { 1568 case PUC_CFG_GET_OFS: 1569 *res = (port < 3) ? 0 : (port - 2) << 3; 1570 return (0); 1571 case PUC_CFG_GET_RID: 1572 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1573 return (0); 1574 default: 1575 break; 1576 } 1577 return (ENXIO); 1578 } 1579