1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_cronyx; 52 static puc_config_f puc_config_diva; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_quatech; 55 static puc_config_f puc_config_syba; 56 static puc_config_f puc_config_siig; 57 static puc_config_f puc_config_timedia; 58 static puc_config_f puc_config_titan; 59 60 const struct puc_cfg puc_pci_devices[] = { 61 62 { 0x0009, 0x7168, 0xffff, 0, 63 "Sunix SUN1889", 64 DEFAULT_RCLK * 8, 65 PUC_PORT_2S, 0x10, 0, 8, 66 }, 67 68 { 0x103c, 0x1048, 0x103c, 0x1049, 69 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 70 DEFAULT_RCLK, 71 PUC_PORT_3S, 0x10, 0, -1, 72 .config_function = puc_config_diva 73 }, 74 75 { 0x103c, 0x1048, 0x103c, 0x104a, 76 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 77 DEFAULT_RCLK, 78 PUC_PORT_2S, 0x10, 0, -1, 79 .config_function = puc_config_diva 80 }, 81 82 { 0x103c, 0x1048, 0x103c, 0x104b, 83 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 84 DEFAULT_RCLK, 85 PUC_PORT_4S, 0x10, 0, -1, 86 .config_function = puc_config_diva 87 }, 88 89 { 0x103c, 0x1048, 0x103c, 0x1223, 90 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 91 DEFAULT_RCLK, 92 PUC_PORT_3S, 0x10, 0, -1, 93 .config_function = puc_config_diva 94 }, 95 96 { 0x103c, 0x1048, 0x103c, 0x1226, 97 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 98 DEFAULT_RCLK, 99 PUC_PORT_3S, 0x10, 0, -1, 100 .config_function = puc_config_diva 101 }, 102 103 { 0x103c, 0x1048, 0x103c, 0x1282, 104 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 105 DEFAULT_RCLK, 106 PUC_PORT_3S, 0x10, 0, -1, 107 .config_function = puc_config_diva 108 }, 109 110 { 0x10b5, 0x1076, 0x10b5, 0x1076, 111 "VScom PCI-800", 112 DEFAULT_RCLK * 8, 113 PUC_PORT_8S, 0x18, 0, 8, 114 }, 115 116 { 0x10b5, 0x1077, 0x10b5, 0x1077, 117 "VScom PCI-400", 118 DEFAULT_RCLK * 8, 119 PUC_PORT_4S, 0x18, 0, 8, 120 }, 121 122 { 0x10b5, 0x1103, 0x10b5, 0x1103, 123 "VScom PCI-200", 124 DEFAULT_RCLK * 8, 125 PUC_PORT_2S, 0x18, 4, 0, 126 }, 127 128 /* 129 * Boca Research Turbo Serial 658 (8 serial port) card. 130 * Appears to be the same as Chase Research PLC PCI-FAST8 131 * and Perle PCI-FAST8 Multi-Port serial cards. 132 */ 133 { 0x10b5, 0x9050, 0x12e0, 0x0021, 134 "Boca Research Turbo Serial 658", 135 DEFAULT_RCLK * 4, 136 PUC_PORT_8S, 0x18, 0, 8, 137 }, 138 139 { 0x10b5, 0x9050, 0x12e0, 0x0031, 140 "Boca Research Turbo Serial 654", 141 DEFAULT_RCLK * 4, 142 PUC_PORT_4S, 0x18, 0, 8, 143 }, 144 145 /* 146 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 147 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 148 * into the subsystem fields, and claims that it's a 149 * network/misc (0x02/0x80) device. 150 */ 151 { 0x10b5, 0x9050, 0xd84d, 0x6808, 152 "Dolphin Peripherals 4035", 153 DEFAULT_RCLK, 154 PUC_PORT_2S, 0x18, 4, 0, 155 }, 156 157 /* 158 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 159 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 160 * into the subsystem fields, and claims that it's a 161 * network/misc (0x02/0x80) device. 162 */ 163 { 0x10b5, 0x9050, 0xd84d, 0x6810, 164 "Dolphin Peripherals 4014", 165 0, 166 PUC_PORT_2P, 0x20, 4, 0, 167 }, 168 169 { 0x10e8, 0x818e, 0xffff, 0, 170 "Applied Micro Circuits 8 Port UART", 171 DEFAULT_RCLK, 172 PUC_PORT_8S, 0x14, -1, -1, 173 .config_function = puc_config_amc 174 }, 175 176 { 0x11fe, 0x8010, 0xffff, 0, 177 "Comtrol RocketPort 550/8 RJ11 part A", 178 DEFAULT_RCLK * 4, 179 PUC_PORT_4S, 0x10, 0, 8, 180 }, 181 182 { 0x11fe, 0x8011, 0xffff, 0, 183 "Comtrol RocketPort 550/8 RJ11 part B", 184 DEFAULT_RCLK * 4, 185 PUC_PORT_4S, 0x10, 0, 8, 186 }, 187 188 { 0x11fe, 0x8012, 0xffff, 0, 189 "Comtrol RocketPort 550/8 Octa part A", 190 DEFAULT_RCLK * 4, 191 PUC_PORT_4S, 0x10, 0, 8, 192 }, 193 194 { 0x11fe, 0x8013, 0xffff, 0, 195 "Comtrol RocketPort 550/8 Octa part B", 196 DEFAULT_RCLK * 4, 197 PUC_PORT_4S, 0x10, 0, 8, 198 }, 199 200 { 0x11fe, 0x8014, 0xffff, 0, 201 "Comtrol RocketPort 550/4 RJ45", 202 DEFAULT_RCLK * 4, 203 PUC_PORT_4S, 0x10, 0, 8, 204 }, 205 206 { 0x11fe, 0x8015, 0xffff, 0, 207 "Comtrol RocketPort 550/Quad", 208 DEFAULT_RCLK * 4, 209 PUC_PORT_4S, 0x10, 0, 8, 210 }, 211 212 { 0x11fe, 0x8016, 0xffff, 0, 213 "Comtrol RocketPort 550/16 part A", 214 DEFAULT_RCLK * 4, 215 PUC_PORT_4S, 0x10, 0, 8, 216 }, 217 218 { 0x11fe, 0x8017, 0xffff, 0, 219 "Comtrol RocketPort 550/16 part B", 220 DEFAULT_RCLK * 4, 221 PUC_PORT_12S, 0x10, 0, 8, 222 }, 223 224 { 0x11fe, 0x8018, 0xffff, 0, 225 "Comtrol RocketPort 550/8 part A", 226 DEFAULT_RCLK * 4, 227 PUC_PORT_4S, 0x10, 0, 8, 228 }, 229 230 { 0x11fe, 0x8019, 0xffff, 0, 231 "Comtrol RocketPort 550/8 part B", 232 DEFAULT_RCLK * 4, 233 PUC_PORT_4S, 0x10, 0, 8, 234 }, 235 236 /* 237 * SIIG Boards. 238 * 239 * SIIG provides documentation for their boards at: 240 * <URL:http://www.siig.com/downloads.asp> 241 */ 242 243 { 0x131f, 0x1010, 0xffff, 0, 244 "SIIG Cyber I/O PCI 16C550 (10x family)", 245 DEFAULT_RCLK, 246 PUC_PORT_1S1P, 0x18, 4, 0, 247 }, 248 249 { 0x131f, 0x1011, 0xffff, 0, 250 "SIIG Cyber I/O PCI 16C650 (10x family)", 251 DEFAULT_RCLK, 252 PUC_PORT_1S1P, 0x18, 4, 0, 253 }, 254 255 { 0x131f, 0x1012, 0xffff, 0, 256 "SIIG Cyber I/O PCI 16C850 (10x family)", 257 DEFAULT_RCLK, 258 PUC_PORT_1S1P, 0x18, 4, 0, 259 }, 260 261 { 0x131f, 0x1021, 0xffff, 0, 262 "SIIG Cyber Parallel Dual PCI (10x family)", 263 0, 264 PUC_PORT_2P, 0x18, 8, 0, 265 }, 266 267 { 0x131f, 0x1030, 0xffff, 0, 268 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 269 DEFAULT_RCLK, 270 PUC_PORT_2S, 0x18, 4, 0, 271 }, 272 273 { 0x131f, 0x1031, 0xffff, 0, 274 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 275 DEFAULT_RCLK, 276 PUC_PORT_2S, 0x18, 4, 0, 277 }, 278 279 { 0x131f, 0x1032, 0xffff, 0, 280 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 281 DEFAULT_RCLK, 282 PUC_PORT_2S, 0x18, 4, 0, 283 }, 284 285 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 286 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 287 DEFAULT_RCLK, 288 PUC_PORT_2S1P, 0x18, 4, 0, 289 }, 290 291 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 292 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 293 DEFAULT_RCLK, 294 PUC_PORT_2S1P, 0x18, 4, 0, 295 }, 296 297 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 298 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 299 DEFAULT_RCLK, 300 PUC_PORT_2S1P, 0x18, 4, 0, 301 }, 302 303 { 0x131f, 0x1050, 0xffff, 0, 304 "SIIG Cyber 4S PCI 16C550 (10x family)", 305 DEFAULT_RCLK, 306 PUC_PORT_4S, 0x18, 4, 0, 307 }, 308 309 { 0x131f, 0x1051, 0xffff, 0, 310 "SIIG Cyber 4S PCI 16C650 (10x family)", 311 DEFAULT_RCLK, 312 PUC_PORT_4S, 0x18, 4, 0, 313 }, 314 315 { 0x131f, 0x1052, 0xffff, 0, 316 "SIIG Cyber 4S PCI 16C850 (10x family)", 317 DEFAULT_RCLK, 318 PUC_PORT_4S, 0x18, 4, 0, 319 }, 320 321 { 0x131f, 0x2010, 0xffff, 0, 322 "SIIG Cyber I/O PCI 16C550 (20x family)", 323 DEFAULT_RCLK, 324 PUC_PORT_1S1P, 0x10, 4, 0, 325 }, 326 327 { 0x131f, 0x2011, 0xffff, 0, 328 "SIIG Cyber I/O PCI 16C650 (20x family)", 329 DEFAULT_RCLK, 330 PUC_PORT_1S1P, 0x10, 4, 0, 331 }, 332 333 { 0x131f, 0x2012, 0xffff, 0, 334 "SIIG Cyber I/O PCI 16C850 (20x family)", 335 DEFAULT_RCLK, 336 PUC_PORT_1S1P, 0x10, 4, 0, 337 }, 338 339 { 0x131f, 0x2021, 0xffff, 0, 340 "SIIG Cyber Parallel Dual PCI (20x family)", 341 0, 342 PUC_PORT_2P, 0x10, 8, 0, 343 }, 344 345 { 0x131f, 0x2030, 0xffff, 0, 346 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 347 DEFAULT_RCLK, 348 PUC_PORT_2S, 0x10, 4, 0, 349 }, 350 351 { 0x131f, 0x2031, 0xffff, 0, 352 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 353 DEFAULT_RCLK, 354 PUC_PORT_2S, 0x10, 4, 0, 355 }, 356 357 { 0x131f, 0x2032, 0xffff, 0, 358 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 359 DEFAULT_RCLK, 360 PUC_PORT_2S, 0x10, 4, 0, 361 }, 362 363 { 0x131f, 0x2040, 0xffff, 0, 364 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 365 DEFAULT_RCLK, 366 PUC_PORT_1S2P, 0x10, -1, 0, 367 .config_function = puc_config_siig 368 }, 369 370 { 0x131f, 0x2041, 0xffff, 0, 371 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 372 DEFAULT_RCLK, 373 PUC_PORT_1S2P, 0x10, -1, 0, 374 .config_function = puc_config_siig 375 }, 376 377 { 0x131f, 0x2042, 0xffff, 0, 378 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 379 DEFAULT_RCLK, 380 PUC_PORT_1S2P, 0x10, -1, 0, 381 .config_function = puc_config_siig 382 }, 383 384 { 0x131f, 0x2050, 0xffff, 0, 385 "SIIG Cyber 4S PCI 16C550 (20x family)", 386 DEFAULT_RCLK, 387 PUC_PORT_4S, 0x10, 4, 0, 388 }, 389 390 { 0x131f, 0x2051, 0xffff, 0, 391 "SIIG Cyber 4S PCI 16C650 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_4S, 0x10, 4, 0, 394 }, 395 396 { 0x131f, 0x2052, 0xffff, 0, 397 "SIIG Cyber 4S PCI 16C850 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_4S, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2060, 0xffff, 0, 403 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_2S1P, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2061, 0xffff, 0, 409 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 410 DEFAULT_RCLK, 411 PUC_PORT_2S1P, 0x10, 4, 0, 412 }, 413 414 { 0x131f, 0x2062, 0xffff, 0, 415 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S1P, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2081, 0xffff, 0, 421 "SIIG PS8000 8S PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_8S, 0x10, -1, -1, 424 .config_function = puc_config_siig 425 }, 426 427 { 0x135c, 0x0010, 0xffff, 0, 428 "Quatech QSC-100", 429 -3, /* max 8x clock rate */ 430 PUC_PORT_4S, 0x14, 0, 8, 431 .config_function = puc_config_quatech 432 }, 433 434 { 0x135c, 0x0020, 0xffff, 0, 435 "Quatech DSC-100", 436 -1, /* max 2x clock rate */ 437 PUC_PORT_2S, 0x14, 0, 8, 438 .config_function = puc_config_quatech 439 }, 440 441 { 0x135c, 0x0030, 0xffff, 0, 442 "Quatech DSC-200/300", 443 -1, /* max 2x clock rate */ 444 PUC_PORT_2S, 0x14, 0, 8, 445 .config_function = puc_config_quatech 446 }, 447 448 { 0x135c, 0x0040, 0xffff, 0, 449 "Quatech QSC-200/300", 450 -3, /* max 8x clock rate */ 451 PUC_PORT_4S, 0x14, 0, 8, 452 .config_function = puc_config_quatech 453 }, 454 455 { 0x135c, 0x0050, 0xffff, 0, 456 "Quatech ESC-100D", 457 -3, /* max 8x clock rate */ 458 PUC_PORT_8S, 0x14, 0, 8, 459 .config_function = puc_config_quatech 460 }, 461 462 { 0x135c, 0x0060, 0xffff, 0, 463 "Quatech ESC-100M", 464 -3, /* max 8x clock rate */ 465 PUC_PORT_8S, 0x14, 0, 8, 466 .config_function = puc_config_quatech 467 }, 468 469 { 0x135c, 0x0170, 0xffff, 0, 470 "Quatech QSCLP-100", 471 -1, /* max 2x clock rate */ 472 PUC_PORT_4S, 0x18, 0, 8, 473 .config_function = puc_config_quatech 474 }, 475 476 { 0x135c, 0x0180, 0xffff, 0, 477 "Quatech DSCLP-100", 478 -1, /* max 3x clock rate */ 479 PUC_PORT_2S, 0x18, 0, 8, 480 .config_function = puc_config_quatech 481 }, 482 483 { 0x135c, 0x01b0, 0xffff, 0, 484 "Quatech DSCLP-200/300", 485 -1, /* max 2x clock rate */ 486 PUC_PORT_2S, 0x18, 0, 8, 487 .config_function = puc_config_quatech 488 }, 489 490 { 0x135c, 0x01e0, 0xffff, 0, 491 "Quatech ESCLP-100", 492 -3, /* max 8x clock rate */ 493 PUC_PORT_8S, 0x10, 0, 8, 494 .config_function = puc_config_quatech 495 }, 496 497 { 0x1393, 0x1040, 0xffff, 0, 498 "Moxa Technologies, Smartio C104H/PCI", 499 DEFAULT_RCLK * 8, 500 PUC_PORT_4S, 0x18, 0, 8, 501 }, 502 503 { 0x1393, 0x1041, 0xffff, 0, 504 "Moxa Technologies, Smartio CP-104UL/PCI", 505 DEFAULT_RCLK * 8, 506 PUC_PORT_4S, 0x18, 0, 8, 507 }, 508 509 { 0x1393, 0x1043, 0xffff, 0, 510 "Moxa Technologies, Smartio CP-104EL/PCIe", 511 DEFAULT_RCLK * 8, 512 PUC_PORT_4S, 0x18, 0, 8, 513 }, 514 515 { 0x1393, 0x1141, 0xffff, 0, 516 "Moxa Technologies, Industio CP-114", 517 DEFAULT_RCLK * 8, 518 PUC_PORT_4S, 0x18, 0, 8, 519 }, 520 521 { 0x1393, 0x1680, 0xffff, 0, 522 "Moxa Technologies, C168H/PCI", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_8S, 0x18, 0, 8, 525 }, 526 527 { 0x1393, 0x1681, 0xffff, 0, 528 "Moxa Technologies, C168U/PCI", 529 DEFAULT_RCLK * 8, 530 PUC_PORT_8S, 0x18, 0, 8, 531 }, 532 533 { 0x13a8, 0x0158, 0xffff, 0, 534 "Cronyx Omega2-PCI", 535 DEFAULT_RCLK * 8, 536 PUC_PORT_8S, 0x10, 0, -1, 537 .config_function = puc_config_cronyx 538 }, 539 540 { 0x1407, 0x0100, 0xffff, 0, 541 "Lava Computers Dual Serial", 542 DEFAULT_RCLK, 543 PUC_PORT_2S, 0x10, 4, 0, 544 }, 545 546 { 0x1407, 0x0101, 0xffff, 0, 547 "Lava Computers Quatro A", 548 DEFAULT_RCLK, 549 PUC_PORT_2S, 0x10, 4, 0, 550 }, 551 552 { 0x1407, 0x0102, 0xffff, 0, 553 "Lava Computers Quatro B", 554 DEFAULT_RCLK, 555 PUC_PORT_2S, 0x10, 4, 0, 556 }, 557 558 { 0x1407, 0x0120, 0xffff, 0, 559 "Lava Computers Quattro-PCI A", 560 DEFAULT_RCLK, 561 PUC_PORT_2S, 0x10, 4, 0, 562 }, 563 564 { 0x1407, 0x0121, 0xffff, 0, 565 "Lava Computers Quattro-PCI B", 566 DEFAULT_RCLK, 567 PUC_PORT_2S, 0x10, 4, 0, 568 }, 569 570 { 0x1407, 0x0180, 0xffff, 0, 571 "Lava Computers Octo A", 572 DEFAULT_RCLK, 573 PUC_PORT_4S, 0x10, 4, 0, 574 }, 575 576 { 0x1407, 0x0181, 0xffff, 0, 577 "Lava Computers Octo B", 578 DEFAULT_RCLK, 579 PUC_PORT_4S, 0x10, 4, 0, 580 }, 581 582 { 0x1409, 0x7168, 0xffff, 0, 583 NULL, 584 DEFAULT_RCLK * 8, 585 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 586 .config_function = puc_config_timedia 587 }, 588 589 /* 590 * Boards with an Oxford Semiconductor chip. 591 * 592 * Oxford Semiconductor provides documentation for their chip at: 593 * <URL:http://www.oxsemi.com/products/uarts/index.html> 594 * 595 * As sold by Kouwell <URL:http://www.kouwell.com/>. 596 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 597 */ 598 599 { 0x1415, 0x9501, 0x131f, 0x2050, 600 "SIIG Cyber 4 PCI 16550", 601 DEFAULT_RCLK * 10, 602 PUC_PORT_4S, 0x10, 0, 8, 603 }, 604 605 { 0x1415, 0x9501, 0x131f, 0x2051, 606 "SIIG Cyber 4S PCI 16C650 (20x family)", 607 DEFAULT_RCLK * 10, 608 PUC_PORT_4S, 0x10, 0, 8, 609 }, 610 611 { 0x1415, 0x9501, 0xffff, 0, 612 "Oxford Semiconductor OX16PCI954 UARTs", 613 DEFAULT_RCLK, 614 PUC_PORT_4S, 0x10, 0, 8, 615 }, 616 617 { 0x1415, 0x950a, 0xffff, 0, 618 "Oxford Semiconductor OX16PCI954 UARTs", 619 DEFAULT_RCLK, 620 PUC_PORT_4S, 0x10, 0, 8, 621 }, 622 623 { 0x1415, 0x9511, 0xffff, 0, 624 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 625 DEFAULT_RCLK, 626 PUC_PORT_4S, 0x10, 0, 8, 627 }, 628 629 { 0x1415, 0x9521, 0xffff, 0, 630 "Oxford Semiconductor OX16PCI952 UARTs", 631 DEFAULT_RCLK, 632 PUC_PORT_2S, 0x10, 4, 0, 633 }, 634 635 { 0x1415, 0x9538, 0xffff, 0, 636 "Oxford Semiconductor OX16PCI958 UARTs", 637 DEFAULT_RCLK * 10, 638 PUC_PORT_8S, 0x18, 0, 8, 639 }, 640 641 { 0x14d2, 0x8010, 0xffff, 0, 642 "VScom PCI-100L", 643 DEFAULT_RCLK * 8, 644 PUC_PORT_1S, 0x14, 0, 0, 645 }, 646 647 { 0x14d2, 0x8020, 0xffff, 0, 648 "VScom PCI-200L", 649 DEFAULT_RCLK * 8, 650 PUC_PORT_2S, 0x14, 4, 0, 651 }, 652 653 { 0x14d2, 0x8028, 0xffff, 0, 654 "VScom 200Li", 655 DEFAULT_RCLK, 656 PUC_PORT_2S, 0x20, 0, 8, 657 }, 658 659 /* 660 * VScom (Titan?) PCI-800L. More modern variant of the 661 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 662 * two of them obviously implemented as macro cells in 663 * the ASIC. This causes the weird port access pattern 664 * below, where two of the IO port ranges each access 665 * one of the ASIC UARTs, and a block of IO addresses 666 * access the external UARTs. 667 */ 668 { 0x14d2, 0x8080, 0xffff, 0, 669 "Titan VScom PCI-800L", 670 DEFAULT_RCLK * 8, 671 PUC_PORT_8S, 0x14, -1, -1, 672 .config_function = puc_config_titan 673 }, 674 675 /* 676 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 677 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 678 * device ID 3 and PCI device 1 device ID 4. 679 */ 680 { 0x14d2, 0xa003, 0xffff, 0, 681 "Titan PCI-800H", 682 DEFAULT_RCLK * 8, 683 PUC_PORT_4S, 0x10, 0, 8, 684 }, 685 { 0x14d2, 0xa004, 0xffff, 0, 686 "Titan PCI-800H", 687 DEFAULT_RCLK * 8, 688 PUC_PORT_4S, 0x10, 0, 8, 689 }, 690 691 { 0x14d2, 0xa005, 0xffff, 0, 692 "Titan PCI-200H", 693 DEFAULT_RCLK * 8, 694 PUC_PORT_2S, 0x10, 0, 8, 695 }, 696 697 { 0x14d2, 0xe020, 0xffff, 0, 698 "Titan VScom PCI-200HV2", 699 DEFAULT_RCLK * 8, 700 PUC_PORT_2S, 0x10, 4, 0, 701 }, 702 703 { 0x14db, 0x2130, 0xffff, 0, 704 "Avlab Technology, PCI IO 2S", 705 DEFAULT_RCLK, 706 PUC_PORT_2S, 0x10, 4, 0, 707 }, 708 709 { 0x14db, 0x2150, 0xffff, 0, 710 "Avlab Low Profile PCI 4 Serial", 711 DEFAULT_RCLK, 712 PUC_PORT_4S, 0x10, 4, 0, 713 }, 714 715 { 0x14db, 0x2152, 0xffff, 0, 716 "Avlab Low Profile PCI 4 Serial", 717 DEFAULT_RCLK, 718 PUC_PORT_4S, 0x10, 4, 0, 719 }, 720 721 { 0x1592, 0x0781, 0xffff, 0, 722 "Syba Tech Ltd. PCI-4S2P-550-ECP", 723 DEFAULT_RCLK, 724 PUC_PORT_4S1P, 0x10, 0, -1, 725 .config_function = puc_config_syba 726 }, 727 728 { 0x6666, 0x0001, 0xffff, 0, 729 "Decision Computer Inc, PCCOM 4-port serial", 730 DEFAULT_RCLK, 731 PUC_PORT_4S, 0x1c, 0, 8, 732 }, 733 734 { 0x6666, 0x0002, 0xffff, 0, 735 "Decision Computer Inc, PCCOM 8-port serial", 736 DEFAULT_RCLK, 737 PUC_PORT_8S, 0x1c, 0, 8, 738 }, 739 740 { 0x6666, 0x0004, 0xffff, 0, 741 "PCCOM dual port RS232/422/485", 742 DEFAULT_RCLK, 743 PUC_PORT_2S, 0x1c, 0, 8, 744 }, 745 746 { 0x9710, 0x9815, 0xffff, 0, 747 "NetMos NM9815 Dual 1284 Printer port", 748 0, 749 PUC_PORT_2P, 0x10, 8, 0, 750 }, 751 752 { 0x9710, 0x9835, 0xffff, 0, 753 "NetMos NM9835 Dual UART and 1284 Printer port", 754 DEFAULT_RCLK, 755 PUC_PORT_2S1P, 0x10, 4, 0, 756 }, 757 758 { 0x9710, 0x9845, 0x1000, 0x0006, 759 "NetMos NM9845 6 Port UART", 760 DEFAULT_RCLK, 761 PUC_PORT_6S, 0x10, 4, 0, 762 }, 763 764 { 0x9710, 0x9845, 0xffff, 0, 765 "NetMos NM9845 Quad UART and 1284 Printer port", 766 DEFAULT_RCLK, 767 PUC_PORT_4S1P, 0x10, 4, 0, 768 }, 769 770 { 0xb00c, 0x021c, 0xffff, 0, 771 "IC Book Labs Gunboat x4 Lite", 772 DEFAULT_RCLK, 773 PUC_PORT_4S, 0x10, 0, 8, 774 .config_function = puc_config_icbook 775 }, 776 777 { 0xb00c, 0x031c, 0xffff, 0, 778 "IC Book Labs Gunboat x4 Pro", 779 DEFAULT_RCLK, 780 PUC_PORT_4S, 0x10, 0, 8, 781 .config_function = puc_config_icbook 782 }, 783 784 { 0xb00c, 0x041c, 0xffff, 0, 785 "IC Book Labs Ironclad x8 Lite", 786 DEFAULT_RCLK, 787 PUC_PORT_8S, 0x10, 0, 8, 788 .config_function = puc_config_icbook 789 }, 790 791 { 0xb00c, 0x051c, 0xffff, 0, 792 "IC Book Labs Ironclad x8 Pro", 793 DEFAULT_RCLK, 794 PUC_PORT_8S, 0x10, 0, 8, 795 .config_function = puc_config_icbook 796 }, 797 798 { 0xb00c, 0x081c, 0xffff, 0, 799 "IC Book Labs Dreadnought x16 Pro", 800 DEFAULT_RCLK * 8, 801 PUC_PORT_16S, 0x10, 0, 8, 802 .config_function = puc_config_icbook 803 }, 804 805 { 0xb00c, 0x091c, 0xffff, 0, 806 "IC Book Labs Dreadnought x16 Lite", 807 DEFAULT_RCLK, 808 PUC_PORT_16S, 0x10, 0, 8, 809 .config_function = puc_config_icbook 810 }, 811 812 { 0xb00c, 0x0a1c, 0xffff, 0, 813 "IC Book Labs Gunboat x2 Low Profile", 814 DEFAULT_RCLK, 815 PUC_PORT_2S, 0x10, 0, 8, 816 }, 817 818 { 0xb00c, 0x0b1c, 0xffff, 0, 819 "IC Book Labs Gunboat x4 Low Profile", 820 DEFAULT_RCLK, 821 PUC_PORT_4S, 0x10, 0, 8, 822 .config_function = puc_config_icbook 823 }, 824 825 { 0xffff, 0, 0xffff, 0, NULL, 0 } 826 }; 827 828 static int 829 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 830 intptr_t *res) 831 { 832 switch (cmd) { 833 case PUC_CFG_GET_OFS: 834 *res = 8 * (port & 1); 835 return (0); 836 case PUC_CFG_GET_RID: 837 *res = 0x14 + (port >> 1) * 4; 838 return (0); 839 default: 840 break; 841 } 842 return (ENXIO); 843 } 844 845 static int 846 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 847 intptr_t *res) 848 { 849 if (cmd == PUC_CFG_GET_OFS) { 850 *res = port * 0x200; 851 return (0); 852 } 853 return (ENXIO); 854 } 855 856 static int 857 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 858 intptr_t *res) 859 { 860 const struct puc_cfg *cfg = sc->sc_cfg; 861 862 if (cmd == PUC_CFG_GET_OFS) { 863 if (cfg->subdevice == 0x1282) /* Everest SP */ 864 port <<= 1; 865 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 866 port = (port == 3) ? 4 : port; 867 *res = port * 8 + ((port > 2) ? 0x18 : 0); 868 return (0); 869 } 870 return (ENXIO); 871 } 872 873 static int 874 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 875 intptr_t *res) 876 { 877 if (cmd == PUC_CFG_GET_ILR) { 878 *res = PUC_ILR_DIGI; 879 return (0); 880 } 881 return (ENXIO); 882 } 883 884 static int 885 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 886 intptr_t *res) 887 { 888 const struct puc_cfg *cfg = sc->sc_cfg; 889 struct puc_bar *bar; 890 uint8_t v0, v1; 891 892 switch (cmd) { 893 case PUC_CFG_SETUP: 894 /* 895 * Check if the scratchpad register is enabled or if the 896 * interrupt status and options registers are active. 897 */ 898 bar = puc_get_bar(sc, cfg->rid); 899 if (bar == NULL) 900 return (ENXIO); 901 /* Set DLAB in the LCR register of UART 0. */ 902 bus_write_1(bar->b_res, 3, 0x80); 903 /* Write 0 to the SPR register of UART 0. */ 904 bus_write_1(bar->b_res, 7, 0); 905 /* Read back the contents of the SPR register of UART 0. */ 906 v0 = bus_read_1(bar->b_res, 7); 907 /* Write a specific value to the SPR register of UART 0. */ 908 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 909 /* Read back the contents of the SPR register of UART 0. */ 910 v1 = bus_read_1(bar->b_res, 7); 911 /* Clear DLAB in the LCR register of UART 0. */ 912 bus_write_1(bar->b_res, 3, 0); 913 /* Save the two values read-back from the SPR register. */ 914 sc->sc_cfg_data = (v0 << 8) | v1; 915 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 916 /* 917 * The SPR register echoed the two values written 918 * by us. This means that the SPAD jumper is set. 919 */ 920 device_printf(sc->sc_dev, "warning: extra features " 921 "not usable -- SPAD compatibility enabled\n"); 922 return (0); 923 } 924 if (v0 != 0) { 925 /* 926 * The first value doesn't match. This can only mean 927 * that the SPAD jumper is not set and that a non- 928 * standard fixed clock multiplier jumper is set. 929 */ 930 if (bootverbose) 931 device_printf(sc->sc_dev, "fixed clock rate " 932 "multiplier of %d\n", 1 << v0); 933 if (v0 < -cfg->clock) 934 device_printf(sc->sc_dev, "warning: " 935 "suboptimal fixed clock rate multiplier " 936 "setting\n"); 937 return (0); 938 } 939 /* 940 * The first value matched, but the second didn't. We know 941 * that the SPAD jumper is not set. We also know that the 942 * clock rate multiplier is software controlled *and* that 943 * we just programmed it to the maximum allowed. 944 */ 945 if (bootverbose) 946 device_printf(sc->sc_dev, "clock rate multiplier of " 947 "%d selected\n", 1 << -cfg->clock); 948 return (0); 949 case PUC_CFG_GET_CLOCK: 950 v0 = (sc->sc_cfg_data >> 8) & 0xff; 951 v1 = sc->sc_cfg_data & 0xff; 952 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 953 /* 954 * XXX With the SPAD jumper applied, there's no 955 * easy way of knowing if there's also a clock 956 * rate multiplier jumper installed. Let's hope 957 * not... 958 */ 959 *res = DEFAULT_RCLK; 960 } else if (v0 == 0) { 961 /* 962 * No clock rate multiplier jumper installed, 963 * so we programmed the board with the maximum 964 * multiplier allowed as given to us in the 965 * clock field of the config record (negated). 966 */ 967 *res = DEFAULT_RCLK << -cfg->clock; 968 } else 969 *res = DEFAULT_RCLK << v0; 970 return (0); 971 case PUC_CFG_GET_ILR: 972 v0 = (sc->sc_cfg_data >> 8) & 0xff; 973 v1 = sc->sc_cfg_data & 0xff; 974 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 975 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 976 return (0); 977 default: 978 break; 979 } 980 return (ENXIO); 981 } 982 983 static int 984 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 985 intptr_t *res) 986 { 987 static int base[] = { 0x251, 0x3f0, 0 }; 988 const struct puc_cfg *cfg = sc->sc_cfg; 989 struct puc_bar *bar; 990 int efir, idx, ofs; 991 uint8_t v; 992 993 switch (cmd) { 994 case PUC_CFG_SETUP: 995 bar = puc_get_bar(sc, cfg->rid); 996 if (bar == NULL) 997 return (ENXIO); 998 999 /* configure both W83877TFs */ 1000 bus_write_1(bar->b_res, 0x250, 0x89); 1001 bus_write_1(bar->b_res, 0x3f0, 0x87); 1002 bus_write_1(bar->b_res, 0x3f0, 0x87); 1003 idx = 0; 1004 while (base[idx] != 0) { 1005 efir = base[idx]; 1006 bus_write_1(bar->b_res, efir, 0x09); 1007 v = bus_read_1(bar->b_res, efir + 1); 1008 if ((v & 0x0f) != 0x0c) 1009 return (ENXIO); 1010 bus_write_1(bar->b_res, efir, 0x16); 1011 v = bus_read_1(bar->b_res, efir + 1); 1012 bus_write_1(bar->b_res, efir, 0x16); 1013 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1014 bus_write_1(bar->b_res, efir, 0x16); 1015 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1016 ofs = base[idx] & 0x300; 1017 bus_write_1(bar->b_res, efir, 0x23); 1018 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1019 bus_write_1(bar->b_res, efir, 0x24); 1020 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1021 bus_write_1(bar->b_res, efir, 0x25); 1022 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1023 bus_write_1(bar->b_res, efir, 0x17); 1024 bus_write_1(bar->b_res, efir + 1, 0x03); 1025 bus_write_1(bar->b_res, efir, 0x28); 1026 bus_write_1(bar->b_res, efir + 1, 0x43); 1027 idx++; 1028 } 1029 bus_write_1(bar->b_res, 0x250, 0xaa); 1030 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1031 return (0); 1032 case PUC_CFG_GET_OFS: 1033 switch (port) { 1034 case 0: 1035 *res = 0x2f8; 1036 return (0); 1037 case 1: 1038 *res = 0x2e8; 1039 return (0); 1040 case 2: 1041 *res = 0x3f8; 1042 return (0); 1043 case 3: 1044 *res = 0x3e8; 1045 return (0); 1046 case 4: 1047 *res = 0x278; 1048 return (0); 1049 } 1050 break; 1051 default: 1052 break; 1053 } 1054 return (ENXIO); 1055 } 1056 1057 static int 1058 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1059 intptr_t *res) 1060 { 1061 const struct puc_cfg *cfg = sc->sc_cfg; 1062 1063 switch (cmd) { 1064 case PUC_CFG_GET_OFS: 1065 if (cfg->ports == PUC_PORT_8S) { 1066 *res = (port > 4) ? 8 * (port - 4) : 0; 1067 return (0); 1068 } 1069 break; 1070 case PUC_CFG_GET_RID: 1071 if (cfg->ports == PUC_PORT_8S) { 1072 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1073 return (0); 1074 } 1075 if (cfg->ports == PUC_PORT_2S1P) { 1076 switch (port) { 1077 case 0: *res = 0x10; return (0); 1078 case 1: *res = 0x14; return (0); 1079 case 2: *res = 0x1c; return (0); 1080 } 1081 } 1082 break; 1083 default: 1084 break; 1085 } 1086 return (ENXIO); 1087 } 1088 1089 static int 1090 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1091 intptr_t *res) 1092 { 1093 static uint16_t dual[] = { 1094 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1095 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1096 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1097 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1098 0xD079, 0 1099 }; 1100 static uint16_t quad[] = { 1101 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1102 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1103 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1104 0xB157, 0 1105 }; 1106 static uint16_t octa[] = { 1107 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1108 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1109 }; 1110 static struct { 1111 int ports; 1112 uint16_t *ids; 1113 } subdevs[] = { 1114 { 2, dual }, 1115 { 4, quad }, 1116 { 8, octa }, 1117 { 0, NULL } 1118 }; 1119 static char desc[64]; 1120 int dev, id; 1121 uint16_t subdev; 1122 1123 switch (cmd) { 1124 case PUC_CFG_GET_DESC: 1125 snprintf(desc, sizeof(desc), 1126 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1127 *res = (intptr_t)desc; 1128 return (0); 1129 case PUC_CFG_GET_NPORTS: 1130 subdev = pci_get_subdevice(sc->sc_dev); 1131 dev = 0; 1132 while (subdevs[dev].ports != 0) { 1133 id = 0; 1134 while (subdevs[dev].ids[id] != 0) { 1135 if (subdev == subdevs[dev].ids[id]) { 1136 sc->sc_cfg_data = subdevs[dev].ports; 1137 *res = sc->sc_cfg_data; 1138 return (0); 1139 } 1140 id++; 1141 } 1142 dev++; 1143 } 1144 return (ENXIO); 1145 case PUC_CFG_GET_OFS: 1146 *res = (port == 1 || port == 3) ? 8 : 0; 1147 return (0); 1148 case PUC_CFG_GET_RID: 1149 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1150 return (0); 1151 case PUC_CFG_GET_TYPE: 1152 *res = PUC_TYPE_SERIAL; 1153 return (0); 1154 default: 1155 break; 1156 } 1157 return (ENXIO); 1158 } 1159 1160 static int 1161 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1162 intptr_t *res) 1163 { 1164 switch (cmd) { 1165 case PUC_CFG_GET_OFS: 1166 *res = (port < 3) ? 0 : (port - 2) << 3; 1167 return (0); 1168 case PUC_CFG_GET_RID: 1169 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1170 return (0); 1171 default: 1172 break; 1173 } 1174 return (ENXIO); 1175 } 1176