1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_exar; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_quatech; 55 static puc_config_f puc_config_syba; 56 static puc_config_f puc_config_siig; 57 static puc_config_f puc_config_timedia; 58 static puc_config_f puc_config_titan; 59 static puc_config_f puc_config_oxford_pcie; 60 61 const struct puc_cfg puc_pci_devices[] = { 62 63 { 0x0009, 0x7168, 0xffff, 0, 64 "Sunix SUN1889", 65 DEFAULT_RCLK * 8, 66 PUC_PORT_2S, 0x10, 0, 8, 67 }, 68 69 { 0x103c, 0x1048, 0x103c, 0x1049, 70 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 71 DEFAULT_RCLK, 72 PUC_PORT_3S, 0x10, 0, -1, 73 .config_function = puc_config_diva 74 }, 75 76 { 0x103c, 0x1048, 0x103c, 0x104a, 77 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 78 DEFAULT_RCLK, 79 PUC_PORT_2S, 0x10, 0, -1, 80 .config_function = puc_config_diva 81 }, 82 83 { 0x103c, 0x1048, 0x103c, 0x104b, 84 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 85 DEFAULT_RCLK, 86 PUC_PORT_4S, 0x10, 0, -1, 87 .config_function = puc_config_diva 88 }, 89 90 { 0x103c, 0x1048, 0x103c, 0x1223, 91 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 92 DEFAULT_RCLK, 93 PUC_PORT_3S, 0x10, 0, -1, 94 .config_function = puc_config_diva 95 }, 96 97 { 0x103c, 0x1048, 0x103c, 0x1226, 98 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 99 DEFAULT_RCLK, 100 PUC_PORT_3S, 0x10, 0, -1, 101 .config_function = puc_config_diva 102 }, 103 104 { 0x103c, 0x1048, 0x103c, 0x1282, 105 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 106 DEFAULT_RCLK, 107 PUC_PORT_3S, 0x10, 0, -1, 108 .config_function = puc_config_diva 109 }, 110 111 { 0x10b5, 0x1076, 0x10b5, 0x1076, 112 "VScom PCI-800", 113 DEFAULT_RCLK * 8, 114 PUC_PORT_8S, 0x18, 0, 8, 115 }, 116 117 { 0x10b5, 0x1077, 0x10b5, 0x1077, 118 "VScom PCI-400", 119 DEFAULT_RCLK * 8, 120 PUC_PORT_4S, 0x18, 0, 8, 121 }, 122 123 { 0x10b5, 0x1103, 0x10b5, 0x1103, 124 "VScom PCI-200", 125 DEFAULT_RCLK * 8, 126 PUC_PORT_2S, 0x18, 4, 0, 127 }, 128 129 /* 130 * Boca Research Turbo Serial 658 (8 serial port) card. 131 * Appears to be the same as Chase Research PLC PCI-FAST8 132 * and Perle PCI-FAST8 Multi-Port serial cards. 133 */ 134 { 0x10b5, 0x9050, 0x12e0, 0x0021, 135 "Boca Research Turbo Serial 658", 136 DEFAULT_RCLK * 4, 137 PUC_PORT_8S, 0x18, 0, 8, 138 }, 139 140 { 0x10b5, 0x9050, 0x12e0, 0x0031, 141 "Boca Research Turbo Serial 654", 142 DEFAULT_RCLK * 4, 143 PUC_PORT_4S, 0x18, 0, 8, 144 }, 145 146 /* 147 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 148 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 149 * into the subsystem fields, and claims that it's a 150 * network/misc (0x02/0x80) device. 151 */ 152 { 0x10b5, 0x9050, 0xd84d, 0x6808, 153 "Dolphin Peripherals 4035", 154 DEFAULT_RCLK, 155 PUC_PORT_2S, 0x18, 4, 0, 156 }, 157 158 /* 159 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 160 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 161 * into the subsystem fields, and claims that it's a 162 * network/misc (0x02/0x80) device. 163 */ 164 { 0x10b5, 0x9050, 0xd84d, 0x6810, 165 "Dolphin Peripherals 4014", 166 0, 167 PUC_PORT_2P, 0x20, 4, 0, 168 }, 169 170 { 0x10e8, 0x818e, 0xffff, 0, 171 "Applied Micro Circuits 8 Port UART", 172 DEFAULT_RCLK, 173 PUC_PORT_8S, 0x14, -1, -1, 174 .config_function = puc_config_amc 175 }, 176 177 { 0x11fe, 0x8010, 0xffff, 0, 178 "Comtrol RocketPort 550/8 RJ11 part A", 179 DEFAULT_RCLK * 4, 180 PUC_PORT_4S, 0x10, 0, 8, 181 }, 182 183 { 0x11fe, 0x8011, 0xffff, 0, 184 "Comtrol RocketPort 550/8 RJ11 part B", 185 DEFAULT_RCLK * 4, 186 PUC_PORT_4S, 0x10, 0, 8, 187 }, 188 189 { 0x11fe, 0x8012, 0xffff, 0, 190 "Comtrol RocketPort 550/8 Octa part A", 191 DEFAULT_RCLK * 4, 192 PUC_PORT_4S, 0x10, 0, 8, 193 }, 194 195 { 0x11fe, 0x8013, 0xffff, 0, 196 "Comtrol RocketPort 550/8 Octa part B", 197 DEFAULT_RCLK * 4, 198 PUC_PORT_4S, 0x10, 0, 8, 199 }, 200 201 { 0x11fe, 0x8014, 0xffff, 0, 202 "Comtrol RocketPort 550/4 RJ45", 203 DEFAULT_RCLK * 4, 204 PUC_PORT_4S, 0x10, 0, 8, 205 }, 206 207 { 0x11fe, 0x8015, 0xffff, 0, 208 "Comtrol RocketPort 550/Quad", 209 DEFAULT_RCLK * 4, 210 PUC_PORT_4S, 0x10, 0, 8, 211 }, 212 213 { 0x11fe, 0x8016, 0xffff, 0, 214 "Comtrol RocketPort 550/16 part A", 215 DEFAULT_RCLK * 4, 216 PUC_PORT_4S, 0x10, 0, 8, 217 }, 218 219 { 0x11fe, 0x8017, 0xffff, 0, 220 "Comtrol RocketPort 550/16 part B", 221 DEFAULT_RCLK * 4, 222 PUC_PORT_12S, 0x10, 0, 8, 223 }, 224 225 { 0x11fe, 0x8018, 0xffff, 0, 226 "Comtrol RocketPort 550/8 part A", 227 DEFAULT_RCLK * 4, 228 PUC_PORT_4S, 0x10, 0, 8, 229 }, 230 231 { 0x11fe, 0x8019, 0xffff, 0, 232 "Comtrol RocketPort 550/8 part B", 233 DEFAULT_RCLK * 4, 234 PUC_PORT_4S, 0x10, 0, 8, 235 }, 236 237 /* 238 * IBM SurePOS 300 Series (481033H) serial ports 239 * Details can be found on the IBM RSS websites 240 */ 241 242 { 0x1014, 0x0297, 0xffff, 0, 243 "IBM SurePOS 300 Series (481033H) serial ports", 244 DEFAULT_RCLK, 245 PUC_PORT_4S, 0x10, 4, 0 246 }, 247 248 /* 249 * SIIG Boards. 250 * 251 * SIIG provides documentation for their boards at: 252 * <URL:http://www.siig.com/downloads.asp> 253 */ 254 255 { 0x131f, 0x1010, 0xffff, 0, 256 "SIIG Cyber I/O PCI 16C550 (10x family)", 257 DEFAULT_RCLK, 258 PUC_PORT_1S1P, 0x18, 4, 0, 259 }, 260 261 { 0x131f, 0x1011, 0xffff, 0, 262 "SIIG Cyber I/O PCI 16C650 (10x family)", 263 DEFAULT_RCLK, 264 PUC_PORT_1S1P, 0x18, 4, 0, 265 }, 266 267 { 0x131f, 0x1012, 0xffff, 0, 268 "SIIG Cyber I/O PCI 16C850 (10x family)", 269 DEFAULT_RCLK, 270 PUC_PORT_1S1P, 0x18, 4, 0, 271 }, 272 273 { 0x131f, 0x1021, 0xffff, 0, 274 "SIIG Cyber Parallel Dual PCI (10x family)", 275 0, 276 PUC_PORT_2P, 0x18, 8, 0, 277 }, 278 279 { 0x131f, 0x1030, 0xffff, 0, 280 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 281 DEFAULT_RCLK, 282 PUC_PORT_2S, 0x18, 4, 0, 283 }, 284 285 { 0x131f, 0x1031, 0xffff, 0, 286 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 287 DEFAULT_RCLK, 288 PUC_PORT_2S, 0x18, 4, 0, 289 }, 290 291 { 0x131f, 0x1032, 0xffff, 0, 292 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 293 DEFAULT_RCLK, 294 PUC_PORT_2S, 0x18, 4, 0, 295 }, 296 297 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 298 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 299 DEFAULT_RCLK, 300 PUC_PORT_2S1P, 0x18, 4, 0, 301 }, 302 303 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 304 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 305 DEFAULT_RCLK, 306 PUC_PORT_2S1P, 0x18, 4, 0, 307 }, 308 309 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 310 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 311 DEFAULT_RCLK, 312 PUC_PORT_2S1P, 0x18, 4, 0, 313 }, 314 315 { 0x131f, 0x1050, 0xffff, 0, 316 "SIIG Cyber 4S PCI 16C550 (10x family)", 317 DEFAULT_RCLK, 318 PUC_PORT_4S, 0x18, 4, 0, 319 }, 320 321 { 0x131f, 0x1051, 0xffff, 0, 322 "SIIG Cyber 4S PCI 16C650 (10x family)", 323 DEFAULT_RCLK, 324 PUC_PORT_4S, 0x18, 4, 0, 325 }, 326 327 { 0x131f, 0x1052, 0xffff, 0, 328 "SIIG Cyber 4S PCI 16C850 (10x family)", 329 DEFAULT_RCLK, 330 PUC_PORT_4S, 0x18, 4, 0, 331 }, 332 333 { 0x131f, 0x2010, 0xffff, 0, 334 "SIIG Cyber I/O PCI 16C550 (20x family)", 335 DEFAULT_RCLK, 336 PUC_PORT_1S1P, 0x10, 4, 0, 337 }, 338 339 { 0x131f, 0x2011, 0xffff, 0, 340 "SIIG Cyber I/O PCI 16C650 (20x family)", 341 DEFAULT_RCLK, 342 PUC_PORT_1S1P, 0x10, 4, 0, 343 }, 344 345 { 0x131f, 0x2012, 0xffff, 0, 346 "SIIG Cyber I/O PCI 16C850 (20x family)", 347 DEFAULT_RCLK, 348 PUC_PORT_1S1P, 0x10, 4, 0, 349 }, 350 351 { 0x131f, 0x2021, 0xffff, 0, 352 "SIIG Cyber Parallel Dual PCI (20x family)", 353 0, 354 PUC_PORT_2P, 0x10, 8, 0, 355 }, 356 357 { 0x131f, 0x2030, 0xffff, 0, 358 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 359 DEFAULT_RCLK, 360 PUC_PORT_2S, 0x10, 4, 0, 361 }, 362 363 { 0x131f, 0x2031, 0xffff, 0, 364 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 365 DEFAULT_RCLK, 366 PUC_PORT_2S, 0x10, 4, 0, 367 }, 368 369 { 0x131f, 0x2032, 0xffff, 0, 370 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 371 DEFAULT_RCLK, 372 PUC_PORT_2S, 0x10, 4, 0, 373 }, 374 375 { 0x131f, 0x2040, 0xffff, 0, 376 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 377 DEFAULT_RCLK, 378 PUC_PORT_1S2P, 0x10, -1, 0, 379 .config_function = puc_config_siig 380 }, 381 382 { 0x131f, 0x2041, 0xffff, 0, 383 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 384 DEFAULT_RCLK, 385 PUC_PORT_1S2P, 0x10, -1, 0, 386 .config_function = puc_config_siig 387 }, 388 389 { 0x131f, 0x2042, 0xffff, 0, 390 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 391 DEFAULT_RCLK, 392 PUC_PORT_1S2P, 0x10, -1, 0, 393 .config_function = puc_config_siig 394 }, 395 396 { 0x131f, 0x2050, 0xffff, 0, 397 "SIIG Cyber 4S PCI 16C550 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_4S, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2051, 0xffff, 0, 403 "SIIG Cyber 4S PCI 16C650 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_4S, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2052, 0xffff, 0, 409 "SIIG Cyber 4S PCI 16C850 (20x family)", 410 DEFAULT_RCLK, 411 PUC_PORT_4S, 0x10, 4, 0, 412 }, 413 414 { 0x131f, 0x2060, 0xffff, 0, 415 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S1P, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2061, 0xffff, 0, 421 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_2S1P, 0x10, 4, 0, 424 }, 425 426 { 0x131f, 0x2062, 0xffff, 0, 427 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 428 DEFAULT_RCLK, 429 PUC_PORT_2S1P, 0x10, 4, 0, 430 }, 431 432 { 0x131f, 0x2081, 0xffff, 0, 433 "SIIG PS8000 8S PCI 16C650 (20x family)", 434 DEFAULT_RCLK, 435 PUC_PORT_8S, 0x10, -1, -1, 436 .config_function = puc_config_siig 437 }, 438 439 { 0x135c, 0x0010, 0xffff, 0, 440 "Quatech QSC-100", 441 -3, /* max 8x clock rate */ 442 PUC_PORT_4S, 0x14, 0, 8, 443 .config_function = puc_config_quatech 444 }, 445 446 { 0x135c, 0x0020, 0xffff, 0, 447 "Quatech DSC-100", 448 -1, /* max 2x clock rate */ 449 PUC_PORT_2S, 0x14, 0, 8, 450 .config_function = puc_config_quatech 451 }, 452 453 { 0x135c, 0x0030, 0xffff, 0, 454 "Quatech DSC-200/300", 455 -1, /* max 2x clock rate */ 456 PUC_PORT_2S, 0x14, 0, 8, 457 .config_function = puc_config_quatech 458 }, 459 460 { 0x135c, 0x0040, 0xffff, 0, 461 "Quatech QSC-200/300", 462 -3, /* max 8x clock rate */ 463 PUC_PORT_4S, 0x14, 0, 8, 464 .config_function = puc_config_quatech 465 }, 466 467 { 0x135c, 0x0050, 0xffff, 0, 468 "Quatech ESC-100D", 469 -3, /* max 8x clock rate */ 470 PUC_PORT_8S, 0x14, 0, 8, 471 .config_function = puc_config_quatech 472 }, 473 474 { 0x135c, 0x0060, 0xffff, 0, 475 "Quatech ESC-100M", 476 -3, /* max 8x clock rate */ 477 PUC_PORT_8S, 0x14, 0, 8, 478 .config_function = puc_config_quatech 479 }, 480 481 { 0x135c, 0x0170, 0xffff, 0, 482 "Quatech QSCLP-100", 483 -1, /* max 2x clock rate */ 484 PUC_PORT_4S, 0x18, 0, 8, 485 .config_function = puc_config_quatech 486 }, 487 488 { 0x135c, 0x0180, 0xffff, 0, 489 "Quatech DSCLP-100", 490 -1, /* max 3x clock rate */ 491 PUC_PORT_2S, 0x18, 0, 8, 492 .config_function = puc_config_quatech 493 }, 494 495 { 0x135c, 0x01b0, 0xffff, 0, 496 "Quatech DSCLP-200/300", 497 -1, /* max 2x clock rate */ 498 PUC_PORT_2S, 0x18, 0, 8, 499 .config_function = puc_config_quatech 500 }, 501 502 { 0x135c, 0x01e0, 0xffff, 0, 503 "Quatech ESCLP-100", 504 -3, /* max 8x clock rate */ 505 PUC_PORT_8S, 0x10, 0, 8, 506 .config_function = puc_config_quatech 507 }, 508 509 { 0x1393, 0x1040, 0xffff, 0, 510 "Moxa Technologies, Smartio C104H/PCI", 511 DEFAULT_RCLK * 8, 512 PUC_PORT_4S, 0x18, 0, 8, 513 }, 514 515 { 0x1393, 0x1041, 0xffff, 0, 516 "Moxa Technologies, Smartio CP-104UL/PCI", 517 DEFAULT_RCLK * 8, 518 PUC_PORT_4S, 0x18, 0, 8, 519 }, 520 521 { 0x1393, 0x1043, 0xffff, 0, 522 "Moxa Technologies, Smartio CP-104EL/PCIe", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_4S, 0x18, 0, 8, 525 }, 526 527 { 0x1393, 0x1141, 0xffff, 0, 528 "Moxa Technologies, Industio CP-114", 529 DEFAULT_RCLK * 8, 530 PUC_PORT_4S, 0x18, 0, 8, 531 }, 532 533 { 0x1393, 0x1680, 0xffff, 0, 534 "Moxa Technologies, C168H/PCI", 535 DEFAULT_RCLK * 8, 536 PUC_PORT_8S, 0x18, 0, 8, 537 }, 538 539 { 0x1393, 0x1681, 0xffff, 0, 540 "Moxa Technologies, C168U/PCI", 541 DEFAULT_RCLK * 8, 542 PUC_PORT_8S, 0x18, 0, 8, 543 }, 544 545 { 0x1393, 0x1682, 0xffff, 0, 546 "Moxa Technologies, CP-168EL/PCIe", 547 DEFAULT_RCLK * 8, 548 PUC_PORT_8S, 0x18, 0, 8, 549 }, 550 551 { 0x13a8, 0x0152, 0xffff, 0, 552 "Exar XR17C/D152", 553 DEFAULT_RCLK * 8, 554 PUC_PORT_2S, 0x10, 0, -1, 555 .config_function = puc_config_exar 556 }, 557 558 { 0x13a8, 0x0154, 0xffff, 0, 559 "Exar XR17C154", 560 DEFAULT_RCLK * 8, 561 PUC_PORT_4S, 0x10, 0, -1, 562 .config_function = puc_config_exar 563 }, 564 565 { 0x13a8, 0x0158, 0xffff, 0, 566 "Exar XR17C158", 567 DEFAULT_RCLK * 8, 568 PUC_PORT_8S, 0x10, 0, -1, 569 .config_function = puc_config_exar 570 }, 571 572 { 0x13a8, 0x0258, 0xffff, 0, 573 "Exar XR17V258IV", 574 DEFAULT_RCLK * 8, 575 PUC_PORT_8S, 0x10, 0, -1, 576 }, 577 578 { 0x1407, 0x0100, 0xffff, 0, 579 "Lava Computers Dual Serial", 580 DEFAULT_RCLK, 581 PUC_PORT_2S, 0x10, 4, 0, 582 }, 583 584 { 0x1407, 0x0101, 0xffff, 0, 585 "Lava Computers Quatro A", 586 DEFAULT_RCLK, 587 PUC_PORT_2S, 0x10, 4, 0, 588 }, 589 590 { 0x1407, 0x0102, 0xffff, 0, 591 "Lava Computers Quatro B", 592 DEFAULT_RCLK, 593 PUC_PORT_2S, 0x10, 4, 0, 594 }, 595 596 { 0x1407, 0x0120, 0xffff, 0, 597 "Lava Computers Quattro-PCI A", 598 DEFAULT_RCLK, 599 PUC_PORT_2S, 0x10, 4, 0, 600 }, 601 602 { 0x1407, 0x0121, 0xffff, 0, 603 "Lava Computers Quattro-PCI B", 604 DEFAULT_RCLK, 605 PUC_PORT_2S, 0x10, 4, 0, 606 }, 607 608 { 0x1407, 0x0180, 0xffff, 0, 609 "Lava Computers Octo A", 610 DEFAULT_RCLK, 611 PUC_PORT_4S, 0x10, 4, 0, 612 }, 613 614 { 0x1407, 0x0181, 0xffff, 0, 615 "Lava Computers Octo B", 616 DEFAULT_RCLK, 617 PUC_PORT_4S, 0x10, 4, 0, 618 }, 619 620 { 0x1409, 0x7268, 0xffff, 0, 621 "Sunix SUN1888", 622 0, 623 PUC_PORT_2P, 0x10, 0, 8, 624 }, 625 626 { 0x1409, 0x7168, 0xffff, 0, 627 NULL, 628 DEFAULT_RCLK * 8, 629 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 630 .config_function = puc_config_timedia 631 }, 632 633 /* 634 * Boards with an Oxford Semiconductor chip. 635 * 636 * Oxford Semiconductor provides documentation for their chip at: 637 * <URL:http://www.plxtech.com/products/uart/> 638 * 639 * As sold by Kouwell <URL:http://www.kouwell.com/>. 640 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 641 */ 642 643 { 0x1415, 0x9501, 0x131f, 0x2050, 644 "SIIG Cyber 4 PCI 16550", 645 DEFAULT_RCLK * 10, 646 PUC_PORT_4S, 0x10, 0, 8, 647 }, 648 649 { 0x1415, 0x9501, 0x131f, 0x2051, 650 "SIIG Cyber 4S PCI 16C650 (20x family)", 651 DEFAULT_RCLK * 10, 652 PUC_PORT_4S, 0x10, 0, 8, 653 }, 654 655 { 0x1415, 0x9501, 0x131f, 0x2052, 656 "SIIG Quartet Serial 850", 657 DEFAULT_RCLK * 10, 658 PUC_PORT_4S, 0x10, 0, 8, 659 }, 660 661 { 0x1415, 0x9501, 0x14db, 0x2150, 662 "Kuroutoshikou SERIAL4P-LPPCI2", 663 DEFAULT_RCLK * 10, 664 PUC_PORT_4S, 0x10, 0, 8, 665 }, 666 667 { 0x1415, 0x9501, 0xffff, 0, 668 "Oxford Semiconductor OX16PCI954 UARTs", 669 DEFAULT_RCLK, 670 PUC_PORT_4S, 0x10, 0, 8, 671 }, 672 673 { 0x1415, 0x950a, 0x131f, 0x2030, 674 "SIIG Cyber 2S PCIe", 675 DEFAULT_RCLK * 10, 676 PUC_PORT_2S, 0x10, 0, 8, 677 }, 678 679 { 0x1415, 0x950a, 0xffff, 0, 680 "Oxford Semiconductor OX16PCI954 UARTs", 681 DEFAULT_RCLK, 682 PUC_PORT_4S, 0x10, 0, 8, 683 }, 684 685 { 0x1415, 0x9511, 0xffff, 0, 686 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 687 DEFAULT_RCLK, 688 PUC_PORT_4S, 0x10, 0, 8, 689 }, 690 691 { 0x1415, 0x9521, 0xffff, 0, 692 "Oxford Semiconductor OX16PCI952 UARTs", 693 DEFAULT_RCLK, 694 PUC_PORT_2S, 0x10, 4, 0, 695 }, 696 697 { 0x1415, 0x9538, 0xffff, 0, 698 "Oxford Semiconductor OX16PCI958 UARTs", 699 DEFAULT_RCLK * 10, 700 PUC_PORT_8S, 0x18, 0, 8, 701 }, 702 703 /* 704 * Perle boards use Oxford Semiconductor chips, but they store the 705 * Oxford Semiconductor device ID as a subvendor device ID and use 706 * their own device IDs. 707 */ 708 709 { 0x155f, 0x0331, 0xffff, 0, 710 "Perle Speed4 LE", 711 DEFAULT_RCLK * 8, 712 PUC_PORT_4S, 0x10, 0, 8, 713 }, 714 715 /* 716 * Oxford Semiconductor PCI Express Expresso family 717 * 718 * Found in many 'native' PCI Express serial boards such as: 719 * 720 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 721 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 722 * 723 * Lindy 51189 (4 port) 724 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 725 * 726 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 727 * <URL:http://www.startech.com> 728 */ 729 730 { 0x1415, 0xc158, 0xffff, 0, 731 "Oxford Semiconductor OXPCIe952 UARTs", 732 DEFAULT_RCLK * 0x22, 733 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 734 .config_function = puc_config_oxford_pcie 735 }, 736 737 { 0x1415, 0xc15d, 0xffff, 0, 738 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 739 DEFAULT_RCLK * 0x22, 740 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 741 .config_function = puc_config_oxford_pcie 742 }, 743 744 { 0x1415, 0xc208, 0xffff, 0, 745 "Oxford Semiconductor OXPCIe954 UARTs", 746 DEFAULT_RCLK * 0x22, 747 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 748 .config_function = puc_config_oxford_pcie 749 }, 750 751 { 0x1415, 0xc20d, 0xffff, 0, 752 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 753 DEFAULT_RCLK * 0x22, 754 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 755 .config_function = puc_config_oxford_pcie 756 }, 757 758 { 0x1415, 0xc308, 0xffff, 0, 759 "Oxford Semiconductor OXPCIe958 UARTs", 760 DEFAULT_RCLK * 0x22, 761 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 762 .config_function = puc_config_oxford_pcie 763 }, 764 765 { 0x1415, 0xc30d, 0xffff, 0, 766 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 767 DEFAULT_RCLK * 0x22, 768 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 769 .config_function = puc_config_oxford_pcie 770 }, 771 772 { 0x14d2, 0x8010, 0xffff, 0, 773 "VScom PCI-100L", 774 DEFAULT_RCLK * 8, 775 PUC_PORT_1S, 0x14, 0, 0, 776 }, 777 778 { 0x14d2, 0x8020, 0xffff, 0, 779 "VScom PCI-200L", 780 DEFAULT_RCLK * 8, 781 PUC_PORT_2S, 0x14, 4, 0, 782 }, 783 784 { 0x14d2, 0x8028, 0xffff, 0, 785 "VScom 200Li", 786 DEFAULT_RCLK, 787 PUC_PORT_2S, 0x20, 0, 8, 788 }, 789 790 /* 791 * VScom (Titan?) PCI-800L. More modern variant of the 792 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 793 * two of them obviously implemented as macro cells in 794 * the ASIC. This causes the weird port access pattern 795 * below, where two of the IO port ranges each access 796 * one of the ASIC UARTs, and a block of IO addresses 797 * access the external UARTs. 798 */ 799 { 0x14d2, 0x8080, 0xffff, 0, 800 "Titan VScom PCI-800L", 801 DEFAULT_RCLK * 8, 802 PUC_PORT_8S, 0x14, -1, -1, 803 .config_function = puc_config_titan 804 }, 805 806 /* 807 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 808 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 809 * device ID 3 and PCI device 1 device ID 4. 810 */ 811 { 0x14d2, 0xa003, 0xffff, 0, 812 "Titan PCI-800H", 813 DEFAULT_RCLK * 8, 814 PUC_PORT_4S, 0x10, 0, 8, 815 }, 816 { 0x14d2, 0xa004, 0xffff, 0, 817 "Titan PCI-800H", 818 DEFAULT_RCLK * 8, 819 PUC_PORT_4S, 0x10, 0, 8, 820 }, 821 822 { 0x14d2, 0xa005, 0xffff, 0, 823 "Titan PCI-200H", 824 DEFAULT_RCLK * 8, 825 PUC_PORT_2S, 0x10, 0, 8, 826 }, 827 828 { 0x14d2, 0xe020, 0xffff, 0, 829 "Titan VScom PCI-200HV2", 830 DEFAULT_RCLK * 8, 831 PUC_PORT_2S, 0x10, 4, 0, 832 }, 833 834 { 0x14db, 0x2130, 0xffff, 0, 835 "Avlab Technology, PCI IO 2S", 836 DEFAULT_RCLK, 837 PUC_PORT_2S, 0x10, 4, 0, 838 }, 839 840 { 0x14db, 0x2150, 0xffff, 0, 841 "Avlab Low Profile PCI 4 Serial", 842 DEFAULT_RCLK, 843 PUC_PORT_4S, 0x10, 4, 0, 844 }, 845 846 { 0x14db, 0x2152, 0xffff, 0, 847 "Avlab Low Profile PCI 4 Serial", 848 DEFAULT_RCLK, 849 PUC_PORT_4S, 0x10, 4, 0, 850 }, 851 852 { 0x1592, 0x0781, 0xffff, 0, 853 "Syba Tech Ltd. PCI-4S2P-550-ECP", 854 DEFAULT_RCLK, 855 PUC_PORT_4S1P, 0x10, 0, -1, 856 .config_function = puc_config_syba 857 }, 858 859 { 0x6666, 0x0001, 0xffff, 0, 860 "Decision Computer Inc, PCCOM 4-port serial", 861 DEFAULT_RCLK, 862 PUC_PORT_4S, 0x1c, 0, 8, 863 }, 864 865 { 0x6666, 0x0002, 0xffff, 0, 866 "Decision Computer Inc, PCCOM 8-port serial", 867 DEFAULT_RCLK, 868 PUC_PORT_8S, 0x1c, 0, 8, 869 }, 870 871 { 0x6666, 0x0004, 0xffff, 0, 872 "PCCOM dual port RS232/422/485", 873 DEFAULT_RCLK, 874 PUC_PORT_2S, 0x1c, 0, 8, 875 }, 876 877 { 0x9710, 0x9815, 0xffff, 0, 878 "NetMos NM9815 Dual 1284 Printer port", 879 0, 880 PUC_PORT_2P, 0x10, 8, 0, 881 }, 882 883 /* 884 * This is more specific than the generic NM9835 entry that follows, and 885 * is placed here to _prevent_ puc from claiming this single port card. 886 * 887 * uart(4) will claim this device. 888 */ 889 { 0x9710, 0x9835, 0x1000, 1, 890 "NetMos NM9835 based 1-port serial", 891 DEFAULT_RCLK, 892 PUC_PORT_1S, 0x10, 4, 0, 893 }, 894 895 { 0x9710, 0x9835, 0x1000, 2, 896 "NetMos NM9835 based 2-port serial", 897 DEFAULT_RCLK, 898 PUC_PORT_2S, 0x10, 4, 0, 899 }, 900 901 { 0x9710, 0x9835, 0xffff, 0, 902 "NetMos NM9835 Dual UART and 1284 Printer port", 903 DEFAULT_RCLK, 904 PUC_PORT_2S1P, 0x10, 4, 0, 905 }, 906 907 { 0x9710, 0x9845, 0x1000, 0x0006, 908 "NetMos NM9845 6 Port UART", 909 DEFAULT_RCLK, 910 PUC_PORT_6S, 0x10, 4, 0, 911 }, 912 913 { 0x9710, 0x9845, 0xffff, 0, 914 "NetMos NM9845 Quad UART and 1284 Printer port", 915 DEFAULT_RCLK, 916 PUC_PORT_4S1P, 0x10, 4, 0, 917 }, 918 919 { 0x9710, 0x9865, 0xa000, 0x3002, 920 "NetMos NM9865 Dual UART", 921 DEFAULT_RCLK, 922 PUC_PORT_2S, 0x10, 4, 0, 923 }, 924 925 { 0x9710, 0x9865, 0xa000, 0x3003, 926 "NetMos NM9865 Triple UART", 927 DEFAULT_RCLK, 928 PUC_PORT_3S, 0x10, 4, 0, 929 }, 930 931 { 0x9710, 0x9865, 0xa000, 0x3004, 932 "NetMos NM9865 Quad UART", 933 DEFAULT_RCLK, 934 PUC_PORT_4S, 0x10, 4, 0,0 935 }, 936 937 { 0x9710, 0x9865, 0xa000, 0x3011, 938 "NetMos NM9865 Single UART and 1284 Printer port", 939 DEFAULT_RCLK, 940 PUC_PORT_1S1P, 0x10, 4, 0, 941 }, 942 943 { 0x9710, 0x9865, 0xa000, 0x3012, 944 "NetMos NM9865 Dual UART and 1284 Printer port", 945 DEFAULT_RCLK, 946 PUC_PORT_2S1P, 0x10, 4, 0, 947 }, 948 949 { 0x9710, 0x9865, 0xa000, 0x3020, 950 "NetMos NM9865 Dual 1284 Printer port", 951 DEFAULT_RCLK, 952 PUC_PORT_2P, 0x10, 4, 0, 953 }, 954 955 { 0xb00c, 0x021c, 0xffff, 0, 956 "IC Book Labs Gunboat x4 Lite", 957 DEFAULT_RCLK, 958 PUC_PORT_4S, 0x10, 0, 8, 959 .config_function = puc_config_icbook 960 }, 961 962 { 0xb00c, 0x031c, 0xffff, 0, 963 "IC Book Labs Gunboat x4 Pro", 964 DEFAULT_RCLK, 965 PUC_PORT_4S, 0x10, 0, 8, 966 .config_function = puc_config_icbook 967 }, 968 969 { 0xb00c, 0x041c, 0xffff, 0, 970 "IC Book Labs Ironclad x8 Lite", 971 DEFAULT_RCLK, 972 PUC_PORT_8S, 0x10, 0, 8, 973 .config_function = puc_config_icbook 974 }, 975 976 { 0xb00c, 0x051c, 0xffff, 0, 977 "IC Book Labs Ironclad x8 Pro", 978 DEFAULT_RCLK, 979 PUC_PORT_8S, 0x10, 0, 8, 980 .config_function = puc_config_icbook 981 }, 982 983 { 0xb00c, 0x081c, 0xffff, 0, 984 "IC Book Labs Dreadnought x16 Pro", 985 DEFAULT_RCLK * 8, 986 PUC_PORT_16S, 0x10, 0, 8, 987 .config_function = puc_config_icbook 988 }, 989 990 { 0xb00c, 0x091c, 0xffff, 0, 991 "IC Book Labs Dreadnought x16 Lite", 992 DEFAULT_RCLK, 993 PUC_PORT_16S, 0x10, 0, 8, 994 .config_function = puc_config_icbook 995 }, 996 997 { 0xb00c, 0x0a1c, 0xffff, 0, 998 "IC Book Labs Gunboat x2 Low Profile", 999 DEFAULT_RCLK, 1000 PUC_PORT_2S, 0x10, 0, 8, 1001 }, 1002 1003 { 0xb00c, 0x0b1c, 0xffff, 0, 1004 "IC Book Labs Gunboat x4 Low Profile", 1005 DEFAULT_RCLK, 1006 PUC_PORT_4S, 0x10, 0, 8, 1007 .config_function = puc_config_icbook 1008 }, 1009 1010 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1011 }; 1012 1013 static int 1014 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1015 intptr_t *res) 1016 { 1017 switch (cmd) { 1018 case PUC_CFG_GET_OFS: 1019 *res = 8 * (port & 1); 1020 return (0); 1021 case PUC_CFG_GET_RID: 1022 *res = 0x14 + (port >> 1) * 4; 1023 return (0); 1024 default: 1025 break; 1026 } 1027 return (ENXIO); 1028 } 1029 1030 static int 1031 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1032 intptr_t *res) 1033 { 1034 const struct puc_cfg *cfg = sc->sc_cfg; 1035 1036 if (cmd == PUC_CFG_GET_OFS) { 1037 if (cfg->subdevice == 0x1282) /* Everest SP */ 1038 port <<= 1; 1039 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1040 port = (port == 3) ? 4 : port; 1041 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1042 return (0); 1043 } 1044 return (ENXIO); 1045 } 1046 1047 static int 1048 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1049 intptr_t *res) 1050 { 1051 if (cmd == PUC_CFG_GET_OFS) { 1052 *res = port * 0x200; 1053 return (0); 1054 } 1055 return (ENXIO); 1056 } 1057 1058 static int 1059 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1060 intptr_t *res) 1061 { 1062 if (cmd == PUC_CFG_GET_ILR) { 1063 *res = PUC_ILR_DIGI; 1064 return (0); 1065 } 1066 return (ENXIO); 1067 } 1068 1069 static int 1070 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1071 intptr_t *res) 1072 { 1073 const struct puc_cfg *cfg = sc->sc_cfg; 1074 struct puc_bar *bar; 1075 uint8_t v0, v1; 1076 1077 switch (cmd) { 1078 case PUC_CFG_SETUP: 1079 /* 1080 * Check if the scratchpad register is enabled or if the 1081 * interrupt status and options registers are active. 1082 */ 1083 bar = puc_get_bar(sc, cfg->rid); 1084 if (bar == NULL) 1085 return (ENXIO); 1086 /* Set DLAB in the LCR register of UART 0. */ 1087 bus_write_1(bar->b_res, 3, 0x80); 1088 /* Write 0 to the SPR register of UART 0. */ 1089 bus_write_1(bar->b_res, 7, 0); 1090 /* Read back the contents of the SPR register of UART 0. */ 1091 v0 = bus_read_1(bar->b_res, 7); 1092 /* Write a specific value to the SPR register of UART 0. */ 1093 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1094 /* Read back the contents of the SPR register of UART 0. */ 1095 v1 = bus_read_1(bar->b_res, 7); 1096 /* Clear DLAB in the LCR register of UART 0. */ 1097 bus_write_1(bar->b_res, 3, 0); 1098 /* Save the two values read-back from the SPR register. */ 1099 sc->sc_cfg_data = (v0 << 8) | v1; 1100 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1101 /* 1102 * The SPR register echoed the two values written 1103 * by us. This means that the SPAD jumper is set. 1104 */ 1105 device_printf(sc->sc_dev, "warning: extra features " 1106 "not usable -- SPAD compatibility enabled\n"); 1107 return (0); 1108 } 1109 if (v0 != 0) { 1110 /* 1111 * The first value doesn't match. This can only mean 1112 * that the SPAD jumper is not set and that a non- 1113 * standard fixed clock multiplier jumper is set. 1114 */ 1115 if (bootverbose) 1116 device_printf(sc->sc_dev, "fixed clock rate " 1117 "multiplier of %d\n", 1 << v0); 1118 if (v0 < -cfg->clock) 1119 device_printf(sc->sc_dev, "warning: " 1120 "suboptimal fixed clock rate multiplier " 1121 "setting\n"); 1122 return (0); 1123 } 1124 /* 1125 * The first value matched, but the second didn't. We know 1126 * that the SPAD jumper is not set. We also know that the 1127 * clock rate multiplier is software controlled *and* that 1128 * we just programmed it to the maximum allowed. 1129 */ 1130 if (bootverbose) 1131 device_printf(sc->sc_dev, "clock rate multiplier of " 1132 "%d selected\n", 1 << -cfg->clock); 1133 return (0); 1134 case PUC_CFG_GET_CLOCK: 1135 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1136 v1 = sc->sc_cfg_data & 0xff; 1137 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1138 /* 1139 * XXX With the SPAD jumper applied, there's no 1140 * easy way of knowing if there's also a clock 1141 * rate multiplier jumper installed. Let's hope 1142 * not... 1143 */ 1144 *res = DEFAULT_RCLK; 1145 } else if (v0 == 0) { 1146 /* 1147 * No clock rate multiplier jumper installed, 1148 * so we programmed the board with the maximum 1149 * multiplier allowed as given to us in the 1150 * clock field of the config record (negated). 1151 */ 1152 *res = DEFAULT_RCLK << -cfg->clock; 1153 } else 1154 *res = DEFAULT_RCLK << v0; 1155 return (0); 1156 case PUC_CFG_GET_ILR: 1157 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1158 v1 = sc->sc_cfg_data & 0xff; 1159 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1160 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1161 return (0); 1162 default: 1163 break; 1164 } 1165 return (ENXIO); 1166 } 1167 1168 static int 1169 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1170 intptr_t *res) 1171 { 1172 static int base[] = { 0x251, 0x3f0, 0 }; 1173 const struct puc_cfg *cfg = sc->sc_cfg; 1174 struct puc_bar *bar; 1175 int efir, idx, ofs; 1176 uint8_t v; 1177 1178 switch (cmd) { 1179 case PUC_CFG_SETUP: 1180 bar = puc_get_bar(sc, cfg->rid); 1181 if (bar == NULL) 1182 return (ENXIO); 1183 1184 /* configure both W83877TFs */ 1185 bus_write_1(bar->b_res, 0x250, 0x89); 1186 bus_write_1(bar->b_res, 0x3f0, 0x87); 1187 bus_write_1(bar->b_res, 0x3f0, 0x87); 1188 idx = 0; 1189 while (base[idx] != 0) { 1190 efir = base[idx]; 1191 bus_write_1(bar->b_res, efir, 0x09); 1192 v = bus_read_1(bar->b_res, efir + 1); 1193 if ((v & 0x0f) != 0x0c) 1194 return (ENXIO); 1195 bus_write_1(bar->b_res, efir, 0x16); 1196 v = bus_read_1(bar->b_res, efir + 1); 1197 bus_write_1(bar->b_res, efir, 0x16); 1198 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1199 bus_write_1(bar->b_res, efir, 0x16); 1200 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1201 ofs = base[idx] & 0x300; 1202 bus_write_1(bar->b_res, efir, 0x23); 1203 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1204 bus_write_1(bar->b_res, efir, 0x24); 1205 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1206 bus_write_1(bar->b_res, efir, 0x25); 1207 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1208 bus_write_1(bar->b_res, efir, 0x17); 1209 bus_write_1(bar->b_res, efir + 1, 0x03); 1210 bus_write_1(bar->b_res, efir, 0x28); 1211 bus_write_1(bar->b_res, efir + 1, 0x43); 1212 idx++; 1213 } 1214 bus_write_1(bar->b_res, 0x250, 0xaa); 1215 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1216 return (0); 1217 case PUC_CFG_GET_OFS: 1218 switch (port) { 1219 case 0: 1220 *res = 0x2f8; 1221 return (0); 1222 case 1: 1223 *res = 0x2e8; 1224 return (0); 1225 case 2: 1226 *res = 0x3f8; 1227 return (0); 1228 case 3: 1229 *res = 0x3e8; 1230 return (0); 1231 case 4: 1232 *res = 0x278; 1233 return (0); 1234 } 1235 break; 1236 default: 1237 break; 1238 } 1239 return (ENXIO); 1240 } 1241 1242 static int 1243 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1244 intptr_t *res) 1245 { 1246 const struct puc_cfg *cfg = sc->sc_cfg; 1247 1248 switch (cmd) { 1249 case PUC_CFG_GET_OFS: 1250 if (cfg->ports == PUC_PORT_8S) { 1251 *res = (port > 4) ? 8 * (port - 4) : 0; 1252 return (0); 1253 } 1254 break; 1255 case PUC_CFG_GET_RID: 1256 if (cfg->ports == PUC_PORT_8S) { 1257 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1258 return (0); 1259 } 1260 if (cfg->ports == PUC_PORT_2S1P) { 1261 switch (port) { 1262 case 0: *res = 0x10; return (0); 1263 case 1: *res = 0x14; return (0); 1264 case 2: *res = 0x1c; return (0); 1265 } 1266 } 1267 break; 1268 default: 1269 break; 1270 } 1271 return (ENXIO); 1272 } 1273 1274 static int 1275 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1276 intptr_t *res) 1277 { 1278 static uint16_t dual[] = { 1279 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1280 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1281 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1282 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1283 0xD079, 0 1284 }; 1285 static uint16_t quad[] = { 1286 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1287 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1288 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1289 0xB157, 0 1290 }; 1291 static uint16_t octa[] = { 1292 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1293 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1294 }; 1295 static struct { 1296 int ports; 1297 uint16_t *ids; 1298 } subdevs[] = { 1299 { 2, dual }, 1300 { 4, quad }, 1301 { 8, octa }, 1302 { 0, NULL } 1303 }; 1304 static char desc[64]; 1305 int dev, id; 1306 uint16_t subdev; 1307 1308 switch (cmd) { 1309 case PUC_CFG_GET_CLOCK: 1310 if (port < 2) 1311 *res = DEFAULT_RCLK * 8; 1312 else 1313 *res = DEFAULT_RCLK; 1314 return (0); 1315 case PUC_CFG_GET_DESC: 1316 snprintf(desc, sizeof(desc), 1317 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1318 *res = (intptr_t)desc; 1319 return (0); 1320 case PUC_CFG_GET_NPORTS: 1321 subdev = pci_get_subdevice(sc->sc_dev); 1322 dev = 0; 1323 while (subdevs[dev].ports != 0) { 1324 id = 0; 1325 while (subdevs[dev].ids[id] != 0) { 1326 if (subdev == subdevs[dev].ids[id]) { 1327 sc->sc_cfg_data = subdevs[dev].ports; 1328 *res = sc->sc_cfg_data; 1329 return (0); 1330 } 1331 id++; 1332 } 1333 dev++; 1334 } 1335 return (ENXIO); 1336 case PUC_CFG_GET_OFS: 1337 *res = (port == 1 || port == 3) ? 8 : 0; 1338 return (0); 1339 case PUC_CFG_GET_RID: 1340 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1341 return (0); 1342 case PUC_CFG_GET_TYPE: 1343 *res = PUC_TYPE_SERIAL; 1344 return (0); 1345 default: 1346 break; 1347 } 1348 return (ENXIO); 1349 } 1350 1351 static int 1352 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1353 intptr_t *res) 1354 { 1355 const struct puc_cfg *cfg = sc->sc_cfg; 1356 int idx; 1357 struct puc_bar *bar; 1358 uint8_t value; 1359 1360 switch (cmd) { 1361 case PUC_CFG_SETUP: 1362 device_printf(sc->sc_dev, "%d UARTs detected\n", 1363 sc->sc_nports); 1364 1365 /* Set UARTs to enhanced mode */ 1366 bar = puc_get_bar(sc, cfg->rid); 1367 if (bar == NULL) 1368 return (ENXIO); 1369 1370 for (idx = 0; idx < sc->sc_nports; idx++) { 1371 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) 1372 + 0x92); 1373 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1374 value | 0x10); 1375 } 1376 1377 return (0); 1378 case PUC_CFG_GET_LEN: 1379 *res = 0x200; 1380 return (0); 1381 case PUC_CFG_GET_NPORTS: 1382 /* 1383 * Check if we are being called from puc_bfe_attach() 1384 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1385 * puc_get_bar(), so we return a value of 16. This has cosmetic 1386 * side-effects at worst; in PUC_CFG_GET_DESC, 1387 * (int)sc->sc_cfg_data will not contain the true number of 1388 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1389 * call for this device family anyway. 1390 * 1391 * The check is for initialisation of sc->sc_bar[idx], which is 1392 * only done in puc_bfe_attach(). 1393 */ 1394 idx = 0; 1395 do { 1396 if (sc->sc_bar[idx++].b_rid != -1) { 1397 sc->sc_cfg_data = 16; 1398 *res = sc->sc_cfg_data; 1399 return (0); 1400 } 1401 } while (idx < PUC_PCI_BARS); 1402 1403 bar = puc_get_bar(sc, cfg->rid); 1404 if (bar == NULL) 1405 return (ENXIO); 1406 1407 value = bus_read_1(bar->b_res, 0x04); 1408 if (value == 0) 1409 return (ENXIO); 1410 1411 sc->sc_cfg_data = value; 1412 *res = sc->sc_cfg_data; 1413 return (0); 1414 case PUC_CFG_GET_OFS: 1415 *res = 0x1000 + (port << 9); 1416 return (0); 1417 case PUC_CFG_GET_TYPE: 1418 *res = PUC_TYPE_SERIAL; 1419 return (0); 1420 default: 1421 break; 1422 } 1423 return (ENXIO); 1424 } 1425 1426 static int 1427 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1428 intptr_t *res) 1429 { 1430 switch (cmd) { 1431 case PUC_CFG_GET_OFS: 1432 *res = (port < 3) ? 0 : (port - 2) << 3; 1433 return (0); 1434 case PUC_CFG_GET_RID: 1435 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1436 return (0); 1437 default: 1438 break; 1439 } 1440 return (ENXIO); 1441 } 1442