1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 45 #include <dev/pci/pcivar.h> 46 47 #include <dev/puc/puc_bus.h> 48 #include <dev/puc/puc_cfg.h> 49 #include <dev/puc/puc_bfe.h> 50 51 static puc_config_f puc_config_amc; 52 static puc_config_f puc_config_diva; 53 static puc_config_f puc_config_exar; 54 static puc_config_f puc_config_exar_pcie; 55 static puc_config_f puc_config_icbook; 56 static puc_config_f puc_config_moxa; 57 static puc_config_f puc_config_oxford_pci954; 58 static puc_config_f puc_config_oxford_pcie; 59 static puc_config_f puc_config_quatech; 60 static puc_config_f puc_config_syba; 61 static puc_config_f puc_config_siig; 62 static puc_config_f puc_config_sunix; 63 static puc_config_f puc_config_timedia; 64 static puc_config_f puc_config_titan; 65 66 const struct puc_cfg puc_pci_devices[] = { 67 68 { 0x0009, 0x7168, 0xffff, 0, 69 "Sunix SUN1889", 70 DEFAULT_RCLK * 8, 71 PUC_PORT_2S, 0x10, 0, 8, 72 }, 73 74 { 0x103c, 0x1048, 0x103c, 0x1049, 75 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 76 DEFAULT_RCLK, 77 PUC_PORT_3S, 0x10, 0, -1, 78 .config_function = puc_config_diva 79 }, 80 81 { 0x103c, 0x1048, 0x103c, 0x104a, 82 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 83 DEFAULT_RCLK, 84 PUC_PORT_2S, 0x10, 0, -1, 85 .config_function = puc_config_diva 86 }, 87 88 { 0x103c, 0x1048, 0x103c, 0x104b, 89 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 90 DEFAULT_RCLK, 91 PUC_PORT_4S, 0x10, 0, -1, 92 .config_function = puc_config_diva 93 }, 94 95 { 0x103c, 0x1048, 0x103c, 0x1223, 96 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 97 DEFAULT_RCLK, 98 PUC_PORT_3S, 0x10, 0, -1, 99 .config_function = puc_config_diva 100 }, 101 102 { 0x103c, 0x1048, 0x103c, 0x1226, 103 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 104 DEFAULT_RCLK, 105 PUC_PORT_3S, 0x10, 0, -1, 106 .config_function = puc_config_diva 107 }, 108 109 { 0x103c, 0x1048, 0x103c, 0x1282, 110 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 111 DEFAULT_RCLK, 112 PUC_PORT_3S, 0x10, 0, -1, 113 .config_function = puc_config_diva 114 }, 115 116 { 0x10b5, 0x1076, 0x10b5, 0x1076, 117 "VScom PCI-800", 118 DEFAULT_RCLK * 8, 119 PUC_PORT_8S, 0x18, 0, 8, 120 }, 121 122 { 0x10b5, 0x1077, 0x10b5, 0x1077, 123 "VScom PCI-400", 124 DEFAULT_RCLK * 8, 125 PUC_PORT_4S, 0x18, 0, 8, 126 }, 127 128 { 0x10b5, 0x1103, 0x10b5, 0x1103, 129 "VScom PCI-200", 130 DEFAULT_RCLK * 8, 131 PUC_PORT_2S, 0x18, 4, 0, 132 }, 133 134 /* 135 * Boca Research Turbo Serial 658 (8 serial port) card. 136 * Appears to be the same as Chase Research PLC PCI-FAST8 137 * and Perle PCI-FAST8 Multi-Port serial cards. 138 */ 139 { 0x10b5, 0x9050, 0x12e0, 0x0021, 140 "Boca Research Turbo Serial 658", 141 DEFAULT_RCLK * 4, 142 PUC_PORT_8S, 0x18, 0, 8, 143 }, 144 145 { 0x10b5, 0x9050, 0x12e0, 0x0031, 146 "Boca Research Turbo Serial 654", 147 DEFAULT_RCLK * 4, 148 PUC_PORT_4S, 0x18, 0, 8, 149 }, 150 151 /* 152 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 153 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 154 * into the subsystem fields, and claims that it's a 155 * network/misc (0x02/0x80) device. 156 */ 157 { 0x10b5, 0x9050, 0xd84d, 0x6808, 158 "Dolphin Peripherals 4035", 159 DEFAULT_RCLK, 160 PUC_PORT_2S, 0x18, 4, 0, 161 }, 162 163 /* 164 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 165 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 166 * into the subsystem fields, and claims that it's a 167 * network/misc (0x02/0x80) device. 168 */ 169 { 0x10b5, 0x9050, 0xd84d, 0x6810, 170 "Dolphin Peripherals 4014", 171 0, 172 PUC_PORT_2P, 0x20, 4, 0, 173 }, 174 175 { 0x10e8, 0x818e, 0xffff, 0, 176 "Applied Micro Circuits 8 Port UART", 177 DEFAULT_RCLK, 178 PUC_PORT_8S, 0x14, -1, -1, 179 .config_function = puc_config_amc 180 }, 181 182 { 0x11fe, 0x8010, 0xffff, 0, 183 "Comtrol RocketPort 550/8 RJ11 part A", 184 DEFAULT_RCLK * 4, 185 PUC_PORT_4S, 0x10, 0, 8, 186 }, 187 188 { 0x11fe, 0x8011, 0xffff, 0, 189 "Comtrol RocketPort 550/8 RJ11 part B", 190 DEFAULT_RCLK * 4, 191 PUC_PORT_4S, 0x10, 0, 8, 192 }, 193 194 { 0x11fe, 0x8012, 0xffff, 0, 195 "Comtrol RocketPort 550/8 Octa part A", 196 DEFAULT_RCLK * 4, 197 PUC_PORT_4S, 0x10, 0, 8, 198 }, 199 200 { 0x11fe, 0x8013, 0xffff, 0, 201 "Comtrol RocketPort 550/8 Octa part B", 202 DEFAULT_RCLK * 4, 203 PUC_PORT_4S, 0x10, 0, 8, 204 }, 205 206 { 0x11fe, 0x8014, 0xffff, 0, 207 "Comtrol RocketPort 550/4 RJ45", 208 DEFAULT_RCLK * 4, 209 PUC_PORT_4S, 0x10, 0, 8, 210 }, 211 212 { 0x11fe, 0x8015, 0xffff, 0, 213 "Comtrol RocketPort 550/Quad", 214 DEFAULT_RCLK * 4, 215 PUC_PORT_4S, 0x10, 0, 8, 216 }, 217 218 { 0x11fe, 0x8016, 0xffff, 0, 219 "Comtrol RocketPort 550/16 part A", 220 DEFAULT_RCLK * 4, 221 PUC_PORT_4S, 0x10, 0, 8, 222 }, 223 224 { 0x11fe, 0x8017, 0xffff, 0, 225 "Comtrol RocketPort 550/16 part B", 226 DEFAULT_RCLK * 4, 227 PUC_PORT_12S, 0x10, 0, 8, 228 }, 229 230 { 0x11fe, 0x8018, 0xffff, 0, 231 "Comtrol RocketPort 550/8 part A", 232 DEFAULT_RCLK * 4, 233 PUC_PORT_4S, 0x10, 0, 8, 234 }, 235 236 { 0x11fe, 0x8019, 0xffff, 0, 237 "Comtrol RocketPort 550/8 part B", 238 DEFAULT_RCLK * 4, 239 PUC_PORT_4S, 0x10, 0, 8, 240 }, 241 242 /* 243 * IBM SurePOS 300 Series (481033H) serial ports 244 * Details can be found on the IBM RSS websites 245 */ 246 247 { 0x1014, 0x0297, 0xffff, 0, 248 "IBM SurePOS 300 Series (481033H) serial ports", 249 DEFAULT_RCLK, 250 PUC_PORT_4S, 0x10, 4, 0 251 }, 252 253 /* 254 * SIIG Boards. 255 * 256 * SIIG provides documentation for their boards at: 257 * <URL:http://www.siig.com/downloads.asp> 258 */ 259 260 { 0x131f, 0x1010, 0xffff, 0, 261 "SIIG Cyber I/O PCI 16C550 (10x family)", 262 DEFAULT_RCLK, 263 PUC_PORT_1S1P, 0x18, 4, 0, 264 }, 265 266 { 0x131f, 0x1011, 0xffff, 0, 267 "SIIG Cyber I/O PCI 16C650 (10x family)", 268 DEFAULT_RCLK, 269 PUC_PORT_1S1P, 0x18, 4, 0, 270 }, 271 272 { 0x131f, 0x1012, 0xffff, 0, 273 "SIIG Cyber I/O PCI 16C850 (10x family)", 274 DEFAULT_RCLK, 275 PUC_PORT_1S1P, 0x18, 4, 0, 276 }, 277 278 { 0x131f, 0x1021, 0xffff, 0, 279 "SIIG Cyber Parallel Dual PCI (10x family)", 280 0, 281 PUC_PORT_2P, 0x18, 8, 0, 282 }, 283 284 { 0x131f, 0x1030, 0xffff, 0, 285 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 286 DEFAULT_RCLK, 287 PUC_PORT_2S, 0x18, 4, 0, 288 }, 289 290 { 0x131f, 0x1031, 0xffff, 0, 291 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 292 DEFAULT_RCLK, 293 PUC_PORT_2S, 0x18, 4, 0, 294 }, 295 296 { 0x131f, 0x1032, 0xffff, 0, 297 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 298 DEFAULT_RCLK, 299 PUC_PORT_2S, 0x18, 4, 0, 300 }, 301 302 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 303 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 304 DEFAULT_RCLK, 305 PUC_PORT_2S1P, 0x18, 4, 0, 306 }, 307 308 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 309 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 310 DEFAULT_RCLK, 311 PUC_PORT_2S1P, 0x18, 4, 0, 312 }, 313 314 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 315 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 316 DEFAULT_RCLK, 317 PUC_PORT_2S1P, 0x18, 4, 0, 318 }, 319 320 { 0x131f, 0x1050, 0xffff, 0, 321 "SIIG Cyber 4S PCI 16C550 (10x family)", 322 DEFAULT_RCLK, 323 PUC_PORT_4S, 0x18, 4, 0, 324 }, 325 326 { 0x131f, 0x1051, 0xffff, 0, 327 "SIIG Cyber 4S PCI 16C650 (10x family)", 328 DEFAULT_RCLK, 329 PUC_PORT_4S, 0x18, 4, 0, 330 }, 331 332 { 0x131f, 0x1052, 0xffff, 0, 333 "SIIG Cyber 4S PCI 16C850 (10x family)", 334 DEFAULT_RCLK, 335 PUC_PORT_4S, 0x18, 4, 0, 336 }, 337 338 { 0x131f, 0x2010, 0xffff, 0, 339 "SIIG Cyber I/O PCI 16C550 (20x family)", 340 DEFAULT_RCLK, 341 PUC_PORT_1S1P, 0x10, 4, 0, 342 }, 343 344 { 0x131f, 0x2011, 0xffff, 0, 345 "SIIG Cyber I/O PCI 16C650 (20x family)", 346 DEFAULT_RCLK, 347 PUC_PORT_1S1P, 0x10, 4, 0, 348 }, 349 350 { 0x131f, 0x2012, 0xffff, 0, 351 "SIIG Cyber I/O PCI 16C850 (20x family)", 352 DEFAULT_RCLK, 353 PUC_PORT_1S1P, 0x10, 4, 0, 354 }, 355 356 { 0x131f, 0x2021, 0xffff, 0, 357 "SIIG Cyber Parallel Dual PCI (20x family)", 358 0, 359 PUC_PORT_2P, 0x10, 8, 0, 360 }, 361 362 { 0x131f, 0x2030, 0xffff, 0, 363 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 364 DEFAULT_RCLK, 365 PUC_PORT_2S, 0x10, 4, 0, 366 }, 367 368 { 0x131f, 0x2031, 0xffff, 0, 369 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 370 DEFAULT_RCLK, 371 PUC_PORT_2S, 0x10, 4, 0, 372 }, 373 374 { 0x131f, 0x2032, 0xffff, 0, 375 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 376 DEFAULT_RCLK, 377 PUC_PORT_2S, 0x10, 4, 0, 378 }, 379 380 { 0x131f, 0x2040, 0xffff, 0, 381 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 382 DEFAULT_RCLK, 383 PUC_PORT_1S2P, 0x10, -1, 0, 384 .config_function = puc_config_siig 385 }, 386 387 { 0x131f, 0x2041, 0xffff, 0, 388 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 389 DEFAULT_RCLK, 390 PUC_PORT_1S2P, 0x10, -1, 0, 391 .config_function = puc_config_siig 392 }, 393 394 { 0x131f, 0x2042, 0xffff, 0, 395 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 396 DEFAULT_RCLK, 397 PUC_PORT_1S2P, 0x10, -1, 0, 398 .config_function = puc_config_siig 399 }, 400 401 { 0x131f, 0x2050, 0xffff, 0, 402 "SIIG Cyber 4S PCI 16C550 (20x family)", 403 DEFAULT_RCLK, 404 PUC_PORT_4S, 0x10, 4, 0, 405 }, 406 407 { 0x131f, 0x2051, 0xffff, 0, 408 "SIIG Cyber 4S PCI 16C650 (20x family)", 409 DEFAULT_RCLK, 410 PUC_PORT_4S, 0x10, 4, 0, 411 }, 412 413 { 0x131f, 0x2052, 0xffff, 0, 414 "SIIG Cyber 4S PCI 16C850 (20x family)", 415 DEFAULT_RCLK, 416 PUC_PORT_4S, 0x10, 4, 0, 417 }, 418 419 { 0x131f, 0x2060, 0xffff, 0, 420 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 421 DEFAULT_RCLK, 422 PUC_PORT_2S1P, 0x10, 4, 0, 423 }, 424 425 { 0x131f, 0x2061, 0xffff, 0, 426 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 427 DEFAULT_RCLK, 428 PUC_PORT_2S1P, 0x10, 4, 0, 429 }, 430 431 { 0x131f, 0x2062, 0xffff, 0, 432 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 433 DEFAULT_RCLK, 434 PUC_PORT_2S1P, 0x10, 4, 0, 435 }, 436 437 { 0x131f, 0x2081, 0xffff, 0, 438 "SIIG PS8000 8S PCI 16C650 (20x family)", 439 DEFAULT_RCLK, 440 PUC_PORT_8S, 0x10, -1, -1, 441 .config_function = puc_config_siig 442 }, 443 444 { 0x135c, 0x0010, 0xffff, 0, 445 "Quatech QSC-100", 446 -3, /* max 8x clock rate */ 447 PUC_PORT_4S, 0x14, 0, 8, 448 .config_function = puc_config_quatech 449 }, 450 451 { 0x135c, 0x0020, 0xffff, 0, 452 "Quatech DSC-100", 453 -1, /* max 2x clock rate */ 454 PUC_PORT_2S, 0x14, 0, 8, 455 .config_function = puc_config_quatech 456 }, 457 458 { 0x135c, 0x0030, 0xffff, 0, 459 "Quatech DSC-200/300", 460 -1, /* max 2x clock rate */ 461 PUC_PORT_2S, 0x14, 0, 8, 462 .config_function = puc_config_quatech 463 }, 464 465 { 0x135c, 0x0040, 0xffff, 0, 466 "Quatech QSC-200/300", 467 -3, /* max 8x clock rate */ 468 PUC_PORT_4S, 0x14, 0, 8, 469 .config_function = puc_config_quatech 470 }, 471 472 { 0x135c, 0x0050, 0xffff, 0, 473 "Quatech ESC-100D", 474 -3, /* max 8x clock rate */ 475 PUC_PORT_8S, 0x14, 0, 8, 476 .config_function = puc_config_quatech 477 }, 478 479 { 0x135c, 0x0060, 0xffff, 0, 480 "Quatech ESC-100M", 481 -3, /* max 8x clock rate */ 482 PUC_PORT_8S, 0x14, 0, 8, 483 .config_function = puc_config_quatech 484 }, 485 486 { 0x135c, 0x0170, 0xffff, 0, 487 "Quatech QSCLP-100", 488 -1, /* max 2x clock rate */ 489 PUC_PORT_4S, 0x18, 0, 8, 490 .config_function = puc_config_quatech 491 }, 492 493 { 0x135c, 0x0180, 0xffff, 0, 494 "Quatech DSCLP-100", 495 -1, /* max 3x clock rate */ 496 PUC_PORT_2S, 0x18, 0, 8, 497 .config_function = puc_config_quatech 498 }, 499 500 { 0x135c, 0x01b0, 0xffff, 0, 501 "Quatech DSCLP-200/300", 502 -1, /* max 2x clock rate */ 503 PUC_PORT_2S, 0x18, 0, 8, 504 .config_function = puc_config_quatech 505 }, 506 507 { 0x135c, 0x01e0, 0xffff, 0, 508 "Quatech ESCLP-100", 509 -3, /* max 8x clock rate */ 510 PUC_PORT_8S, 0x10, 0, 8, 511 .config_function = puc_config_quatech 512 }, 513 514 { 0x1393, 0x1024, 0xffff, 0, 515 "Moxa Technologies, Smartio CP-102E/PCIe", 516 DEFAULT_RCLK * 8, 517 PUC_PORT_2S, 0x14, 0, -1, 518 .config_function = puc_config_moxa 519 }, 520 521 { 0x1393, 0x1025, 0xffff, 0, 522 "Moxa Technologies, Smartio CP-102EL/PCIe", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_2S, 0x14, 0, -1, 525 .config_function = puc_config_moxa 526 }, 527 528 { 0x1393, 0x1040, 0xffff, 0, 529 "Moxa Technologies, Smartio C104H/PCI", 530 DEFAULT_RCLK * 8, 531 PUC_PORT_4S, 0x18, 0, 8, 532 }, 533 534 { 0x1393, 0x1041, 0xffff, 0, 535 "Moxa Technologies, Smartio CP-104UL/PCI", 536 DEFAULT_RCLK * 8, 537 PUC_PORT_4S, 0x18, 0, 8, 538 }, 539 540 { 0x1393, 0x1042, 0xffff, 0, 541 "Moxa Technologies, Smartio CP-104JU/PCI", 542 DEFAULT_RCLK * 8, 543 PUC_PORT_4S, 0x18, 0, 8, 544 }, 545 546 { 0x1393, 0x1043, 0xffff, 0, 547 "Moxa Technologies, Smartio CP-104EL/PCIe", 548 DEFAULT_RCLK * 8, 549 PUC_PORT_4S, 0x18, 0, 8, 550 }, 551 552 { 0x1393, 0x1045, 0xffff, 0, 553 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 554 DEFAULT_RCLK * 8, 555 PUC_PORT_4S, 0x14, 0, -1, 556 .config_function = puc_config_moxa 557 }, 558 559 { 0x1393, 0x1120, 0xffff, 0, 560 "Moxa Technologies, CP-112UL", 561 DEFAULT_RCLK * 8, 562 PUC_PORT_2S, 0x18, 0, 8, 563 }, 564 565 { 0x1393, 0x1141, 0xffff, 0, 566 "Moxa Technologies, Industio CP-114", 567 DEFAULT_RCLK * 8, 568 PUC_PORT_4S, 0x18, 0, 8, 569 }, 570 571 { 0x1393, 0x1144, 0xffff, 0, 572 "Moxa Technologies, Smartio CP-114EL/PCIe", 573 DEFAULT_RCLK * 8, 574 PUC_PORT_4S, 0x14, 0, -1, 575 .config_function = puc_config_moxa 576 }, 577 578 { 0x1393, 0x1182, 0xffff, 0, 579 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 580 DEFAULT_RCLK * 8, 581 PUC_PORT_8S, 0x14, 0, -1, 582 .config_function = puc_config_moxa 583 }, 584 585 { 0x1393, 0x1680, 0xffff, 0, 586 "Moxa Technologies, C168H/PCI", 587 DEFAULT_RCLK * 8, 588 PUC_PORT_8S, 0x18, 0, 8, 589 }, 590 591 { 0x1393, 0x1681, 0xffff, 0, 592 "Moxa Technologies, C168U/PCI", 593 DEFAULT_RCLK * 8, 594 PUC_PORT_8S, 0x18, 0, 8, 595 }, 596 597 { 0x1393, 0x1682, 0xffff, 0, 598 "Moxa Technologies, CP-168EL/PCIe", 599 DEFAULT_RCLK * 8, 600 PUC_PORT_8S, 0x18, 0, 8, 601 }, 602 603 { 0x1393, 0x1683, 0xffff, 0, 604 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 605 DEFAULT_RCLK * 8, 606 PUC_PORT_8S, 0x14, 0, -1, 607 .config_function = puc_config_moxa 608 }, 609 610 { 0x13a8, 0x0152, 0xffff, 0, 611 "Exar XR17C/D152", 612 DEFAULT_RCLK * 8, 613 PUC_PORT_2S, 0x10, 0, -1, 614 .config_function = puc_config_exar 615 }, 616 617 { 0x13a8, 0x0154, 0xffff, 0, 618 "Exar XR17C154", 619 DEFAULT_RCLK * 8, 620 PUC_PORT_4S, 0x10, 0, -1, 621 .config_function = puc_config_exar 622 }, 623 624 { 0x13a8, 0x0158, 0xffff, 0, 625 "Exar XR17C158", 626 DEFAULT_RCLK * 8, 627 PUC_PORT_8S, 0x10, 0, -1, 628 .config_function = puc_config_exar 629 }, 630 631 { 0x13a8, 0x0258, 0xffff, 0, 632 "Exar XR17V258IV", 633 DEFAULT_RCLK * 8, 634 PUC_PORT_8S, 0x10, 0, -1, 635 .config_function = puc_config_exar 636 }, 637 638 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 639 { 0x13a8, 0x0358, 0xffff, 0, 640 "Exar XR17V358", 641 125000000, 642 PUC_PORT_8S, 0x10, 0, -1, 643 .config_function = puc_config_exar_pcie 644 }, 645 646 { 0x13fe, 0x1600, 0x1602, 0x0002, 647 "Advantech PCI-1602", 648 DEFAULT_RCLK * 8, 649 PUC_PORT_2S, 0x10, 0, 8, 650 }, 651 652 { 0x1407, 0x0100, 0xffff, 0, 653 "Lava Computers Dual Serial", 654 DEFAULT_RCLK, 655 PUC_PORT_2S, 0x10, 4, 0, 656 }, 657 658 { 0x1407, 0x0101, 0xffff, 0, 659 "Lava Computers Quatro A", 660 DEFAULT_RCLK, 661 PUC_PORT_2S, 0x10, 4, 0, 662 }, 663 664 { 0x1407, 0x0102, 0xffff, 0, 665 "Lava Computers Quatro B", 666 DEFAULT_RCLK, 667 PUC_PORT_2S, 0x10, 4, 0, 668 }, 669 670 { 0x1407, 0x0120, 0xffff, 0, 671 "Lava Computers Quattro-PCI A", 672 DEFAULT_RCLK, 673 PUC_PORT_2S, 0x10, 4, 0, 674 }, 675 676 { 0x1407, 0x0121, 0xffff, 0, 677 "Lava Computers Quattro-PCI B", 678 DEFAULT_RCLK, 679 PUC_PORT_2S, 0x10, 4, 0, 680 }, 681 682 { 0x1407, 0x0180, 0xffff, 0, 683 "Lava Computers Octo A", 684 DEFAULT_RCLK, 685 PUC_PORT_4S, 0x10, 4, 0, 686 }, 687 688 { 0x1407, 0x0181, 0xffff, 0, 689 "Lava Computers Octo B", 690 DEFAULT_RCLK, 691 PUC_PORT_4S, 0x10, 4, 0, 692 }, 693 694 { 0x1409, 0x7268, 0xffff, 0, 695 "Sunix SUN1888", 696 0, 697 PUC_PORT_2P, 0x10, 0, 8, 698 }, 699 700 { 0x1409, 0x7168, 0xffff, 0, 701 NULL, 702 DEFAULT_RCLK * 8, 703 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 704 .config_function = puc_config_timedia 705 }, 706 707 /* 708 * Boards with an Oxford Semiconductor chip. 709 * 710 * Oxford Semiconductor provides documentation for their chip at: 711 * <URL:http://www.plxtech.com/products/uart/> 712 * 713 * As sold by Kouwell <URL:http://www.kouwell.com/>. 714 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 715 */ 716 { 717 0x1415, 0x9501, 0x10fc, 0xc070, 718 "I-O DATA RSA-PCI2/R", 719 DEFAULT_RCLK * 8, 720 PUC_PORT_2S, 0x10, 0, 8, 721 }, 722 723 { 0x1415, 0x9501, 0x131f, 0x2050, 724 "SIIG Cyber 4 PCI 16550", 725 DEFAULT_RCLK * 10, 726 PUC_PORT_4S, 0x10, 0, 8, 727 }, 728 729 { 0x1415, 0x9501, 0x131f, 0x2051, 730 "SIIG Cyber 4S PCI 16C650 (20x family)", 731 DEFAULT_RCLK * 10, 732 PUC_PORT_4S, 0x10, 0, 8, 733 }, 734 735 { 0x1415, 0x9501, 0x131f, 0x2052, 736 "SIIG Quartet Serial 850", 737 DEFAULT_RCLK * 10, 738 PUC_PORT_4S, 0x10, 0, 8, 739 }, 740 741 { 0x1415, 0x9501, 0x14db, 0x2150, 742 "Kuroutoshikou SERIAL4P-LPPCI2", 743 DEFAULT_RCLK * 10, 744 PUC_PORT_4S, 0x10, 0, 8, 745 }, 746 747 { 0x1415, 0x9501, 0xffff, 0, 748 "Oxford Semiconductor OX16PCI954 UARTs", 749 0, 750 PUC_PORT_4S, 0x10, 0, 8, 751 .config_function = puc_config_oxford_pci954 752 }, 753 754 { 0x1415, 0x950a, 0x131f, 0x2030, 755 "SIIG Cyber 2S PCIe", 756 DEFAULT_RCLK * 10, 757 PUC_PORT_2S, 0x10, 0, 8, 758 }, 759 760 { 0x1415, 0x950a, 0x131f, 0x2032, 761 "SIIG Cyber Serial Dual PCI 16C850", 762 DEFAULT_RCLK * 10, 763 PUC_PORT_4S, 0x10, 0, 8, 764 }, 765 766 { 0x1415, 0x950a, 0xffff, 0, 767 "Oxford Semiconductor OX16PCI954 UARTs", 768 DEFAULT_RCLK, 769 PUC_PORT_4S, 0x10, 0, 8, 770 }, 771 772 { 0x1415, 0x9511, 0xffff, 0, 773 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 774 DEFAULT_RCLK, 775 PUC_PORT_4S, 0x10, 0, 8, 776 }, 777 778 { 0x1415, 0x9521, 0xffff, 0, 779 "Oxford Semiconductor OX16PCI952 UARTs", 780 DEFAULT_RCLK, 781 PUC_PORT_2S, 0x10, 4, 0, 782 }, 783 784 { 0x1415, 0x9538, 0xffff, 0, 785 "Oxford Semiconductor OX16PCI958 UARTs", 786 DEFAULT_RCLK, 787 PUC_PORT_8S, 0x18, 0, 8, 788 }, 789 790 /* 791 * Perle boards use Oxford Semiconductor chips, but they store the 792 * Oxford Semiconductor device ID as a subvendor device ID and use 793 * their own device IDs. 794 */ 795 796 { 0x155f, 0x0331, 0xffff, 0, 797 "Perle Ultraport4 Express", 798 DEFAULT_RCLK * 8, 799 PUC_PORT_4S, 0x10, 0, 8, 800 }, 801 802 { 0x155f, 0xB012, 0xffff, 0, 803 "Perle Speed2 LE", 804 DEFAULT_RCLK * 8, 805 PUC_PORT_2S, 0x10, 0, 8, 806 }, 807 808 { 0x155f, 0xB022, 0xffff, 0, 809 "Perle Speed2 LE", 810 DEFAULT_RCLK * 8, 811 PUC_PORT_2S, 0x10, 0, 8, 812 }, 813 814 { 0x155f, 0xB004, 0xffff, 0, 815 "Perle Speed4 LE", 816 DEFAULT_RCLK * 8, 817 PUC_PORT_4S, 0x10, 0, 8, 818 }, 819 820 { 0x155f, 0xB008, 0xffff, 0, 821 "Perle Speed8 LE", 822 DEFAULT_RCLK * 8, 823 PUC_PORT_8S, 0x10, 0, 8, 824 }, 825 826 827 /* 828 * Oxford Semiconductor PCI Express Expresso family 829 * 830 * Found in many 'native' PCI Express serial boards such as: 831 * 832 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 833 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 834 * 835 * Lindy 51189 (4 port) 836 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 837 * 838 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 839 * <URL:http://www.startech.com> 840 */ 841 842 { 0x1415, 0xc138, 0xffff, 0, 843 "Oxford Semiconductor OXPCIe952 UARTs", 844 DEFAULT_RCLK * 0x22, 845 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 846 .config_function = puc_config_oxford_pcie 847 }, 848 849 { 0x1415, 0xc158, 0xffff, 0, 850 "Oxford Semiconductor OXPCIe952 UARTs", 851 DEFAULT_RCLK * 0x22, 852 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 853 .config_function = puc_config_oxford_pcie 854 }, 855 856 { 0x1415, 0xc15d, 0xffff, 0, 857 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 858 DEFAULT_RCLK * 0x22, 859 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 860 .config_function = puc_config_oxford_pcie 861 }, 862 863 { 0x1415, 0xc208, 0xffff, 0, 864 "Oxford Semiconductor OXPCIe954 UARTs", 865 DEFAULT_RCLK * 0x22, 866 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 867 .config_function = puc_config_oxford_pcie 868 }, 869 870 { 0x1415, 0xc20d, 0xffff, 0, 871 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 872 DEFAULT_RCLK * 0x22, 873 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 874 .config_function = puc_config_oxford_pcie 875 }, 876 877 { 0x1415, 0xc308, 0xffff, 0, 878 "Oxford Semiconductor OXPCIe958 UARTs", 879 DEFAULT_RCLK * 0x22, 880 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 881 .config_function = puc_config_oxford_pcie 882 }, 883 884 { 0x1415, 0xc30d, 0xffff, 0, 885 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 886 DEFAULT_RCLK * 0x22, 887 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 888 .config_function = puc_config_oxford_pcie 889 }, 890 891 { 0x14d2, 0x8010, 0xffff, 0, 892 "VScom PCI-100L", 893 DEFAULT_RCLK * 8, 894 PUC_PORT_1S, 0x14, 0, 0, 895 }, 896 897 { 0x14d2, 0x8020, 0xffff, 0, 898 "VScom PCI-200L", 899 DEFAULT_RCLK * 8, 900 PUC_PORT_2S, 0x14, 4, 0, 901 }, 902 903 { 0x14d2, 0x8028, 0xffff, 0, 904 "VScom 200Li", 905 DEFAULT_RCLK, 906 PUC_PORT_2S, 0x20, 0, 8, 907 }, 908 909 /* 910 * VScom (Titan?) PCI-800L. More modern variant of the 911 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 912 * two of them obviously implemented as macro cells in 913 * the ASIC. This causes the weird port access pattern 914 * below, where two of the IO port ranges each access 915 * one of the ASIC UARTs, and a block of IO addresses 916 * access the external UARTs. 917 */ 918 { 0x14d2, 0x8080, 0xffff, 0, 919 "Titan VScom PCI-800L", 920 DEFAULT_RCLK * 8, 921 PUC_PORT_8S, 0x14, -1, -1, 922 .config_function = puc_config_titan 923 }, 924 925 /* 926 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 927 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 928 * device ID 3 and PCI device 1 device ID 4. 929 */ 930 { 0x14d2, 0xa003, 0xffff, 0, 931 "Titan PCI-800H", 932 DEFAULT_RCLK * 8, 933 PUC_PORT_4S, 0x10, 0, 8, 934 }, 935 936 { 0x14d2, 0xa004, 0xffff, 0, 937 "Titan PCI-800H", 938 DEFAULT_RCLK * 8, 939 PUC_PORT_4S, 0x10, 0, 8, 940 }, 941 942 { 0x14d2, 0xa005, 0xffff, 0, 943 "Titan PCI-200H", 944 DEFAULT_RCLK * 8, 945 PUC_PORT_2S, 0x10, 0, 8, 946 }, 947 948 { 0x14d2, 0xe020, 0xffff, 0, 949 "Titan VScom PCI-200HV2", 950 DEFAULT_RCLK * 8, 951 PUC_PORT_2S, 0x10, 4, 0, 952 }, 953 954 { 0x14d2, 0xa007, 0xffff, 0, 955 "Titan VScom PCIex-800H", 956 DEFAULT_RCLK * 8, 957 PUC_PORT_4S, 0x10, 0, 8, 958 }, 959 960 { 0x14d2, 0xa008, 0xffff, 0, 961 "Titan VScom PCIex-800H", 962 DEFAULT_RCLK * 8, 963 PUC_PORT_4S, 0x10, 0, 8, 964 }, 965 966 { 0x14db, 0x2130, 0xffff, 0, 967 "Avlab Technology, PCI IO 2S", 968 DEFAULT_RCLK, 969 PUC_PORT_2S, 0x10, 4, 0, 970 }, 971 972 { 0x14db, 0x2150, 0xffff, 0, 973 "Avlab Low Profile PCI 4 Serial", 974 DEFAULT_RCLK, 975 PUC_PORT_4S, 0x10, 4, 0, 976 }, 977 978 { 0x14db, 0x2152, 0xffff, 0, 979 "Avlab Low Profile PCI 4 Serial", 980 DEFAULT_RCLK, 981 PUC_PORT_4S, 0x10, 4, 0, 982 }, 983 984 { 0x1592, 0x0781, 0xffff, 0, 985 "Syba Tech Ltd. PCI-4S2P-550-ECP", 986 DEFAULT_RCLK, 987 PUC_PORT_4S1P, 0x10, 0, -1, 988 .config_function = puc_config_syba 989 }, 990 991 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 992 "Sunix SER5xxxx 2-port serial", 993 DEFAULT_RCLK * 8, 994 PUC_PORT_2S, 0x10, 0, 8, 995 }, 996 997 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 998 "Sunix SER5xxxx 4-port serial", 999 DEFAULT_RCLK * 8, 1000 PUC_PORT_4S, 0x10, 0, 8, 1001 }, 1002 1003 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1004 "Sunix SER5xxxx 8-port serial", 1005 DEFAULT_RCLK * 8, 1006 PUC_PORT_8S, -1, -1, -1, 1007 .config_function = puc_config_sunix 1008 }, 1009 1010 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1011 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1012 DEFAULT_RCLK * 8, 1013 PUC_PORT_1S1P, -1, -1, -1, 1014 .config_function = puc_config_sunix 1015 }, 1016 1017 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1018 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1019 DEFAULT_RCLK * 8, 1020 PUC_PORT_2S1P, -1, -1, -1, 1021 .config_function = puc_config_sunix 1022 }, 1023 1024 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1025 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1026 DEFAULT_RCLK * 8, 1027 PUC_PORT_4S1P, -1, -1, -1, 1028 .config_function = puc_config_sunix 1029 }, 1030 1031 { 0x5372, 0x6873, 0xffff, 0, 1032 "Sun 1040 PCI Quad Serial", 1033 DEFAULT_RCLK, 1034 PUC_PORT_4S, 0x10, 4, 0, 1035 }, 1036 1037 { 0x6666, 0x0001, 0xffff, 0, 1038 "Decision Computer Inc, PCCOM 4-port serial", 1039 DEFAULT_RCLK, 1040 PUC_PORT_4S, 0x1c, 0, 8, 1041 }, 1042 1043 { 0x6666, 0x0002, 0xffff, 0, 1044 "Decision Computer Inc, PCCOM 8-port serial", 1045 DEFAULT_RCLK, 1046 PUC_PORT_8S, 0x1c, 0, 8, 1047 }, 1048 1049 { 0x6666, 0x0004, 0xffff, 0, 1050 "PCCOM dual port RS232/422/485", 1051 DEFAULT_RCLK, 1052 PUC_PORT_2S, 0x1c, 0, 8, 1053 }, 1054 1055 { 0x9710, 0x9815, 0xffff, 0, 1056 "NetMos NM9815 Dual 1284 Printer port", 1057 0, 1058 PUC_PORT_2P, 0x10, 8, 0, 1059 }, 1060 1061 /* 1062 * This is more specific than the generic NM9835 entry, and is placed 1063 * here to _prevent_ puc(4) from claiming this single port card. 1064 * 1065 * uart(4) will claim this device. 1066 */ 1067 { 0x9710, 0x9835, 0x1000, 1, 1068 "NetMos NM9835 based 1-port serial", 1069 DEFAULT_RCLK, 1070 PUC_PORT_1S, 0x10, 4, 0, 1071 }, 1072 1073 { 0x9710, 0x9835, 0x1000, 2, 1074 "NetMos NM9835 based 2-port serial", 1075 DEFAULT_RCLK, 1076 PUC_PORT_2S, 0x10, 4, 0, 1077 }, 1078 1079 { 0x9710, 0x9835, 0xffff, 0, 1080 "NetMos NM9835 Dual UART and 1284 Printer port", 1081 DEFAULT_RCLK, 1082 PUC_PORT_2S1P, 0x10, 4, 0, 1083 }, 1084 1085 { 0x9710, 0x9845, 0x1000, 0x0006, 1086 "NetMos NM9845 6 Port UART", 1087 DEFAULT_RCLK, 1088 PUC_PORT_6S, 0x10, 4, 0, 1089 }, 1090 1091 { 0x9710, 0x9845, 0xffff, 0, 1092 "NetMos NM9845 Quad UART and 1284 Printer port", 1093 DEFAULT_RCLK, 1094 PUC_PORT_4S1P, 0x10, 4, 0, 1095 }, 1096 1097 { 0x9710, 0x9865, 0xa000, 0x3002, 1098 "NetMos NM9865 Dual UART", 1099 DEFAULT_RCLK, 1100 PUC_PORT_2S, 0x10, 4, 0, 1101 }, 1102 1103 { 0x9710, 0x9865, 0xa000, 0x3003, 1104 "NetMos NM9865 Triple UART", 1105 DEFAULT_RCLK, 1106 PUC_PORT_3S, 0x10, 4, 0, 1107 }, 1108 1109 { 0x9710, 0x9865, 0xa000, 0x3004, 1110 "NetMos NM9865 Quad UART", 1111 DEFAULT_RCLK, 1112 PUC_PORT_4S, 0x10, 4, 0, 1113 }, 1114 1115 { 0x9710, 0x9865, 0xa000, 0x3011, 1116 "NetMos NM9865 Single UART and 1284 Printer port", 1117 DEFAULT_RCLK, 1118 PUC_PORT_1S1P, 0x10, 4, 0, 1119 }, 1120 1121 { 0x9710, 0x9865, 0xa000, 0x3012, 1122 "NetMos NM9865 Dual UART and 1284 Printer port", 1123 DEFAULT_RCLK, 1124 PUC_PORT_2S1P, 0x10, 4, 0, 1125 }, 1126 1127 { 0x9710, 0x9865, 0xa000, 0x3020, 1128 "NetMos NM9865 Dual 1284 Printer port", 1129 DEFAULT_RCLK, 1130 PUC_PORT_2P, 0x10, 4, 0, 1131 }, 1132 1133 { 0xb00c, 0x021c, 0xffff, 0, 1134 "IC Book Labs Gunboat x4 Lite", 1135 DEFAULT_RCLK, 1136 PUC_PORT_4S, 0x10, 0, 8, 1137 .config_function = puc_config_icbook 1138 }, 1139 1140 { 0xb00c, 0x031c, 0xffff, 0, 1141 "IC Book Labs Gunboat x4 Pro", 1142 DEFAULT_RCLK, 1143 PUC_PORT_4S, 0x10, 0, 8, 1144 .config_function = puc_config_icbook 1145 }, 1146 1147 { 0xb00c, 0x041c, 0xffff, 0, 1148 "IC Book Labs Ironclad x8 Lite", 1149 DEFAULT_RCLK, 1150 PUC_PORT_8S, 0x10, 0, 8, 1151 .config_function = puc_config_icbook 1152 }, 1153 1154 { 0xb00c, 0x051c, 0xffff, 0, 1155 "IC Book Labs Ironclad x8 Pro", 1156 DEFAULT_RCLK, 1157 PUC_PORT_8S, 0x10, 0, 8, 1158 .config_function = puc_config_icbook 1159 }, 1160 1161 { 0xb00c, 0x081c, 0xffff, 0, 1162 "IC Book Labs Dreadnought x16 Pro", 1163 DEFAULT_RCLK * 8, 1164 PUC_PORT_16S, 0x10, 0, 8, 1165 .config_function = puc_config_icbook 1166 }, 1167 1168 { 0xb00c, 0x091c, 0xffff, 0, 1169 "IC Book Labs Dreadnought x16 Lite", 1170 DEFAULT_RCLK, 1171 PUC_PORT_16S, 0x10, 0, 8, 1172 .config_function = puc_config_icbook 1173 }, 1174 1175 { 0xb00c, 0x0a1c, 0xffff, 0, 1176 "IC Book Labs Gunboat x2 Low Profile", 1177 DEFAULT_RCLK, 1178 PUC_PORT_2S, 0x10, 0, 8, 1179 }, 1180 1181 { 0xb00c, 0x0b1c, 0xffff, 0, 1182 "IC Book Labs Gunboat x4 Low Profile", 1183 DEFAULT_RCLK, 1184 PUC_PORT_4S, 0x10, 0, 8, 1185 .config_function = puc_config_icbook 1186 }, 1187 1188 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1189 }; 1190 1191 static int 1192 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1193 intptr_t *res) 1194 { 1195 switch (cmd) { 1196 case PUC_CFG_GET_OFS: 1197 *res = 8 * (port & 1); 1198 return (0); 1199 case PUC_CFG_GET_RID: 1200 *res = 0x14 + (port >> 1) * 4; 1201 return (0); 1202 default: 1203 break; 1204 } 1205 return (ENXIO); 1206 } 1207 1208 static int 1209 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1210 intptr_t *res) 1211 { 1212 const struct puc_cfg *cfg = sc->sc_cfg; 1213 1214 if (cmd == PUC_CFG_GET_OFS) { 1215 if (cfg->subdevice == 0x1282) /* Everest SP */ 1216 port <<= 1; 1217 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1218 port = (port == 3) ? 4 : port; 1219 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1220 return (0); 1221 } 1222 return (ENXIO); 1223 } 1224 1225 static int 1226 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1227 intptr_t *res) 1228 { 1229 if (cmd == PUC_CFG_GET_OFS) { 1230 *res = port * 0x200; 1231 return (0); 1232 } 1233 return (ENXIO); 1234 } 1235 1236 static int 1237 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1238 intptr_t *res) 1239 { 1240 if (cmd == PUC_CFG_GET_OFS) { 1241 *res = port * 0x400; 1242 return (0); 1243 } 1244 return (ENXIO); 1245 } 1246 1247 static int 1248 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1249 intptr_t *res) 1250 { 1251 if (cmd == PUC_CFG_GET_ILR) { 1252 *res = PUC_ILR_DIGI; 1253 return (0); 1254 } 1255 return (ENXIO); 1256 } 1257 1258 static int 1259 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1260 intptr_t *res) 1261 { 1262 if (cmd == PUC_CFG_GET_OFS) { 1263 const struct puc_cfg *cfg = sc->sc_cfg; 1264 1265 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144)) 1266 port = 7; 1267 *res = port * 0x200; 1268 1269 return 0; 1270 } 1271 return (ENXIO); 1272 } 1273 1274 static int 1275 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1276 intptr_t *res) 1277 { 1278 const struct puc_cfg *cfg = sc->sc_cfg; 1279 struct puc_bar *bar; 1280 uint8_t v0, v1; 1281 1282 switch (cmd) { 1283 case PUC_CFG_SETUP: 1284 /* 1285 * Check if the scratchpad register is enabled or if the 1286 * interrupt status and options registers are active. 1287 */ 1288 bar = puc_get_bar(sc, cfg->rid); 1289 if (bar == NULL) 1290 return (ENXIO); 1291 /* Set DLAB in the LCR register of UART 0. */ 1292 bus_write_1(bar->b_res, 3, 0x80); 1293 /* Write 0 to the SPR register of UART 0. */ 1294 bus_write_1(bar->b_res, 7, 0); 1295 /* Read back the contents of the SPR register of UART 0. */ 1296 v0 = bus_read_1(bar->b_res, 7); 1297 /* Write a specific value to the SPR register of UART 0. */ 1298 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1299 /* Read back the contents of the SPR register of UART 0. */ 1300 v1 = bus_read_1(bar->b_res, 7); 1301 /* Clear DLAB in the LCR register of UART 0. */ 1302 bus_write_1(bar->b_res, 3, 0); 1303 /* Save the two values read-back from the SPR register. */ 1304 sc->sc_cfg_data = (v0 << 8) | v1; 1305 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1306 /* 1307 * The SPR register echoed the two values written 1308 * by us. This means that the SPAD jumper is set. 1309 */ 1310 device_printf(sc->sc_dev, "warning: extra features " 1311 "not usable -- SPAD compatibility enabled\n"); 1312 return (0); 1313 } 1314 if (v0 != 0) { 1315 /* 1316 * The first value doesn't match. This can only mean 1317 * that the SPAD jumper is not set and that a non- 1318 * standard fixed clock multiplier jumper is set. 1319 */ 1320 if (bootverbose) 1321 device_printf(sc->sc_dev, "fixed clock rate " 1322 "multiplier of %d\n", 1 << v0); 1323 if (v0 < -cfg->clock) 1324 device_printf(sc->sc_dev, "warning: " 1325 "suboptimal fixed clock rate multiplier " 1326 "setting\n"); 1327 return (0); 1328 } 1329 /* 1330 * The first value matched, but the second didn't. We know 1331 * that the SPAD jumper is not set. We also know that the 1332 * clock rate multiplier is software controlled *and* that 1333 * we just programmed it to the maximum allowed. 1334 */ 1335 if (bootverbose) 1336 device_printf(sc->sc_dev, "clock rate multiplier of " 1337 "%d selected\n", 1 << -cfg->clock); 1338 return (0); 1339 case PUC_CFG_GET_CLOCK: 1340 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1341 v1 = sc->sc_cfg_data & 0xff; 1342 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1343 /* 1344 * XXX With the SPAD jumper applied, there's no 1345 * easy way of knowing if there's also a clock 1346 * rate multiplier jumper installed. Let's hope 1347 * not... 1348 */ 1349 *res = DEFAULT_RCLK; 1350 } else if (v0 == 0) { 1351 /* 1352 * No clock rate multiplier jumper installed, 1353 * so we programmed the board with the maximum 1354 * multiplier allowed as given to us in the 1355 * clock field of the config record (negated). 1356 */ 1357 *res = DEFAULT_RCLK << -cfg->clock; 1358 } else 1359 *res = DEFAULT_RCLK << v0; 1360 return (0); 1361 case PUC_CFG_GET_ILR: 1362 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1363 v1 = sc->sc_cfg_data & 0xff; 1364 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1365 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1366 return (0); 1367 default: 1368 break; 1369 } 1370 return (ENXIO); 1371 } 1372 1373 static int 1374 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1375 intptr_t *res) 1376 { 1377 static int base[] = { 0x251, 0x3f0, 0 }; 1378 const struct puc_cfg *cfg = sc->sc_cfg; 1379 struct puc_bar *bar; 1380 int efir, idx, ofs; 1381 uint8_t v; 1382 1383 switch (cmd) { 1384 case PUC_CFG_SETUP: 1385 bar = puc_get_bar(sc, cfg->rid); 1386 if (bar == NULL) 1387 return (ENXIO); 1388 1389 /* configure both W83877TFs */ 1390 bus_write_1(bar->b_res, 0x250, 0x89); 1391 bus_write_1(bar->b_res, 0x3f0, 0x87); 1392 bus_write_1(bar->b_res, 0x3f0, 0x87); 1393 idx = 0; 1394 while (base[idx] != 0) { 1395 efir = base[idx]; 1396 bus_write_1(bar->b_res, efir, 0x09); 1397 v = bus_read_1(bar->b_res, efir + 1); 1398 if ((v & 0x0f) != 0x0c) 1399 return (ENXIO); 1400 bus_write_1(bar->b_res, efir, 0x16); 1401 v = bus_read_1(bar->b_res, efir + 1); 1402 bus_write_1(bar->b_res, efir, 0x16); 1403 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1404 bus_write_1(bar->b_res, efir, 0x16); 1405 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1406 ofs = base[idx] & 0x300; 1407 bus_write_1(bar->b_res, efir, 0x23); 1408 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1409 bus_write_1(bar->b_res, efir, 0x24); 1410 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1411 bus_write_1(bar->b_res, efir, 0x25); 1412 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1413 bus_write_1(bar->b_res, efir, 0x17); 1414 bus_write_1(bar->b_res, efir + 1, 0x03); 1415 bus_write_1(bar->b_res, efir, 0x28); 1416 bus_write_1(bar->b_res, efir + 1, 0x43); 1417 idx++; 1418 } 1419 bus_write_1(bar->b_res, 0x250, 0xaa); 1420 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1421 return (0); 1422 case PUC_CFG_GET_OFS: 1423 switch (port) { 1424 case 0: 1425 *res = 0x2f8; 1426 return (0); 1427 case 1: 1428 *res = 0x2e8; 1429 return (0); 1430 case 2: 1431 *res = 0x3f8; 1432 return (0); 1433 case 3: 1434 *res = 0x3e8; 1435 return (0); 1436 case 4: 1437 *res = 0x278; 1438 return (0); 1439 } 1440 break; 1441 default: 1442 break; 1443 } 1444 return (ENXIO); 1445 } 1446 1447 static int 1448 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1449 intptr_t *res) 1450 { 1451 const struct puc_cfg *cfg = sc->sc_cfg; 1452 1453 switch (cmd) { 1454 case PUC_CFG_GET_OFS: 1455 if (cfg->ports == PUC_PORT_8S) { 1456 *res = (port > 4) ? 8 * (port - 4) : 0; 1457 return (0); 1458 } 1459 break; 1460 case PUC_CFG_GET_RID: 1461 if (cfg->ports == PUC_PORT_8S) { 1462 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1463 return (0); 1464 } 1465 if (cfg->ports == PUC_PORT_2S1P) { 1466 switch (port) { 1467 case 0: *res = 0x10; return (0); 1468 case 1: *res = 0x14; return (0); 1469 case 2: *res = 0x1c; return (0); 1470 } 1471 } 1472 break; 1473 default: 1474 break; 1475 } 1476 return (ENXIO); 1477 } 1478 1479 static int 1480 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1481 intptr_t *res) 1482 { 1483 static const uint16_t dual[] = { 1484 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1485 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1486 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1487 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1488 0xD079, 0 1489 }; 1490 static const uint16_t quad[] = { 1491 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1492 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1493 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1494 0xB157, 0 1495 }; 1496 static const uint16_t octa[] = { 1497 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1498 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1499 }; 1500 static const struct { 1501 int ports; 1502 const uint16_t *ids; 1503 } subdevs[] = { 1504 { 2, dual }, 1505 { 4, quad }, 1506 { 8, octa }, 1507 { 0, NULL } 1508 }; 1509 static char desc[64]; 1510 int dev, id; 1511 uint16_t subdev; 1512 1513 switch (cmd) { 1514 case PUC_CFG_GET_CLOCK: 1515 if (port < 2) 1516 *res = DEFAULT_RCLK * 8; 1517 else 1518 *res = DEFAULT_RCLK; 1519 return (0); 1520 case PUC_CFG_GET_DESC: 1521 snprintf(desc, sizeof(desc), 1522 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1523 *res = (intptr_t)desc; 1524 return (0); 1525 case PUC_CFG_GET_NPORTS: 1526 subdev = pci_get_subdevice(sc->sc_dev); 1527 dev = 0; 1528 while (subdevs[dev].ports != 0) { 1529 id = 0; 1530 while (subdevs[dev].ids[id] != 0) { 1531 if (subdev == subdevs[dev].ids[id]) { 1532 sc->sc_cfg_data = subdevs[dev].ports; 1533 *res = sc->sc_cfg_data; 1534 return (0); 1535 } 1536 id++; 1537 } 1538 dev++; 1539 } 1540 return (ENXIO); 1541 case PUC_CFG_GET_OFS: 1542 *res = (port == 1 || port == 3) ? 8 : 0; 1543 return (0); 1544 case PUC_CFG_GET_RID: 1545 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1546 return (0); 1547 case PUC_CFG_GET_TYPE: 1548 *res = PUC_TYPE_SERIAL; 1549 return (0); 1550 default: 1551 break; 1552 } 1553 return (ENXIO); 1554 } 1555 1556 static int 1557 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1558 int port __unused, intptr_t *res) 1559 { 1560 1561 switch (cmd) { 1562 case PUC_CFG_GET_CLOCK: 1563 /* 1564 * OXu16PCI954 use a 14.7456 MHz clock by default while 1565 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1566 */ 1567 if (pci_get_revid(sc->sc_dev) == 1) 1568 *res = DEFAULT_RCLK * 8; 1569 else 1570 *res = DEFAULT_RCLK; 1571 return (0); 1572 default: 1573 break; 1574 } 1575 return (ENXIO); 1576 } 1577 1578 static int 1579 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1580 intptr_t *res) 1581 { 1582 const struct puc_cfg *cfg = sc->sc_cfg; 1583 int idx; 1584 struct puc_bar *bar; 1585 uint8_t value; 1586 1587 switch (cmd) { 1588 case PUC_CFG_SETUP: 1589 device_printf(sc->sc_dev, "%d UARTs detected\n", 1590 sc->sc_nports); 1591 1592 /* Set UARTs to enhanced mode */ 1593 bar = puc_get_bar(sc, cfg->rid); 1594 if (bar == NULL) 1595 return (ENXIO); 1596 for (idx = 0; idx < sc->sc_nports; idx++) { 1597 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1598 0x92); 1599 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1600 value | 0x10); 1601 } 1602 return (0); 1603 case PUC_CFG_GET_LEN: 1604 *res = 0x200; 1605 return (0); 1606 case PUC_CFG_GET_NPORTS: 1607 /* 1608 * Check if we are being called from puc_bfe_attach() 1609 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1610 * puc_get_bar(), so we return a value of 16. This has cosmetic 1611 * side-effects at worst; in PUC_CFG_GET_DESC, 1612 * (int)sc->sc_cfg_data will not contain the true number of 1613 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1614 * call for this device family anyway. 1615 * 1616 * The check is for initialisation of sc->sc_bar[idx], which is 1617 * only done in puc_bfe_attach(). 1618 */ 1619 idx = 0; 1620 do { 1621 if (sc->sc_bar[idx++].b_rid != -1) { 1622 sc->sc_cfg_data = 16; 1623 *res = sc->sc_cfg_data; 1624 return (0); 1625 } 1626 } while (idx < PUC_PCI_BARS); 1627 1628 bar = puc_get_bar(sc, cfg->rid); 1629 if (bar == NULL) 1630 return (ENXIO); 1631 1632 value = bus_read_1(bar->b_res, 0x04); 1633 if (value == 0) 1634 return (ENXIO); 1635 1636 sc->sc_cfg_data = value; 1637 *res = sc->sc_cfg_data; 1638 return (0); 1639 case PUC_CFG_GET_OFS: 1640 *res = 0x1000 + (port << 9); 1641 return (0); 1642 case PUC_CFG_GET_TYPE: 1643 *res = PUC_TYPE_SERIAL; 1644 return (0); 1645 default: 1646 break; 1647 } 1648 return (ENXIO); 1649 } 1650 1651 static int 1652 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1653 intptr_t *res) 1654 { 1655 int error; 1656 1657 switch (cmd) { 1658 case PUC_CFG_GET_OFS: 1659 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1660 if (error != 0) 1661 return (error); 1662 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1663 return (0); 1664 case PUC_CFG_GET_RID: 1665 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1666 if (error != 0) 1667 return (error); 1668 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1669 return (0); 1670 default: 1671 break; 1672 } 1673 return (ENXIO); 1674 } 1675 1676 static int 1677 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1678 intptr_t *res) 1679 { 1680 switch (cmd) { 1681 case PUC_CFG_GET_OFS: 1682 *res = (port < 3) ? 0 : (port - 2) << 3; 1683 return (0); 1684 case PUC_CFG_GET_RID: 1685 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1686 return (0); 1687 default: 1688 break; 1689 } 1690 return (ENXIO); 1691 } 1692