1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <sys/rman.h> 42 43 #include <dev/pci/pcivar.h> 44 45 #include <dev/puc/puc_bfe.h> 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 49 static puc_config_f puc_config_amc; 50 static puc_config_f puc_config_cronyx; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_icbook; 53 static puc_config_f puc_config_quatech; 54 static puc_config_f puc_config_syba; 55 static puc_config_f puc_config_siig; 56 static puc_config_f puc_config_timedia; 57 static puc_config_f puc_config_titan; 58 59 const struct puc_cfg puc_pci_devices[] = { 60 61 { 0x0009, 0x7168, 0xffff, 0, 62 "Sunix SUN1889", 63 DEFAULT_RCLK * 8, 64 PUC_PORT_2S, 0x10, 0, 8, 65 }, 66 67 { 0x103c, 0x1048, 0x103c, 0x1049, 68 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 69 DEFAULT_RCLK, 70 PUC_PORT_3S, 0x10, 0, -1, 71 .config_function = puc_config_diva 72 }, 73 74 { 0x103c, 0x1048, 0x103c, 0x104a, 75 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 76 DEFAULT_RCLK, 77 PUC_PORT_2S, 0x10, 0, -1, 78 .config_function = puc_config_diva 79 }, 80 81 { 0x103c, 0x1048, 0x103c, 0x104b, 82 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 83 DEFAULT_RCLK, 84 PUC_PORT_4S, 0x10, 0, -1, 85 .config_function = puc_config_diva 86 }, 87 88 { 0x103c, 0x1048, 0x103c, 0x1223, 89 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 90 DEFAULT_RCLK, 91 PUC_PORT_3S, 0x10, 0, -1, 92 .config_function = puc_config_diva 93 }, 94 95 { 0x103c, 0x1048, 0x103c, 0x1226, 96 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 97 DEFAULT_RCLK, 98 PUC_PORT_3S, 0x10, 0, -1, 99 .config_function = puc_config_diva 100 }, 101 102 { 0x103c, 0x1048, 0x103c, 0x1282, 103 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 104 DEFAULT_RCLK, 105 PUC_PORT_3S, 0x10, 0, -1, 106 .config_function = puc_config_diva 107 }, 108 109 { 0x10b5, 0x1076, 0x10b5, 0x1076, 110 "VScom PCI-800", 111 DEFAULT_RCLK * 8, 112 PUC_PORT_8S, 0x18, 0, 8, 113 }, 114 115 { 0x10b5, 0x1077, 0x10b5, 0x1077, 116 "VScom PCI-400", 117 DEFAULT_RCLK * 8, 118 PUC_PORT_4S, 0x18, 0, 8, 119 }, 120 121 { 0x10b5, 0x1103, 0x10b5, 0x1103, 122 "VScom PCI-200", 123 DEFAULT_RCLK * 8, 124 PUC_PORT_2S, 0x18, 4, 0, 125 }, 126 127 /* 128 * Boca Research Turbo Serial 658 (8 serial port) card. 129 * Appears to be the same as Chase Research PLC PCI-FAST8 130 * and Perle PCI-FAST8 Multi-Port serial cards. 131 */ 132 { 0x10b5, 0x9050, 0x12e0, 0x0021, 133 "Boca Research Turbo Serial 658", 134 DEFAULT_RCLK * 4, 135 PUC_PORT_8S, 0x18, 0, 8, 136 }, 137 138 { 0x10b5, 0x9050, 0x12e0, 0x0031, 139 "Boca Research Turbo Serial 654", 140 DEFAULT_RCLK * 4, 141 PUC_PORT_4S, 0x18, 0, 8, 142 }, 143 144 /* 145 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 146 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 147 * into the subsystem fields, and claims that it's a 148 * network/misc (0x02/0x80) device. 149 */ 150 { 0x10b5, 0x9050, 0xd84d, 0x6808, 151 "Dolphin Peripherals 4035", 152 DEFAULT_RCLK, 153 PUC_PORT_2S, 0x18, 4, 0, 154 }, 155 156 /* 157 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 158 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 159 * into the subsystem fields, and claims that it's a 160 * network/misc (0x02/0x80) device. 161 */ 162 { 0x10b5, 0x9050, 0xd84d, 0x6810, 163 "Dolphin Peripherals 4014", 164 0, 165 PUC_PORT_2P, 0x20, 4, 0, 166 }, 167 168 { 0x10e8, 0x818e, 0xffff, 0, 169 "Applied Micro Circuits 8 Port UART", 170 DEFAULT_RCLK, 171 PUC_PORT_8S, 0x14, -1, -1, 172 .config_function = puc_config_amc 173 }, 174 175 { 0x11fe, 0x8010, 0xffff, 0, 176 "Comtrol RocketPort 550/8 RJ11 part A", 177 DEFAULT_RCLK * 4, 178 PUC_PORT_4S, 0x10, 0, 8, 179 }, 180 181 { 0x11fe, 0x8011, 0xffff, 0, 182 "Comtrol RocketPort 550/8 RJ11 part B", 183 DEFAULT_RCLK * 4, 184 PUC_PORT_4S, 0x10, 0, 8, 185 }, 186 187 { 0x11fe, 0x8012, 0xffff, 0, 188 "Comtrol RocketPort 550/8 Octa part A", 189 DEFAULT_RCLK * 4, 190 PUC_PORT_4S, 0x10, 0, 8, 191 }, 192 193 { 0x11fe, 0x8013, 0xffff, 0, 194 "Comtrol RocketPort 550/8 Octa part B", 195 DEFAULT_RCLK * 4, 196 PUC_PORT_4S, 0x10, 0, 8, 197 }, 198 199 { 0x11fe, 0x8014, 0xffff, 0, 200 "Comtrol RocketPort 550/4 RJ45", 201 DEFAULT_RCLK * 4, 202 PUC_PORT_4S, 0x10, 0, 8, 203 }, 204 205 { 0x11fe, 0x8015, 0xffff, 0, 206 "Comtrol RocketPort 550/Quad", 207 DEFAULT_RCLK * 4, 208 PUC_PORT_4S, 0x10, 0, 8, 209 }, 210 211 { 0x11fe, 0x8016, 0xffff, 0, 212 "Comtrol RocketPort 550/16 part A", 213 DEFAULT_RCLK * 4, 214 PUC_PORT_4S, 0x10, 0, 8, 215 }, 216 217 { 0x11fe, 0x8017, 0xffff, 0, 218 "Comtrol RocketPort 550/16 part B", 219 DEFAULT_RCLK * 4, 220 PUC_PORT_12S, 0x10, 0, 8, 221 }, 222 223 { 0x11fe, 0x8018, 0xffff, 0, 224 "Comtrol RocketPort 550/8 part A", 225 DEFAULT_RCLK * 4, 226 PUC_PORT_4S, 0x10, 0, 8, 227 }, 228 229 { 0x11fe, 0x8019, 0xffff, 0, 230 "Comtrol RocketPort 550/8 part B", 231 DEFAULT_RCLK * 4, 232 PUC_PORT_4S, 0x10, 0, 8, 233 }, 234 235 /* 236 * SIIG Boards. 237 * 238 * SIIG provides documentation for their boards at: 239 * <URL:http://www.siig.com/downloads.asp> 240 */ 241 242 { 0x131f, 0x1010, 0xffff, 0, 243 "SIIG Cyber I/O PCI 16C550 (10x family)", 244 DEFAULT_RCLK, 245 PUC_PORT_1S1P, 0x18, 4, 0, 246 }, 247 248 { 0x131f, 0x1011, 0xffff, 0, 249 "SIIG Cyber I/O PCI 16C650 (10x family)", 250 DEFAULT_RCLK, 251 PUC_PORT_1S1P, 0x18, 4, 0, 252 }, 253 254 { 0x131f, 0x1012, 0xffff, 0, 255 "SIIG Cyber I/O PCI 16C850 (10x family)", 256 DEFAULT_RCLK, 257 PUC_PORT_1S1P, 0x18, 4, 0, 258 }, 259 260 { 0x131f, 0x1021, 0xffff, 0, 261 "SIIG Cyber Parallel Dual PCI (10x family)", 262 0, 263 PUC_PORT_2P, 0x18, 8, 0, 264 }, 265 266 { 0x131f, 0x1030, 0xffff, 0, 267 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 268 DEFAULT_RCLK, 269 PUC_PORT_2S, 0x18, 4, 0, 270 }, 271 272 { 0x131f, 0x1031, 0xffff, 0, 273 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 274 DEFAULT_RCLK, 275 PUC_PORT_2S, 0x18, 4, 0, 276 }, 277 278 { 0x131f, 0x1032, 0xffff, 0, 279 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 280 DEFAULT_RCLK, 281 PUC_PORT_2S, 0x18, 4, 0, 282 }, 283 284 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 285 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 286 DEFAULT_RCLK, 287 PUC_PORT_2S1P, 0x18, 4, 0, 288 }, 289 290 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 291 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 292 DEFAULT_RCLK, 293 PUC_PORT_2S1P, 0x18, 4, 0, 294 }, 295 296 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 297 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 298 DEFAULT_RCLK, 299 PUC_PORT_2S1P, 0x18, 4, 0, 300 }, 301 302 { 0x131f, 0x1050, 0xffff, 0, 303 "SIIG Cyber 4S PCI 16C550 (10x family)", 304 DEFAULT_RCLK, 305 PUC_PORT_4S, 0x18, 4, 0, 306 }, 307 308 { 0x131f, 0x1051, 0xffff, 0, 309 "SIIG Cyber 4S PCI 16C650 (10x family)", 310 DEFAULT_RCLK, 311 PUC_PORT_4S, 0x18, 4, 0, 312 }, 313 314 { 0x131f, 0x1052, 0xffff, 0, 315 "SIIG Cyber 4S PCI 16C850 (10x family)", 316 DEFAULT_RCLK, 317 PUC_PORT_4S, 0x18, 4, 0, 318 }, 319 320 { 0x131f, 0x2010, 0xffff, 0, 321 "SIIG Cyber I/O PCI 16C550 (20x family)", 322 DEFAULT_RCLK, 323 PUC_PORT_1S1P, 0x10, 4, 0, 324 }, 325 326 { 0x131f, 0x2011, 0xffff, 0, 327 "SIIG Cyber I/O PCI 16C650 (20x family)", 328 DEFAULT_RCLK, 329 PUC_PORT_1S1P, 0x10, 4, 0, 330 }, 331 332 { 0x131f, 0x2012, 0xffff, 0, 333 "SIIG Cyber I/O PCI 16C850 (20x family)", 334 DEFAULT_RCLK, 335 PUC_PORT_1S1P, 0x10, 4, 0, 336 }, 337 338 { 0x131f, 0x2021, 0xffff, 0, 339 "SIIG Cyber Parallel Dual PCI (20x family)", 340 0, 341 PUC_PORT_2P, 0x10, 8, 0, 342 }, 343 344 { 0x131f, 0x2030, 0xffff, 0, 345 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 346 DEFAULT_RCLK, 347 PUC_PORT_2S, 0x10, 4, 0, 348 }, 349 350 { 0x131f, 0x2031, 0xffff, 0, 351 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 352 DEFAULT_RCLK, 353 PUC_PORT_2S, 0x10, 4, 0, 354 }, 355 356 { 0x131f, 0x2032, 0xffff, 0, 357 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 358 DEFAULT_RCLK, 359 PUC_PORT_2S, 0x10, 4, 0, 360 }, 361 362 { 0x131f, 0x2040, 0xffff, 0, 363 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 364 DEFAULT_RCLK, 365 PUC_PORT_1S2P, 0x10, -1, 0, 366 .config_function = puc_config_siig 367 }, 368 369 { 0x131f, 0x2041, 0xffff, 0, 370 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 371 DEFAULT_RCLK, 372 PUC_PORT_1S2P, 0x10, -1, 0, 373 .config_function = puc_config_siig 374 }, 375 376 { 0x131f, 0x2042, 0xffff, 0, 377 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 378 DEFAULT_RCLK, 379 PUC_PORT_1S2P, 0x10, -1, 0, 380 .config_function = puc_config_siig 381 }, 382 383 { 0x131f, 0x2050, 0xffff, 0, 384 "SIIG Cyber 4S PCI 16C550 (20x family)", 385 DEFAULT_RCLK, 386 PUC_PORT_4S, 0x10, 4, 0, 387 }, 388 389 { 0x131f, 0x2051, 0xffff, 0, 390 "SIIG Cyber 4S PCI 16C650 (20x family)", 391 DEFAULT_RCLK, 392 PUC_PORT_4S, 0x10, 4, 0, 393 }, 394 395 { 0x131f, 0x2052, 0xffff, 0, 396 "SIIG Cyber 4S PCI 16C850 (20x family)", 397 DEFAULT_RCLK, 398 PUC_PORT_4S, 0x10, 4, 0, 399 }, 400 401 { 0x131f, 0x2060, 0xffff, 0, 402 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 403 DEFAULT_RCLK, 404 PUC_PORT_2S1P, 0x10, 4, 0, 405 }, 406 407 { 0x131f, 0x2061, 0xffff, 0, 408 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 409 DEFAULT_RCLK, 410 PUC_PORT_2S1P, 0x10, 4, 0, 411 }, 412 413 { 0x131f, 0x2062, 0xffff, 0, 414 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 415 DEFAULT_RCLK, 416 PUC_PORT_2S1P, 0x10, 4, 0, 417 }, 418 419 { 0x131f, 0x2081, 0xffff, 0, 420 "SIIG PS8000 8S PCI 16C650 (20x family)", 421 DEFAULT_RCLK, 422 PUC_PORT_8S, 0x10, -1, -1, 423 .config_function = puc_config_siig 424 }, 425 426 { 0x135c, 0x0010, 0xffff, 0, 427 "Quatech QSC-100", 428 -3, /* max 8x clock rate */ 429 PUC_PORT_4S, 0x14, 0, 8, 430 .config_function = puc_config_quatech 431 }, 432 433 { 0x135c, 0x0020, 0xffff, 0, 434 "Quatech DSC-100", 435 -1, /* max 2x clock rate */ 436 PUC_PORT_2S, 0x14, 0, 8, 437 .config_function = puc_config_quatech 438 }, 439 440 { 0x135c, 0x0030, 0xffff, 0, 441 "Quatech DSC-200/300", 442 -1, /* max 2x clock rate */ 443 PUC_PORT_2S, 0x14, 0, 8, 444 .config_function = puc_config_quatech 445 }, 446 447 { 0x135c, 0x0040, 0xffff, 0, 448 "Quatech QSC-200/300", 449 -3, /* max 8x clock rate */ 450 PUC_PORT_4S, 0x14, 0, 8, 451 .config_function = puc_config_quatech 452 }, 453 454 { 0x135c, 0x0050, 0xffff, 0, 455 "Quatech ESC-100D", 456 -3, /* max 8x clock rate */ 457 PUC_PORT_8S, 0x14, 0, 8, 458 .config_function = puc_config_quatech 459 }, 460 461 { 0x135c, 0x0060, 0xffff, 0, 462 "Quatech ESC-100M", 463 -3, /* max 8x clock rate */ 464 PUC_PORT_8S, 0x14, 0, 8, 465 .config_function = puc_config_quatech 466 }, 467 468 { 0x135c, 0x0170, 0xffff, 0, 469 "Quatech QSCLP-100", 470 -1, /* max 2x clock rate */ 471 PUC_PORT_4S, 0x18, 0, 8, 472 .config_function = puc_config_quatech 473 }, 474 475 { 0x135c, 0x0180, 0xffff, 0, 476 "Quatech DSCLP-100", 477 -1, /* max 3x clock rate */ 478 PUC_PORT_2S, 0x18, 0, 8, 479 .config_function = puc_config_quatech 480 }, 481 482 { 0x135c, 0x01b0, 0xffff, 0, 483 "Quatech DSCLP-200/300", 484 -1, /* max 2x clock rate */ 485 PUC_PORT_2S, 0x18, 0, 8, 486 .config_function = puc_config_quatech 487 }, 488 489 { 0x135c, 0x01e0, 0xffff, 0, 490 "Quatech ESCLP-100", 491 -3, /* max 8x clock rate */ 492 PUC_PORT_8S, 0x10, 0, 8, 493 .config_function = puc_config_quatech 494 }, 495 496 { 0x1393, 0x1040, 0xffff, 0, 497 "Moxa Technologies, Smartio C104H/PCI", 498 DEFAULT_RCLK * 8, 499 PUC_PORT_4S, 0x18, 0, 8, 500 }, 501 502 { 0x1393, 0x1041, 0xffff, 0, 503 "Moxa Technologies, Smartio CP-104UL/PCI", 504 DEFAULT_RCLK * 8, 505 PUC_PORT_4S, 0x18, 0, 8, 506 }, 507 508 { 0x1393, 0x1141, 0xffff, 0, 509 "Moxa Technologies, Industio CP-114", 510 DEFAULT_RCLK * 8, 511 PUC_PORT_4S, 0x18, 0, 8, 512 }, 513 514 { 0x1393, 0x1680, 0xffff, 0, 515 "Moxa Technologies, C168H/PCI", 516 DEFAULT_RCLK * 8, 517 PUC_PORT_8S, 0x18, 0, 8, 518 }, 519 520 { 0x1393, 0x1681, 0xffff, 0, 521 "Moxa Technologies, C168U/PCI", 522 DEFAULT_RCLK * 8, 523 PUC_PORT_8S, 0x18, 0, 8, 524 }, 525 526 { 0x13a8, 0x0158, 0xffff, 0, 527 "Cronyx Omega2-PCI", 528 DEFAULT_RCLK * 8, 529 PUC_PORT_8S, 0x10, 0, -1, 530 .config_function = puc_config_cronyx 531 }, 532 533 { 0x1407, 0x0100, 0xffff, 0, 534 "Lava Computers Dual Serial", 535 DEFAULT_RCLK, 536 PUC_PORT_2S, 0x10, 4, 0, 537 }, 538 539 { 0x1407, 0x0101, 0xffff, 0, 540 "Lava Computers Quatro A", 541 DEFAULT_RCLK, 542 PUC_PORT_2S, 0x10, 4, 0, 543 }, 544 545 { 0x1407, 0x0102, 0xffff, 0, 546 "Lava Computers Quatro B", 547 DEFAULT_RCLK, 548 PUC_PORT_2S, 0x10, 4, 0, 549 }, 550 551 { 0x1407, 0x0120, 0xffff, 0, 552 "Lava Computers Quattro-PCI A", 553 DEFAULT_RCLK, 554 PUC_PORT_2S, 0x10, 4, 0, 555 }, 556 557 { 0x1407, 0x0121, 0xffff, 0, 558 "Lava Computers Quattro-PCI B", 559 DEFAULT_RCLK, 560 PUC_PORT_2S, 0x10, 4, 0, 561 }, 562 563 { 0x1407, 0x0180, 0xffff, 0, 564 "Lava Computers Octo A", 565 DEFAULT_RCLK, 566 PUC_PORT_4S, 0x10, 4, 0, 567 }, 568 569 { 0x1407, 0x0181, 0xffff, 0, 570 "Lava Computers Octo B", 571 DEFAULT_RCLK, 572 PUC_PORT_4S, 0x10, 4, 0, 573 }, 574 575 { 0x1409, 0x7168, 0xffff, 0, 576 NULL, 577 DEFAULT_RCLK * 8, 578 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 579 .config_function = puc_config_timedia 580 }, 581 582 /* 583 * Boards with an Oxford Semiconductor chip. 584 * 585 * Oxford Semiconductor provides documentation for their chip at: 586 * <URL:http://www.oxsemi.com/products/uarts/index.html> 587 * 588 * As sold by Kouwell <URL:http://www.kouwell.com/>. 589 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 590 */ 591 592 { 0x1415, 0x9501, 0xffff, 0, 593 "Oxford Semiconductor OX16PCI954 UARTs", 594 DEFAULT_RCLK, 595 PUC_PORT_4S, 0x10, 0, 8, 596 }, 597 598 { 0x1415, 0x950a, 0xffff, 0, 599 "Oxford Semiconductor OX16PCI954 UARTs", 600 DEFAULT_RCLK, 601 PUC_PORT_4S, 0x10, 0, 8, 602 }, 603 604 { 0x1415, 0x9511, 0xffff, 0, 605 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 606 DEFAULT_RCLK, 607 PUC_PORT_4S, 0x10, 0, 8, 608 }, 609 610 { 0x1415, 0x9521, 0xffff, 0, 611 "Oxford Semiconductor OX16PCI952 UARTs", 612 DEFAULT_RCLK, 613 PUC_PORT_2S, 0x10, 4, 0, 614 }, 615 616 { 0x14d2, 0x8020, 0xffff, 0, 617 "VScom PCI-200L", 618 DEFAULT_RCLK * 8, 619 PUC_PORT_2S, 0x14, 4, 0, 620 }, 621 622 { 0x14d2, 0x8028, 0xffff, 0, 623 "VScom 200Li", 624 DEFAULT_RCLK, 625 PUC_PORT_2S, 0x20, 0, 8, 626 }, 627 628 /* 629 * VScom (Titan?) PCI-800L. More modern variant of the 630 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 631 * two of them obviously implemented as macro cells in 632 * the ASIC. This causes the weird port access pattern 633 * below, where two of the IO port ranges each access 634 * one of the ASIC UARTs, and a block of IO addresses 635 * access the external UARTs. 636 */ 637 { 0x14d2, 0x8080, 0xffff, 0, 638 "Titan VScom PCI-800L", 639 DEFAULT_RCLK * 8, 640 PUC_PORT_8S, 0x14, -1, -1, 641 .config_function = puc_config_titan 642 }, 643 644 /* 645 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 646 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 647 * device ID 3 and PCI device 1 device ID 4. 648 */ 649 { 0x14d2, 0xa003, 0xffff, 0, 650 "Titan PCI-800H", 651 DEFAULT_RCLK * 8, 652 PUC_PORT_4S, 0x10, 0, 8, 653 }, 654 { 0x14d2, 0xa004, 0xffff, 0, 655 "Titan PCI-800H", 656 DEFAULT_RCLK * 8, 657 PUC_PORT_4S, 0x10, 0, 8, 658 }, 659 660 { 0x14d2, 0xa005, 0xffff, 0, 661 "Titan PCI-200H", 662 DEFAULT_RCLK * 8, 663 PUC_PORT_2S, 0x10, 0, 8, 664 }, 665 666 { 0x14d2, 0xe020, 0xffff, 0, 667 "Titan VScom PCI-200HV2", 668 DEFAULT_RCLK * 8, 669 PUC_PORT_2S, 0x10, 4, 0, 670 }, 671 672 { 0x14db, 0x2130, 0xffff, 0, 673 "Avlab Technology, PCI IO 2S", 674 DEFAULT_RCLK, 675 PUC_PORT_2S, 0x10, 4, 0, 676 }, 677 678 { 0x14db, 0x2150, 0xffff, 0, 679 "Avlab Low Profile PCI 4 Serial", 680 DEFAULT_RCLK, 681 PUC_PORT_4S, 0x10, 4, 0, 682 }, 683 684 { 0x1592, 0x0781, 0xffff, 0, 685 "Syba Tech Ltd. PCI-4S2P-550-ECP", 686 DEFAULT_RCLK, 687 PUC_PORT_4S1P, 0x10, 0, -1, 688 .config_function = puc_config_syba 689 }, 690 691 { 0x6666, 0x0001, 0xffff, 0, 692 "Decision Computer Inc, PCCOM 4-port serial", 693 DEFAULT_RCLK, 694 PUC_PORT_4S, 0x1c, 0, 8, 695 }, 696 697 { 0x6666, 0x0004, 0xffff, 0, 698 "PCCOM dual port RS232/422/485", 699 DEFAULT_RCLK, 700 PUC_PORT_2S, 0x1c, 0, 8, 701 }, 702 703 { 0x9710, 0x9815, 0xffff, 0, 704 "NetMos NM9815 Dual 1284 Printer port", 705 0, 706 PUC_PORT_2P, 0x10, 8, 0, 707 }, 708 709 { 0x9710, 0x9835, 0xffff, 0, 710 "NetMos NM9835 Dual UART and 1284 Printer port", 711 DEFAULT_RCLK, 712 PUC_PORT_2S1P, 0x10, 4, 0, 713 }, 714 715 { 0x9710, 0x9845, 0x1000, 0x0006, 716 "NetMos NM9845 6 Port UART", 717 DEFAULT_RCLK, 718 PUC_PORT_6S, 0x10, 4, 0, 719 }, 720 721 { 0x9710, 0x9845, 0xffff, 0, 722 "NetMos NM9845 Quad UART and 1284 Printer port", 723 DEFAULT_RCLK, 724 PUC_PORT_4S1P, 0x10, 4, 0, 725 }, 726 727 { 0xb00c, 0x021c, 0xffff, 0, 728 "IC Book Labs Gunboat x4 Lite", 729 DEFAULT_RCLK, 730 PUC_PORT_4S, 0x10, 0, 8, 731 .config_function = puc_config_icbook 732 }, 733 734 { 0xb00c, 0x031c, 0xffff, 0, 735 "IC Book Labs Gunboat x4 Pro", 736 DEFAULT_RCLK, 737 PUC_PORT_4S, 0x10, 0, 8, 738 .config_function = puc_config_icbook 739 }, 740 741 { 0xb00c, 0x041c, 0xffff, 0, 742 "IC Book Labs Ironclad x8 Lite", 743 DEFAULT_RCLK, 744 PUC_PORT_8S, 0x10, 0, 8, 745 .config_function = puc_config_icbook 746 }, 747 748 { 0xb00c, 0x051c, 0xffff, 0, 749 "IC Book Labs Ironclad x8 Pro", 750 DEFAULT_RCLK, 751 PUC_PORT_8S, 0x10, 0, 8, 752 .config_function = puc_config_icbook 753 }, 754 755 { 0xb00c, 0x081c, 0xffff, 0, 756 "IC Book Labs Dreadnought x16 Pro", 757 DEFAULT_RCLK * 8, 758 PUC_PORT_16S, 0x10, 0, 8, 759 .config_function = puc_config_icbook 760 }, 761 762 { 0xb00c, 0x091c, 0xffff, 0, 763 "IC Book Labs Dreadnought x16 Lite", 764 DEFAULT_RCLK, 765 PUC_PORT_16S, 0x10, 0, 8, 766 .config_function = puc_config_icbook 767 }, 768 769 { 0xb00c, 0x0a1c, 0xffff, 0, 770 "IC Book Labs Gunboat x2 Low Profile", 771 DEFAULT_RCLK, 772 PUC_PORT_2S, 0x10, 0, 8, 773 }, 774 775 { 0xb00c, 0x0b1c, 0xffff, 0, 776 "IC Book Labs Gunboat x4 Low Profile", 777 DEFAULT_RCLK, 778 PUC_PORT_4S, 0x10, 0, 8, 779 .config_function = puc_config_icbook 780 }, 781 782 { 0xffff, 0, 0xffff, 0, NULL, 0 } 783 }; 784 785 static int 786 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 787 intptr_t *res) 788 { 789 switch (cmd) { 790 case PUC_CFG_GET_OFS: 791 *res = 8 * (port & 1); 792 return (0); 793 case PUC_CFG_GET_RID: 794 *res = 0x14 + (port >> 1) * 4; 795 return (0); 796 default: 797 break; 798 } 799 return (ENXIO); 800 } 801 802 static int 803 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 804 intptr_t *res) 805 { 806 if (cmd == PUC_CFG_GET_OFS) { 807 *res = port * 0x200; 808 return (0); 809 } 810 return (ENXIO); 811 } 812 813 static int 814 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 815 intptr_t *res) 816 { 817 const struct puc_cfg *cfg = sc->sc_cfg; 818 819 if (cmd == PUC_CFG_GET_OFS) { 820 if (cfg->subdevice == 0x1282) /* Everest SP */ 821 port <<= 1; 822 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 823 port = (port == 3) ? 4 : port; 824 *res = port * 8 + ((port > 2) ? 0x18 : 0); 825 return (0); 826 } 827 return (ENXIO); 828 } 829 830 static int 831 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 832 intptr_t *res) 833 { 834 if (cmd == PUC_CFG_GET_ILR) { 835 *res = PUC_ILR_DIGI; 836 return (0); 837 } 838 return (ENXIO); 839 } 840 841 static int 842 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 843 intptr_t *res) 844 { 845 const struct puc_cfg *cfg = sc->sc_cfg; 846 struct puc_bar *bar; 847 uint8_t v0, v1; 848 849 switch (cmd) { 850 case PUC_CFG_SETUP: 851 /* 852 * Check if the scratchpad register is enabled or if the 853 * interrupt status and options registers are active. 854 */ 855 bar = puc_get_bar(sc, cfg->rid); 856 if (bar == NULL) 857 return (ENXIO); 858 /* Set DLAB in the LCR register of UART 0. */ 859 bus_write_1(bar->b_res, 3, 0x80); 860 /* Write 0 to the SPR register of UART 0. */ 861 bus_write_1(bar->b_res, 7, 0); 862 /* Read back the contents of the SPR register of UART 0. */ 863 v0 = bus_read_1(bar->b_res, 7); 864 /* Write a specific value to the SPR register of UART 0. */ 865 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 866 /* Read back the contents of the SPR register of UART 0. */ 867 v1 = bus_read_1(bar->b_res, 7); 868 /* Clear DLAB in the LCR register of UART 0. */ 869 bus_write_1(bar->b_res, 3, 0); 870 /* Save the two values read-back from the SPR register. */ 871 sc->sc_cfg_data = (v0 << 8) | v1; 872 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 873 /* 874 * The SPR register echoed the two values written 875 * by us. This means that the SPAD jumper is set. 876 */ 877 device_printf(sc->sc_dev, "warning: extra features " 878 "not usable -- SPAD compatibility enabled\n"); 879 return (0); 880 } 881 if (v0 != 0) { 882 /* 883 * The first value doesn't match. This can only mean 884 * that the SPAD jumper is not set and that a non- 885 * standard fixed clock multiplier jumper is set. 886 */ 887 if (bootverbose) 888 device_printf(sc->sc_dev, "fixed clock rate " 889 "multiplier of %d\n", 1 << v0); 890 if (v0 < -cfg->clock) 891 device_printf(sc->sc_dev, "warning: " 892 "suboptimal fixed clock rate multiplier " 893 "setting\n"); 894 return (0); 895 } 896 /* 897 * The first value matched, but the second didn't. We know 898 * that the SPAD jumper is not set. We also know that the 899 * clock rate multiplier is software controlled *and* that 900 * we just programmed it to the maximum allowed. 901 */ 902 if (bootverbose) 903 device_printf(sc->sc_dev, "clock rate multiplier of " 904 "%d selected\n", 1 << -cfg->clock); 905 return (0); 906 case PUC_CFG_GET_CLOCK: 907 v0 = (sc->sc_cfg_data >> 8) & 0xff; 908 v1 = sc->sc_cfg_data & 0xff; 909 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 910 /* 911 * XXX With the SPAD jumper applied, there's no 912 * easy way of knowing if there's also a clock 913 * rate multiplier jumper installed. Let's hope 914 * not... 915 */ 916 *res = DEFAULT_RCLK; 917 } else if (v0 == 0) { 918 /* 919 * No clock rate multiplier jumper installed, 920 * so we programmed the board with the maximum 921 * multiplier allowed as given to us in the 922 * clock field of the config record (negated). 923 */ 924 *res = DEFAULT_RCLK << -cfg->clock; 925 } else 926 *res = DEFAULT_RCLK << v0; 927 return (0); 928 case PUC_CFG_GET_ILR: 929 v0 = (sc->sc_cfg_data >> 8) & 0xff; 930 v1 = sc->sc_cfg_data & 0xff; 931 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 932 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 933 return (0); 934 default: 935 break; 936 } 937 return (ENXIO); 938 } 939 940 static int 941 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 942 intptr_t *res) 943 { 944 static int base[] = { 0x251, 0x3f0, 0 }; 945 const struct puc_cfg *cfg = sc->sc_cfg; 946 struct puc_bar *bar; 947 int efir, idx, ofs; 948 uint8_t v; 949 950 switch (cmd) { 951 case PUC_CFG_SETUP: 952 bar = puc_get_bar(sc, cfg->rid); 953 if (bar == NULL) 954 return (ENXIO); 955 956 /* configure both W83877TFs */ 957 bus_write_1(bar->b_res, 0x250, 0x89); 958 bus_write_1(bar->b_res, 0x3f0, 0x87); 959 bus_write_1(bar->b_res, 0x3f0, 0x87); 960 idx = 0; 961 while (base[idx] != 0) { 962 efir = base[idx]; 963 bus_write_1(bar->b_res, efir, 0x09); 964 v = bus_read_1(bar->b_res, efir + 1); 965 if ((v & 0x0f) != 0x0c) 966 return (ENXIO); 967 bus_write_1(bar->b_res, efir, 0x16); 968 v = bus_read_1(bar->b_res, efir + 1); 969 bus_write_1(bar->b_res, efir, 0x16); 970 bus_write_1(bar->b_res, efir + 1, v | 0x04); 971 bus_write_1(bar->b_res, efir, 0x16); 972 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 973 ofs = base[idx] & 0x300; 974 bus_write_1(bar->b_res, efir, 0x23); 975 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 976 bus_write_1(bar->b_res, efir, 0x24); 977 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 978 bus_write_1(bar->b_res, efir, 0x25); 979 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 980 bus_write_1(bar->b_res, efir, 0x17); 981 bus_write_1(bar->b_res, efir + 1, 0x03); 982 bus_write_1(bar->b_res, efir, 0x28); 983 bus_write_1(bar->b_res, efir + 1, 0x43); 984 idx++; 985 } 986 bus_write_1(bar->b_res, 0x250, 0xaa); 987 bus_write_1(bar->b_res, 0x3f0, 0xaa); 988 return (0); 989 case PUC_CFG_GET_OFS: 990 switch (port) { 991 case 0: 992 *res = 0x2f8; 993 return (0); 994 case 1: 995 *res = 0x2e8; 996 return (0); 997 case 2: 998 *res = 0x3f8; 999 return (0); 1000 case 3: 1001 *res = 0x3e8; 1002 return (0); 1003 case 4: 1004 *res = 0x278; 1005 return (0); 1006 } 1007 break; 1008 default: 1009 break; 1010 } 1011 return (ENXIO); 1012 } 1013 1014 static int 1015 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1016 intptr_t *res) 1017 { 1018 const struct puc_cfg *cfg = sc->sc_cfg; 1019 1020 switch (cmd) { 1021 case PUC_CFG_GET_OFS: 1022 if (cfg->ports == PUC_PORT_8S) { 1023 *res = (port > 4) ? 8 * (port - 4) : 0; 1024 return (0); 1025 } 1026 break; 1027 case PUC_CFG_GET_RID: 1028 if (cfg->ports == PUC_PORT_8S) { 1029 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1030 return (0); 1031 } 1032 if (cfg->ports == PUC_PORT_2S1P) { 1033 switch (port) { 1034 case 0: *res = 0x10; return (0); 1035 case 1: *res = 0x14; return (0); 1036 case 2: *res = 0x1c; return (0); 1037 } 1038 } 1039 break; 1040 default: 1041 break; 1042 } 1043 return (ENXIO); 1044 } 1045 1046 static int 1047 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1048 intptr_t *res) 1049 { 1050 static uint16_t dual[] = { 1051 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1052 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1053 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1054 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1055 0xD079, 0 1056 }; 1057 static uint16_t quad[] = { 1058 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1059 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1060 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1061 0xB157, 0 1062 }; 1063 static uint16_t octa[] = { 1064 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1065 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1066 }; 1067 static struct { 1068 int ports; 1069 uint16_t *ids; 1070 } subdevs[] = { 1071 { 2, dual }, 1072 { 4, quad }, 1073 { 8, octa }, 1074 { 0, NULL } 1075 }; 1076 static char desc[64]; 1077 int dev, id; 1078 uint16_t subdev; 1079 1080 switch (cmd) { 1081 case PUC_CFG_GET_DESC: 1082 snprintf(desc, sizeof(desc), 1083 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1084 *res = (intptr_t)desc; 1085 return (0); 1086 case PUC_CFG_GET_NPORTS: 1087 subdev = pci_get_subdevice(sc->sc_dev); 1088 dev = 0; 1089 while (subdevs[dev].ports != 0) { 1090 id = 0; 1091 while (subdevs[dev].ids[id] != 0) { 1092 if (subdev == subdevs[dev].ids[id]) { 1093 sc->sc_cfg_data = subdevs[dev].ports; 1094 *res = sc->sc_cfg_data; 1095 return (0); 1096 } 1097 id++; 1098 } 1099 dev++; 1100 } 1101 return (ENXIO); 1102 case PUC_CFG_GET_OFS: 1103 *res = (port == 1 || port == 3) ? 8 : 0; 1104 return (0); 1105 case PUC_CFG_GET_RID: 1106 *res = (port > 3) ? port - 2 : port >> 1; 1107 return (0); 1108 case PUC_CFG_GET_TYPE: 1109 *res = PUC_TYPE_SERIAL; 1110 return (0); 1111 default: 1112 break; 1113 } 1114 return (ENXIO); 1115 } 1116 1117 static int 1118 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1119 intptr_t *res) 1120 { 1121 switch (cmd) { 1122 case PUC_CFG_GET_OFS: 1123 *res = (port < 3) ? 0 : (port - 2) << 3; 1124 return (0); 1125 case PUC_CFG_GET_RID: 1126 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1127 return (0); 1128 default: 1129 break; 1130 } 1131 return (ENXIO); 1132 } 1133