1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_diva; 52 static puc_config_f puc_config_exar; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_oxford_pcie; 55 static puc_config_f puc_config_quatech; 56 static puc_config_f puc_config_syba; 57 static puc_config_f puc_config_siig; 58 static puc_config_f puc_config_timedia; 59 static puc_config_f puc_config_titan; 60 61 const struct puc_cfg puc_pci_devices[] = { 62 63 { 0x0009, 0x7168, 0xffff, 0, 64 "Sunix SUN1889", 65 DEFAULT_RCLK * 8, 66 PUC_PORT_2S, 0x10, 0, 8, 67 }, 68 69 { 0x103c, 0x1048, 0x103c, 0x1049, 70 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 71 DEFAULT_RCLK, 72 PUC_PORT_3S, 0x10, 0, -1, 73 .config_function = puc_config_diva 74 }, 75 76 { 0x103c, 0x1048, 0x103c, 0x104a, 77 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 78 DEFAULT_RCLK, 79 PUC_PORT_2S, 0x10, 0, -1, 80 .config_function = puc_config_diva 81 }, 82 83 { 0x103c, 0x1048, 0x103c, 0x104b, 84 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 85 DEFAULT_RCLK, 86 PUC_PORT_4S, 0x10, 0, -1, 87 .config_function = puc_config_diva 88 }, 89 90 { 0x103c, 0x1048, 0x103c, 0x1223, 91 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 92 DEFAULT_RCLK, 93 PUC_PORT_3S, 0x10, 0, -1, 94 .config_function = puc_config_diva 95 }, 96 97 { 0x103c, 0x1048, 0x103c, 0x1226, 98 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 99 DEFAULT_RCLK, 100 PUC_PORT_3S, 0x10, 0, -1, 101 .config_function = puc_config_diva 102 }, 103 104 { 0x103c, 0x1048, 0x103c, 0x1282, 105 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 106 DEFAULT_RCLK, 107 PUC_PORT_3S, 0x10, 0, -1, 108 .config_function = puc_config_diva 109 }, 110 111 { 0x10b5, 0x1076, 0x10b5, 0x1076, 112 "VScom PCI-800", 113 DEFAULT_RCLK * 8, 114 PUC_PORT_8S, 0x18, 0, 8, 115 }, 116 117 { 0x10b5, 0x1077, 0x10b5, 0x1077, 118 "VScom PCI-400", 119 DEFAULT_RCLK * 8, 120 PUC_PORT_4S, 0x18, 0, 8, 121 }, 122 123 { 0x10b5, 0x1103, 0x10b5, 0x1103, 124 "VScom PCI-200", 125 DEFAULT_RCLK * 8, 126 PUC_PORT_2S, 0x18, 4, 0, 127 }, 128 129 /* 130 * Boca Research Turbo Serial 658 (8 serial port) card. 131 * Appears to be the same as Chase Research PLC PCI-FAST8 132 * and Perle PCI-FAST8 Multi-Port serial cards. 133 */ 134 { 0x10b5, 0x9050, 0x12e0, 0x0021, 135 "Boca Research Turbo Serial 658", 136 DEFAULT_RCLK * 4, 137 PUC_PORT_8S, 0x18, 0, 8, 138 }, 139 140 { 0x10b5, 0x9050, 0x12e0, 0x0031, 141 "Boca Research Turbo Serial 654", 142 DEFAULT_RCLK * 4, 143 PUC_PORT_4S, 0x18, 0, 8, 144 }, 145 146 /* 147 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 148 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 149 * into the subsystem fields, and claims that it's a 150 * network/misc (0x02/0x80) device. 151 */ 152 { 0x10b5, 0x9050, 0xd84d, 0x6808, 153 "Dolphin Peripherals 4035", 154 DEFAULT_RCLK, 155 PUC_PORT_2S, 0x18, 4, 0, 156 }, 157 158 /* 159 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 160 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 161 * into the subsystem fields, and claims that it's a 162 * network/misc (0x02/0x80) device. 163 */ 164 { 0x10b5, 0x9050, 0xd84d, 0x6810, 165 "Dolphin Peripherals 4014", 166 0, 167 PUC_PORT_2P, 0x20, 4, 0, 168 }, 169 170 { 0x10e8, 0x818e, 0xffff, 0, 171 "Applied Micro Circuits 8 Port UART", 172 DEFAULT_RCLK, 173 PUC_PORT_8S, 0x14, -1, -1, 174 .config_function = puc_config_amc 175 }, 176 177 { 0x11fe, 0x8010, 0xffff, 0, 178 "Comtrol RocketPort 550/8 RJ11 part A", 179 DEFAULT_RCLK * 4, 180 PUC_PORT_4S, 0x10, 0, 8, 181 }, 182 183 { 0x11fe, 0x8011, 0xffff, 0, 184 "Comtrol RocketPort 550/8 RJ11 part B", 185 DEFAULT_RCLK * 4, 186 PUC_PORT_4S, 0x10, 0, 8, 187 }, 188 189 { 0x11fe, 0x8012, 0xffff, 0, 190 "Comtrol RocketPort 550/8 Octa part A", 191 DEFAULT_RCLK * 4, 192 PUC_PORT_4S, 0x10, 0, 8, 193 }, 194 195 { 0x11fe, 0x8013, 0xffff, 0, 196 "Comtrol RocketPort 550/8 Octa part B", 197 DEFAULT_RCLK * 4, 198 PUC_PORT_4S, 0x10, 0, 8, 199 }, 200 201 { 0x11fe, 0x8014, 0xffff, 0, 202 "Comtrol RocketPort 550/4 RJ45", 203 DEFAULT_RCLK * 4, 204 PUC_PORT_4S, 0x10, 0, 8, 205 }, 206 207 { 0x11fe, 0x8015, 0xffff, 0, 208 "Comtrol RocketPort 550/Quad", 209 DEFAULT_RCLK * 4, 210 PUC_PORT_4S, 0x10, 0, 8, 211 }, 212 213 { 0x11fe, 0x8016, 0xffff, 0, 214 "Comtrol RocketPort 550/16 part A", 215 DEFAULT_RCLK * 4, 216 PUC_PORT_4S, 0x10, 0, 8, 217 }, 218 219 { 0x11fe, 0x8017, 0xffff, 0, 220 "Comtrol RocketPort 550/16 part B", 221 DEFAULT_RCLK * 4, 222 PUC_PORT_12S, 0x10, 0, 8, 223 }, 224 225 { 0x11fe, 0x8018, 0xffff, 0, 226 "Comtrol RocketPort 550/8 part A", 227 DEFAULT_RCLK * 4, 228 PUC_PORT_4S, 0x10, 0, 8, 229 }, 230 231 { 0x11fe, 0x8019, 0xffff, 0, 232 "Comtrol RocketPort 550/8 part B", 233 DEFAULT_RCLK * 4, 234 PUC_PORT_4S, 0x10, 0, 8, 235 }, 236 237 /* 238 * IBM SurePOS 300 Series (481033H) serial ports 239 * Details can be found on the IBM RSS websites 240 */ 241 242 { 0x1014, 0x0297, 0xffff, 0, 243 "IBM SurePOS 300 Series (481033H) serial ports", 244 DEFAULT_RCLK, 245 PUC_PORT_4S, 0x10, 4, 0 246 }, 247 248 /* 249 * SIIG Boards. 250 * 251 * SIIG provides documentation for their boards at: 252 * <URL:http://www.siig.com/downloads.asp> 253 */ 254 255 { 0x131f, 0x1010, 0xffff, 0, 256 "SIIG Cyber I/O PCI 16C550 (10x family)", 257 DEFAULT_RCLK, 258 PUC_PORT_1S1P, 0x18, 4, 0, 259 }, 260 261 { 0x131f, 0x1011, 0xffff, 0, 262 "SIIG Cyber I/O PCI 16C650 (10x family)", 263 DEFAULT_RCLK, 264 PUC_PORT_1S1P, 0x18, 4, 0, 265 }, 266 267 { 0x131f, 0x1012, 0xffff, 0, 268 "SIIG Cyber I/O PCI 16C850 (10x family)", 269 DEFAULT_RCLK, 270 PUC_PORT_1S1P, 0x18, 4, 0, 271 }, 272 273 { 0x131f, 0x1021, 0xffff, 0, 274 "SIIG Cyber Parallel Dual PCI (10x family)", 275 0, 276 PUC_PORT_2P, 0x18, 8, 0, 277 }, 278 279 { 0x131f, 0x1030, 0xffff, 0, 280 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 281 DEFAULT_RCLK, 282 PUC_PORT_2S, 0x18, 4, 0, 283 }, 284 285 { 0x131f, 0x1031, 0xffff, 0, 286 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 287 DEFAULT_RCLK, 288 PUC_PORT_2S, 0x18, 4, 0, 289 }, 290 291 { 0x131f, 0x1032, 0xffff, 0, 292 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 293 DEFAULT_RCLK, 294 PUC_PORT_2S, 0x18, 4, 0, 295 }, 296 297 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 298 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 299 DEFAULT_RCLK, 300 PUC_PORT_2S1P, 0x18, 4, 0, 301 }, 302 303 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 304 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 305 DEFAULT_RCLK, 306 PUC_PORT_2S1P, 0x18, 4, 0, 307 }, 308 309 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 310 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 311 DEFAULT_RCLK, 312 PUC_PORT_2S1P, 0x18, 4, 0, 313 }, 314 315 { 0x131f, 0x1050, 0xffff, 0, 316 "SIIG Cyber 4S PCI 16C550 (10x family)", 317 DEFAULT_RCLK, 318 PUC_PORT_4S, 0x18, 4, 0, 319 }, 320 321 { 0x131f, 0x1051, 0xffff, 0, 322 "SIIG Cyber 4S PCI 16C650 (10x family)", 323 DEFAULT_RCLK, 324 PUC_PORT_4S, 0x18, 4, 0, 325 }, 326 327 { 0x131f, 0x1052, 0xffff, 0, 328 "SIIG Cyber 4S PCI 16C850 (10x family)", 329 DEFAULT_RCLK, 330 PUC_PORT_4S, 0x18, 4, 0, 331 }, 332 333 { 0x131f, 0x2010, 0xffff, 0, 334 "SIIG Cyber I/O PCI 16C550 (20x family)", 335 DEFAULT_RCLK, 336 PUC_PORT_1S1P, 0x10, 4, 0, 337 }, 338 339 { 0x131f, 0x2011, 0xffff, 0, 340 "SIIG Cyber I/O PCI 16C650 (20x family)", 341 DEFAULT_RCLK, 342 PUC_PORT_1S1P, 0x10, 4, 0, 343 }, 344 345 { 0x131f, 0x2012, 0xffff, 0, 346 "SIIG Cyber I/O PCI 16C850 (20x family)", 347 DEFAULT_RCLK, 348 PUC_PORT_1S1P, 0x10, 4, 0, 349 }, 350 351 { 0x131f, 0x2021, 0xffff, 0, 352 "SIIG Cyber Parallel Dual PCI (20x family)", 353 0, 354 PUC_PORT_2P, 0x10, 8, 0, 355 }, 356 357 { 0x131f, 0x2030, 0xffff, 0, 358 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 359 DEFAULT_RCLK, 360 PUC_PORT_2S, 0x10, 4, 0, 361 }, 362 363 { 0x131f, 0x2031, 0xffff, 0, 364 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 365 DEFAULT_RCLK, 366 PUC_PORT_2S, 0x10, 4, 0, 367 }, 368 369 { 0x131f, 0x2032, 0xffff, 0, 370 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 371 DEFAULT_RCLK, 372 PUC_PORT_2S, 0x10, 4, 0, 373 }, 374 375 { 0x131f, 0x2040, 0xffff, 0, 376 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 377 DEFAULT_RCLK, 378 PUC_PORT_1S2P, 0x10, -1, 0, 379 .config_function = puc_config_siig 380 }, 381 382 { 0x131f, 0x2041, 0xffff, 0, 383 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 384 DEFAULT_RCLK, 385 PUC_PORT_1S2P, 0x10, -1, 0, 386 .config_function = puc_config_siig 387 }, 388 389 { 0x131f, 0x2042, 0xffff, 0, 390 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 391 DEFAULT_RCLK, 392 PUC_PORT_1S2P, 0x10, -1, 0, 393 .config_function = puc_config_siig 394 }, 395 396 { 0x131f, 0x2050, 0xffff, 0, 397 "SIIG Cyber 4S PCI 16C550 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_4S, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2051, 0xffff, 0, 403 "SIIG Cyber 4S PCI 16C650 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_4S, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2052, 0xffff, 0, 409 "SIIG Cyber 4S PCI 16C850 (20x family)", 410 DEFAULT_RCLK, 411 PUC_PORT_4S, 0x10, 4, 0, 412 }, 413 414 { 0x131f, 0x2060, 0xffff, 0, 415 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S1P, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2061, 0xffff, 0, 421 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_2S1P, 0x10, 4, 0, 424 }, 425 426 { 0x131f, 0x2062, 0xffff, 0, 427 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 428 DEFAULT_RCLK, 429 PUC_PORT_2S1P, 0x10, 4, 0, 430 }, 431 432 { 0x131f, 0x2081, 0xffff, 0, 433 "SIIG PS8000 8S PCI 16C650 (20x family)", 434 DEFAULT_RCLK, 435 PUC_PORT_8S, 0x10, -1, -1, 436 .config_function = puc_config_siig 437 }, 438 439 { 0x135c, 0x0010, 0xffff, 0, 440 "Quatech QSC-100", 441 -3, /* max 8x clock rate */ 442 PUC_PORT_4S, 0x14, 0, 8, 443 .config_function = puc_config_quatech 444 }, 445 446 { 0x135c, 0x0020, 0xffff, 0, 447 "Quatech DSC-100", 448 -1, /* max 2x clock rate */ 449 PUC_PORT_2S, 0x14, 0, 8, 450 .config_function = puc_config_quatech 451 }, 452 453 { 0x135c, 0x0030, 0xffff, 0, 454 "Quatech DSC-200/300", 455 -1, /* max 2x clock rate */ 456 PUC_PORT_2S, 0x14, 0, 8, 457 .config_function = puc_config_quatech 458 }, 459 460 { 0x135c, 0x0040, 0xffff, 0, 461 "Quatech QSC-200/300", 462 -3, /* max 8x clock rate */ 463 PUC_PORT_4S, 0x14, 0, 8, 464 .config_function = puc_config_quatech 465 }, 466 467 { 0x135c, 0x0050, 0xffff, 0, 468 "Quatech ESC-100D", 469 -3, /* max 8x clock rate */ 470 PUC_PORT_8S, 0x14, 0, 8, 471 .config_function = puc_config_quatech 472 }, 473 474 { 0x135c, 0x0060, 0xffff, 0, 475 "Quatech ESC-100M", 476 -3, /* max 8x clock rate */ 477 PUC_PORT_8S, 0x14, 0, 8, 478 .config_function = puc_config_quatech 479 }, 480 481 { 0x135c, 0x0170, 0xffff, 0, 482 "Quatech QSCLP-100", 483 -1, /* max 2x clock rate */ 484 PUC_PORT_4S, 0x18, 0, 8, 485 .config_function = puc_config_quatech 486 }, 487 488 { 0x135c, 0x0180, 0xffff, 0, 489 "Quatech DSCLP-100", 490 -1, /* max 3x clock rate */ 491 PUC_PORT_2S, 0x18, 0, 8, 492 .config_function = puc_config_quatech 493 }, 494 495 { 0x135c, 0x01b0, 0xffff, 0, 496 "Quatech DSCLP-200/300", 497 -1, /* max 2x clock rate */ 498 PUC_PORT_2S, 0x18, 0, 8, 499 .config_function = puc_config_quatech 500 }, 501 502 { 0x135c, 0x01e0, 0xffff, 0, 503 "Quatech ESCLP-100", 504 -3, /* max 8x clock rate */ 505 PUC_PORT_8S, 0x10, 0, 8, 506 .config_function = puc_config_quatech 507 }, 508 509 { 0x1393, 0x1040, 0xffff, 0, 510 "Moxa Technologies, Smartio C104H/PCI", 511 DEFAULT_RCLK * 8, 512 PUC_PORT_4S, 0x18, 0, 8, 513 }, 514 515 { 0x1393, 0x1041, 0xffff, 0, 516 "Moxa Technologies, Smartio CP-104UL/PCI", 517 DEFAULT_RCLK * 8, 518 PUC_PORT_4S, 0x18, 0, 8, 519 }, 520 521 { 0x1393, 0x1043, 0xffff, 0, 522 "Moxa Technologies, Smartio CP-104EL/PCIe", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_4S, 0x18, 0, 8, 525 }, 526 527 { 0x1393, 0x1120, 0xffff, 0, 528 "Moxa Technologies, CP-112UL", 529 DEFAULT_RCLK * 8, 530 PUC_PORT_2S, 0x18, 0, 8, 531 }, 532 533 { 0x1393, 0x1141, 0xffff, 0, 534 "Moxa Technologies, Industio CP-114", 535 DEFAULT_RCLK * 8, 536 PUC_PORT_4S, 0x18, 0, 8, 537 }, 538 539 { 0x1393, 0x1680, 0xffff, 0, 540 "Moxa Technologies, C168H/PCI", 541 DEFAULT_RCLK * 8, 542 PUC_PORT_8S, 0x18, 0, 8, 543 }, 544 545 { 0x1393, 0x1681, 0xffff, 0, 546 "Moxa Technologies, C168U/PCI", 547 DEFAULT_RCLK * 8, 548 PUC_PORT_8S, 0x18, 0, 8, 549 }, 550 551 { 0x1393, 0x1682, 0xffff, 0, 552 "Moxa Technologies, CP-168EL/PCIe", 553 DEFAULT_RCLK * 8, 554 PUC_PORT_8S, 0x18, 0, 8, 555 }, 556 557 { 0x13a8, 0x0152, 0xffff, 0, 558 "Exar XR17C/D152", 559 DEFAULT_RCLK * 8, 560 PUC_PORT_2S, 0x10, 0, -1, 561 .config_function = puc_config_exar 562 }, 563 564 { 0x13a8, 0x0154, 0xffff, 0, 565 "Exar XR17C154", 566 DEFAULT_RCLK * 8, 567 PUC_PORT_4S, 0x10, 0, -1, 568 .config_function = puc_config_exar 569 }, 570 571 { 0x13a8, 0x0158, 0xffff, 0, 572 "Exar XR17C158", 573 DEFAULT_RCLK * 8, 574 PUC_PORT_8S, 0x10, 0, -1, 575 .config_function = puc_config_exar 576 }, 577 578 { 0x13a8, 0x0258, 0xffff, 0, 579 "Exar XR17V258IV", 580 DEFAULT_RCLK * 8, 581 PUC_PORT_8S, 0x10, 0, -1, 582 }, 583 584 { 0x1407, 0x0100, 0xffff, 0, 585 "Lava Computers Dual Serial", 586 DEFAULT_RCLK, 587 PUC_PORT_2S, 0x10, 4, 0, 588 }, 589 590 { 0x1407, 0x0101, 0xffff, 0, 591 "Lava Computers Quatro A", 592 DEFAULT_RCLK, 593 PUC_PORT_2S, 0x10, 4, 0, 594 }, 595 596 { 0x1407, 0x0102, 0xffff, 0, 597 "Lava Computers Quatro B", 598 DEFAULT_RCLK, 599 PUC_PORT_2S, 0x10, 4, 0, 600 }, 601 602 { 0x1407, 0x0120, 0xffff, 0, 603 "Lava Computers Quattro-PCI A", 604 DEFAULT_RCLK, 605 PUC_PORT_2S, 0x10, 4, 0, 606 }, 607 608 { 0x1407, 0x0121, 0xffff, 0, 609 "Lava Computers Quattro-PCI B", 610 DEFAULT_RCLK, 611 PUC_PORT_2S, 0x10, 4, 0, 612 }, 613 614 { 0x1407, 0x0180, 0xffff, 0, 615 "Lava Computers Octo A", 616 DEFAULT_RCLK, 617 PUC_PORT_4S, 0x10, 4, 0, 618 }, 619 620 { 0x1407, 0x0181, 0xffff, 0, 621 "Lava Computers Octo B", 622 DEFAULT_RCLK, 623 PUC_PORT_4S, 0x10, 4, 0, 624 }, 625 626 { 0x1409, 0x7268, 0xffff, 0, 627 "Sunix SUN1888", 628 0, 629 PUC_PORT_2P, 0x10, 0, 8, 630 }, 631 632 { 0x1409, 0x7168, 0xffff, 0, 633 NULL, 634 DEFAULT_RCLK * 8, 635 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 636 .config_function = puc_config_timedia 637 }, 638 639 /* 640 * Boards with an Oxford Semiconductor chip. 641 * 642 * Oxford Semiconductor provides documentation for their chip at: 643 * <URL:http://www.plxtech.com/products/uart/> 644 * 645 * As sold by Kouwell <URL:http://www.kouwell.com/>. 646 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 647 */ 648 649 { 0x1415, 0x9501, 0x131f, 0x2050, 650 "SIIG Cyber 4 PCI 16550", 651 DEFAULT_RCLK * 10, 652 PUC_PORT_4S, 0x10, 0, 8, 653 }, 654 655 { 0x1415, 0x9501, 0x131f, 0x2051, 656 "SIIG Cyber 4S PCI 16C650 (20x family)", 657 DEFAULT_RCLK * 10, 658 PUC_PORT_4S, 0x10, 0, 8, 659 }, 660 661 { 0x1415, 0x9501, 0x131f, 0x2052, 662 "SIIG Quartet Serial 850", 663 DEFAULT_RCLK * 10, 664 PUC_PORT_4S, 0x10, 0, 8, 665 }, 666 667 { 0x1415, 0x9501, 0x14db, 0x2150, 668 "Kuroutoshikou SERIAL4P-LPPCI2", 669 DEFAULT_RCLK * 10, 670 PUC_PORT_4S, 0x10, 0, 8, 671 }, 672 673 { 0x1415, 0x9501, 0xffff, 0, 674 "Oxford Semiconductor OX16PCI954 UARTs", 675 DEFAULT_RCLK, 676 PUC_PORT_4S, 0x10, 0, 8, 677 }, 678 679 { 0x1415, 0x950a, 0x131f, 0x2030, 680 "SIIG Cyber 2S PCIe", 681 DEFAULT_RCLK * 10, 682 PUC_PORT_2S, 0x10, 0, 8, 683 }, 684 685 { 0x1415, 0x950a, 0xffff, 0, 686 "Oxford Semiconductor OX16PCI954 UARTs", 687 DEFAULT_RCLK, 688 PUC_PORT_4S, 0x10, 0, 8, 689 }, 690 691 { 0x1415, 0x9511, 0xffff, 0, 692 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 693 DEFAULT_RCLK, 694 PUC_PORT_4S, 0x10, 0, 8, 695 }, 696 697 { 0x1415, 0x9521, 0xffff, 0, 698 "Oxford Semiconductor OX16PCI952 UARTs", 699 DEFAULT_RCLK, 700 PUC_PORT_2S, 0x10, 4, 0, 701 }, 702 703 { 0x1415, 0x9538, 0xffff, 0, 704 "Oxford Semiconductor OX16PCI958 UARTs", 705 DEFAULT_RCLK * 10, 706 PUC_PORT_8S, 0x18, 0, 8, 707 }, 708 709 /* 710 * Perle boards use Oxford Semiconductor chips, but they store the 711 * Oxford Semiconductor device ID as a subvendor device ID and use 712 * their own device IDs. 713 */ 714 715 { 0x155f, 0x0331, 0xffff, 0, 716 "Perle Speed4 LE", 717 DEFAULT_RCLK * 8, 718 PUC_PORT_4S, 0x10, 0, 8, 719 }, 720 721 /* 722 * Oxford Semiconductor PCI Express Expresso family 723 * 724 * Found in many 'native' PCI Express serial boards such as: 725 * 726 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 727 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 728 * 729 * Lindy 51189 (4 port) 730 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 731 * 732 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 733 * <URL:http://www.startech.com> 734 */ 735 736 { 0x1415, 0xc158, 0xffff, 0, 737 "Oxford Semiconductor OXPCIe952 UARTs", 738 DEFAULT_RCLK * 0x22, 739 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 740 .config_function = puc_config_oxford_pcie 741 }, 742 743 { 0x1415, 0xc15d, 0xffff, 0, 744 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 745 DEFAULT_RCLK * 0x22, 746 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 747 .config_function = puc_config_oxford_pcie 748 }, 749 750 { 0x1415, 0xc208, 0xffff, 0, 751 "Oxford Semiconductor OXPCIe954 UARTs", 752 DEFAULT_RCLK * 0x22, 753 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 754 .config_function = puc_config_oxford_pcie 755 }, 756 757 { 0x1415, 0xc20d, 0xffff, 0, 758 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 759 DEFAULT_RCLK * 0x22, 760 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 761 .config_function = puc_config_oxford_pcie 762 }, 763 764 { 0x1415, 0xc308, 0xffff, 0, 765 "Oxford Semiconductor OXPCIe958 UARTs", 766 DEFAULT_RCLK * 0x22, 767 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 768 .config_function = puc_config_oxford_pcie 769 }, 770 771 { 0x1415, 0xc30d, 0xffff, 0, 772 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 773 DEFAULT_RCLK * 0x22, 774 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 775 .config_function = puc_config_oxford_pcie 776 }, 777 778 { 0x14d2, 0x8010, 0xffff, 0, 779 "VScom PCI-100L", 780 DEFAULT_RCLK * 8, 781 PUC_PORT_1S, 0x14, 0, 0, 782 }, 783 784 { 0x14d2, 0x8020, 0xffff, 0, 785 "VScom PCI-200L", 786 DEFAULT_RCLK * 8, 787 PUC_PORT_2S, 0x14, 4, 0, 788 }, 789 790 { 0x14d2, 0x8028, 0xffff, 0, 791 "VScom 200Li", 792 DEFAULT_RCLK, 793 PUC_PORT_2S, 0x20, 0, 8, 794 }, 795 796 /* 797 * VScom (Titan?) PCI-800L. More modern variant of the 798 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 799 * two of them obviously implemented as macro cells in 800 * the ASIC. This causes the weird port access pattern 801 * below, where two of the IO port ranges each access 802 * one of the ASIC UARTs, and a block of IO addresses 803 * access the external UARTs. 804 */ 805 { 0x14d2, 0x8080, 0xffff, 0, 806 "Titan VScom PCI-800L", 807 DEFAULT_RCLK * 8, 808 PUC_PORT_8S, 0x14, -1, -1, 809 .config_function = puc_config_titan 810 }, 811 812 /* 813 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 814 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 815 * device ID 3 and PCI device 1 device ID 4. 816 */ 817 { 0x14d2, 0xa003, 0xffff, 0, 818 "Titan PCI-800H", 819 DEFAULT_RCLK * 8, 820 PUC_PORT_4S, 0x10, 0, 8, 821 }, 822 { 0x14d2, 0xa004, 0xffff, 0, 823 "Titan PCI-800H", 824 DEFAULT_RCLK * 8, 825 PUC_PORT_4S, 0x10, 0, 8, 826 }, 827 828 { 0x14d2, 0xa005, 0xffff, 0, 829 "Titan PCI-200H", 830 DEFAULT_RCLK * 8, 831 PUC_PORT_2S, 0x10, 0, 8, 832 }, 833 834 { 0x14d2, 0xe020, 0xffff, 0, 835 "Titan VScom PCI-200HV2", 836 DEFAULT_RCLK * 8, 837 PUC_PORT_2S, 0x10, 4, 0, 838 }, 839 840 { 0x14db, 0x2130, 0xffff, 0, 841 "Avlab Technology, PCI IO 2S", 842 DEFAULT_RCLK, 843 PUC_PORT_2S, 0x10, 4, 0, 844 }, 845 846 { 0x14db, 0x2150, 0xffff, 0, 847 "Avlab Low Profile PCI 4 Serial", 848 DEFAULT_RCLK, 849 PUC_PORT_4S, 0x10, 4, 0, 850 }, 851 852 { 0x14db, 0x2152, 0xffff, 0, 853 "Avlab Low Profile PCI 4 Serial", 854 DEFAULT_RCLK, 855 PUC_PORT_4S, 0x10, 4, 0, 856 }, 857 858 { 0x1592, 0x0781, 0xffff, 0, 859 "Syba Tech Ltd. PCI-4S2P-550-ECP", 860 DEFAULT_RCLK, 861 PUC_PORT_4S1P, 0x10, 0, -1, 862 .config_function = puc_config_syba 863 }, 864 865 { 0x6666, 0x0001, 0xffff, 0, 866 "Decision Computer Inc, PCCOM 4-port serial", 867 DEFAULT_RCLK, 868 PUC_PORT_4S, 0x1c, 0, 8, 869 }, 870 871 { 0x6666, 0x0002, 0xffff, 0, 872 "Decision Computer Inc, PCCOM 8-port serial", 873 DEFAULT_RCLK, 874 PUC_PORT_8S, 0x1c, 0, 8, 875 }, 876 877 { 0x6666, 0x0004, 0xffff, 0, 878 "PCCOM dual port RS232/422/485", 879 DEFAULT_RCLK, 880 PUC_PORT_2S, 0x1c, 0, 8, 881 }, 882 883 { 0x9710, 0x9815, 0xffff, 0, 884 "NetMos NM9815 Dual 1284 Printer port", 885 0, 886 PUC_PORT_2P, 0x10, 8, 0, 887 }, 888 889 /* 890 * This is more specific than the generic NM9835 entry that follows, and 891 * is placed here to _prevent_ puc from claiming this single port card. 892 * 893 * uart(4) will claim this device. 894 */ 895 { 0x9710, 0x9835, 0x1000, 1, 896 "NetMos NM9835 based 1-port serial", 897 DEFAULT_RCLK, 898 PUC_PORT_1S, 0x10, 4, 0, 899 }, 900 901 { 0x9710, 0x9835, 0x1000, 2, 902 "NetMos NM9835 based 2-port serial", 903 DEFAULT_RCLK, 904 PUC_PORT_2S, 0x10, 4, 0, 905 }, 906 907 { 0x9710, 0x9835, 0xffff, 0, 908 "NetMos NM9835 Dual UART and 1284 Printer port", 909 DEFAULT_RCLK, 910 PUC_PORT_2S1P, 0x10, 4, 0, 911 }, 912 913 { 0x9710, 0x9845, 0x1000, 0x0006, 914 "NetMos NM9845 6 Port UART", 915 DEFAULT_RCLK, 916 PUC_PORT_6S, 0x10, 4, 0, 917 }, 918 919 { 0x9710, 0x9845, 0xffff, 0, 920 "NetMos NM9845 Quad UART and 1284 Printer port", 921 DEFAULT_RCLK, 922 PUC_PORT_4S1P, 0x10, 4, 0, 923 }, 924 925 { 0x9710, 0x9865, 0xa000, 0x3002, 926 "NetMos NM9865 Dual UART", 927 DEFAULT_RCLK, 928 PUC_PORT_2S, 0x10, 4, 0, 929 }, 930 931 { 0x9710, 0x9865, 0xa000, 0x3003, 932 "NetMos NM9865 Triple UART", 933 DEFAULT_RCLK, 934 PUC_PORT_3S, 0x10, 4, 0, 935 }, 936 937 { 0x9710, 0x9865, 0xa000, 0x3004, 938 "NetMos NM9865 Quad UART", 939 DEFAULT_RCLK, 940 PUC_PORT_4S, 0x10, 4, 0,0 941 }, 942 943 { 0x9710, 0x9865, 0xa000, 0x3011, 944 "NetMos NM9865 Single UART and 1284 Printer port", 945 DEFAULT_RCLK, 946 PUC_PORT_1S1P, 0x10, 4, 0, 947 }, 948 949 { 0x9710, 0x9865, 0xa000, 0x3012, 950 "NetMos NM9865 Dual UART and 1284 Printer port", 951 DEFAULT_RCLK, 952 PUC_PORT_2S1P, 0x10, 4, 0, 953 }, 954 955 { 0x9710, 0x9865, 0xa000, 0x3020, 956 "NetMos NM9865 Dual 1284 Printer port", 957 DEFAULT_RCLK, 958 PUC_PORT_2P, 0x10, 4, 0, 959 }, 960 961 { 0xb00c, 0x021c, 0xffff, 0, 962 "IC Book Labs Gunboat x4 Lite", 963 DEFAULT_RCLK, 964 PUC_PORT_4S, 0x10, 0, 8, 965 .config_function = puc_config_icbook 966 }, 967 968 { 0xb00c, 0x031c, 0xffff, 0, 969 "IC Book Labs Gunboat x4 Pro", 970 DEFAULT_RCLK, 971 PUC_PORT_4S, 0x10, 0, 8, 972 .config_function = puc_config_icbook 973 }, 974 975 { 0xb00c, 0x041c, 0xffff, 0, 976 "IC Book Labs Ironclad x8 Lite", 977 DEFAULT_RCLK, 978 PUC_PORT_8S, 0x10, 0, 8, 979 .config_function = puc_config_icbook 980 }, 981 982 { 0xb00c, 0x051c, 0xffff, 0, 983 "IC Book Labs Ironclad x8 Pro", 984 DEFAULT_RCLK, 985 PUC_PORT_8S, 0x10, 0, 8, 986 .config_function = puc_config_icbook 987 }, 988 989 { 0xb00c, 0x081c, 0xffff, 0, 990 "IC Book Labs Dreadnought x16 Pro", 991 DEFAULT_RCLK * 8, 992 PUC_PORT_16S, 0x10, 0, 8, 993 .config_function = puc_config_icbook 994 }, 995 996 { 0xb00c, 0x091c, 0xffff, 0, 997 "IC Book Labs Dreadnought x16 Lite", 998 DEFAULT_RCLK, 999 PUC_PORT_16S, 0x10, 0, 8, 1000 .config_function = puc_config_icbook 1001 }, 1002 1003 { 0xb00c, 0x0a1c, 0xffff, 0, 1004 "IC Book Labs Gunboat x2 Low Profile", 1005 DEFAULT_RCLK, 1006 PUC_PORT_2S, 0x10, 0, 8, 1007 }, 1008 1009 { 0xb00c, 0x0b1c, 0xffff, 0, 1010 "IC Book Labs Gunboat x4 Low Profile", 1011 DEFAULT_RCLK, 1012 PUC_PORT_4S, 0x10, 0, 8, 1013 .config_function = puc_config_icbook 1014 }, 1015 1016 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1017 }; 1018 1019 static int 1020 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1021 intptr_t *res) 1022 { 1023 switch (cmd) { 1024 case PUC_CFG_GET_OFS: 1025 *res = 8 * (port & 1); 1026 return (0); 1027 case PUC_CFG_GET_RID: 1028 *res = 0x14 + (port >> 1) * 4; 1029 return (0); 1030 default: 1031 break; 1032 } 1033 return (ENXIO); 1034 } 1035 1036 static int 1037 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1038 intptr_t *res) 1039 { 1040 const struct puc_cfg *cfg = sc->sc_cfg; 1041 1042 if (cmd == PUC_CFG_GET_OFS) { 1043 if (cfg->subdevice == 0x1282) /* Everest SP */ 1044 port <<= 1; 1045 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1046 port = (port == 3) ? 4 : port; 1047 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1048 return (0); 1049 } 1050 return (ENXIO); 1051 } 1052 1053 static int 1054 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1055 intptr_t *res) 1056 { 1057 if (cmd == PUC_CFG_GET_OFS) { 1058 *res = port * 0x200; 1059 return (0); 1060 } 1061 return (ENXIO); 1062 } 1063 1064 static int 1065 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1066 intptr_t *res) 1067 { 1068 if (cmd == PUC_CFG_GET_ILR) { 1069 *res = PUC_ILR_DIGI; 1070 return (0); 1071 } 1072 return (ENXIO); 1073 } 1074 1075 static int 1076 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1077 intptr_t *res) 1078 { 1079 const struct puc_cfg *cfg = sc->sc_cfg; 1080 struct puc_bar *bar; 1081 uint8_t v0, v1; 1082 1083 switch (cmd) { 1084 case PUC_CFG_SETUP: 1085 /* 1086 * Check if the scratchpad register is enabled or if the 1087 * interrupt status and options registers are active. 1088 */ 1089 bar = puc_get_bar(sc, cfg->rid); 1090 if (bar == NULL) 1091 return (ENXIO); 1092 /* Set DLAB in the LCR register of UART 0. */ 1093 bus_write_1(bar->b_res, 3, 0x80); 1094 /* Write 0 to the SPR register of UART 0. */ 1095 bus_write_1(bar->b_res, 7, 0); 1096 /* Read back the contents of the SPR register of UART 0. */ 1097 v0 = bus_read_1(bar->b_res, 7); 1098 /* Write a specific value to the SPR register of UART 0. */ 1099 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1100 /* Read back the contents of the SPR register of UART 0. */ 1101 v1 = bus_read_1(bar->b_res, 7); 1102 /* Clear DLAB in the LCR register of UART 0. */ 1103 bus_write_1(bar->b_res, 3, 0); 1104 /* Save the two values read-back from the SPR register. */ 1105 sc->sc_cfg_data = (v0 << 8) | v1; 1106 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1107 /* 1108 * The SPR register echoed the two values written 1109 * by us. This means that the SPAD jumper is set. 1110 */ 1111 device_printf(sc->sc_dev, "warning: extra features " 1112 "not usable -- SPAD compatibility enabled\n"); 1113 return (0); 1114 } 1115 if (v0 != 0) { 1116 /* 1117 * The first value doesn't match. This can only mean 1118 * that the SPAD jumper is not set and that a non- 1119 * standard fixed clock multiplier jumper is set. 1120 */ 1121 if (bootverbose) 1122 device_printf(sc->sc_dev, "fixed clock rate " 1123 "multiplier of %d\n", 1 << v0); 1124 if (v0 < -cfg->clock) 1125 device_printf(sc->sc_dev, "warning: " 1126 "suboptimal fixed clock rate multiplier " 1127 "setting\n"); 1128 return (0); 1129 } 1130 /* 1131 * The first value matched, but the second didn't. We know 1132 * that the SPAD jumper is not set. We also know that the 1133 * clock rate multiplier is software controlled *and* that 1134 * we just programmed it to the maximum allowed. 1135 */ 1136 if (bootverbose) 1137 device_printf(sc->sc_dev, "clock rate multiplier of " 1138 "%d selected\n", 1 << -cfg->clock); 1139 return (0); 1140 case PUC_CFG_GET_CLOCK: 1141 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1142 v1 = sc->sc_cfg_data & 0xff; 1143 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1144 /* 1145 * XXX With the SPAD jumper applied, there's no 1146 * easy way of knowing if there's also a clock 1147 * rate multiplier jumper installed. Let's hope 1148 * not... 1149 */ 1150 *res = DEFAULT_RCLK; 1151 } else if (v0 == 0) { 1152 /* 1153 * No clock rate multiplier jumper installed, 1154 * so we programmed the board with the maximum 1155 * multiplier allowed as given to us in the 1156 * clock field of the config record (negated). 1157 */ 1158 *res = DEFAULT_RCLK << -cfg->clock; 1159 } else 1160 *res = DEFAULT_RCLK << v0; 1161 return (0); 1162 case PUC_CFG_GET_ILR: 1163 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1164 v1 = sc->sc_cfg_data & 0xff; 1165 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1166 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1167 return (0); 1168 default: 1169 break; 1170 } 1171 return (ENXIO); 1172 } 1173 1174 static int 1175 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1176 intptr_t *res) 1177 { 1178 static int base[] = { 0x251, 0x3f0, 0 }; 1179 const struct puc_cfg *cfg = sc->sc_cfg; 1180 struct puc_bar *bar; 1181 int efir, idx, ofs; 1182 uint8_t v; 1183 1184 switch (cmd) { 1185 case PUC_CFG_SETUP: 1186 bar = puc_get_bar(sc, cfg->rid); 1187 if (bar == NULL) 1188 return (ENXIO); 1189 1190 /* configure both W83877TFs */ 1191 bus_write_1(bar->b_res, 0x250, 0x89); 1192 bus_write_1(bar->b_res, 0x3f0, 0x87); 1193 bus_write_1(bar->b_res, 0x3f0, 0x87); 1194 idx = 0; 1195 while (base[idx] != 0) { 1196 efir = base[idx]; 1197 bus_write_1(bar->b_res, efir, 0x09); 1198 v = bus_read_1(bar->b_res, efir + 1); 1199 if ((v & 0x0f) != 0x0c) 1200 return (ENXIO); 1201 bus_write_1(bar->b_res, efir, 0x16); 1202 v = bus_read_1(bar->b_res, efir + 1); 1203 bus_write_1(bar->b_res, efir, 0x16); 1204 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1205 bus_write_1(bar->b_res, efir, 0x16); 1206 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1207 ofs = base[idx] & 0x300; 1208 bus_write_1(bar->b_res, efir, 0x23); 1209 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1210 bus_write_1(bar->b_res, efir, 0x24); 1211 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1212 bus_write_1(bar->b_res, efir, 0x25); 1213 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1214 bus_write_1(bar->b_res, efir, 0x17); 1215 bus_write_1(bar->b_res, efir + 1, 0x03); 1216 bus_write_1(bar->b_res, efir, 0x28); 1217 bus_write_1(bar->b_res, efir + 1, 0x43); 1218 idx++; 1219 } 1220 bus_write_1(bar->b_res, 0x250, 0xaa); 1221 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1222 return (0); 1223 case PUC_CFG_GET_OFS: 1224 switch (port) { 1225 case 0: 1226 *res = 0x2f8; 1227 return (0); 1228 case 1: 1229 *res = 0x2e8; 1230 return (0); 1231 case 2: 1232 *res = 0x3f8; 1233 return (0); 1234 case 3: 1235 *res = 0x3e8; 1236 return (0); 1237 case 4: 1238 *res = 0x278; 1239 return (0); 1240 } 1241 break; 1242 default: 1243 break; 1244 } 1245 return (ENXIO); 1246 } 1247 1248 static int 1249 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1250 intptr_t *res) 1251 { 1252 const struct puc_cfg *cfg = sc->sc_cfg; 1253 1254 switch (cmd) { 1255 case PUC_CFG_GET_OFS: 1256 if (cfg->ports == PUC_PORT_8S) { 1257 *res = (port > 4) ? 8 * (port - 4) : 0; 1258 return (0); 1259 } 1260 break; 1261 case PUC_CFG_GET_RID: 1262 if (cfg->ports == PUC_PORT_8S) { 1263 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1264 return (0); 1265 } 1266 if (cfg->ports == PUC_PORT_2S1P) { 1267 switch (port) { 1268 case 0: *res = 0x10; return (0); 1269 case 1: *res = 0x14; return (0); 1270 case 2: *res = 0x1c; return (0); 1271 } 1272 } 1273 break; 1274 default: 1275 break; 1276 } 1277 return (ENXIO); 1278 } 1279 1280 static int 1281 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1282 intptr_t *res) 1283 { 1284 static uint16_t dual[] = { 1285 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1286 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1287 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1288 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1289 0xD079, 0 1290 }; 1291 static uint16_t quad[] = { 1292 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1293 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1294 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1295 0xB157, 0 1296 }; 1297 static uint16_t octa[] = { 1298 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1299 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1300 }; 1301 static struct { 1302 int ports; 1303 uint16_t *ids; 1304 } subdevs[] = { 1305 { 2, dual }, 1306 { 4, quad }, 1307 { 8, octa }, 1308 { 0, NULL } 1309 }; 1310 static char desc[64]; 1311 int dev, id; 1312 uint16_t subdev; 1313 1314 switch (cmd) { 1315 case PUC_CFG_GET_CLOCK: 1316 if (port < 2) 1317 *res = DEFAULT_RCLK * 8; 1318 else 1319 *res = DEFAULT_RCLK; 1320 return (0); 1321 case PUC_CFG_GET_DESC: 1322 snprintf(desc, sizeof(desc), 1323 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1324 *res = (intptr_t)desc; 1325 return (0); 1326 case PUC_CFG_GET_NPORTS: 1327 subdev = pci_get_subdevice(sc->sc_dev); 1328 dev = 0; 1329 while (subdevs[dev].ports != 0) { 1330 id = 0; 1331 while (subdevs[dev].ids[id] != 0) { 1332 if (subdev == subdevs[dev].ids[id]) { 1333 sc->sc_cfg_data = subdevs[dev].ports; 1334 *res = sc->sc_cfg_data; 1335 return (0); 1336 } 1337 id++; 1338 } 1339 dev++; 1340 } 1341 return (ENXIO); 1342 case PUC_CFG_GET_OFS: 1343 *res = (port == 1 || port == 3) ? 8 : 0; 1344 return (0); 1345 case PUC_CFG_GET_RID: 1346 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1347 return (0); 1348 case PUC_CFG_GET_TYPE: 1349 *res = PUC_TYPE_SERIAL; 1350 return (0); 1351 default: 1352 break; 1353 } 1354 return (ENXIO); 1355 } 1356 1357 static int 1358 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1359 intptr_t *res) 1360 { 1361 const struct puc_cfg *cfg = sc->sc_cfg; 1362 int idx; 1363 struct puc_bar *bar; 1364 uint8_t value; 1365 1366 switch (cmd) { 1367 case PUC_CFG_SETUP: 1368 device_printf(sc->sc_dev, "%d UARTs detected\n", 1369 sc->sc_nports); 1370 1371 /* Set UARTs to enhanced mode */ 1372 bar = puc_get_bar(sc, cfg->rid); 1373 if (bar == NULL) 1374 return (ENXIO); 1375 for (idx = 0; idx < sc->sc_nports; idx++) { 1376 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1377 0x92); 1378 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1379 value | 0x10); 1380 } 1381 return (0); 1382 case PUC_CFG_GET_LEN: 1383 *res = 0x200; 1384 return (0); 1385 case PUC_CFG_GET_NPORTS: 1386 /* 1387 * Check if we are being called from puc_bfe_attach() 1388 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1389 * puc_get_bar(), so we return a value of 16. This has cosmetic 1390 * side-effects at worst; in PUC_CFG_GET_DESC, 1391 * (int)sc->sc_cfg_data will not contain the true number of 1392 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1393 * call for this device family anyway. 1394 * 1395 * The check is for initialisation of sc->sc_bar[idx], which is 1396 * only done in puc_bfe_attach(). 1397 */ 1398 idx = 0; 1399 do { 1400 if (sc->sc_bar[idx++].b_rid != -1) { 1401 sc->sc_cfg_data = 16; 1402 *res = sc->sc_cfg_data; 1403 return (0); 1404 } 1405 } while (idx < PUC_PCI_BARS); 1406 1407 bar = puc_get_bar(sc, cfg->rid); 1408 if (bar == NULL) 1409 return (ENXIO); 1410 1411 value = bus_read_1(bar->b_res, 0x04); 1412 if (value == 0) 1413 return (ENXIO); 1414 1415 sc->sc_cfg_data = value; 1416 *res = sc->sc_cfg_data; 1417 return (0); 1418 case PUC_CFG_GET_OFS: 1419 *res = 0x1000 + (port << 9); 1420 return (0); 1421 case PUC_CFG_GET_TYPE: 1422 *res = PUC_TYPE_SERIAL; 1423 return (0); 1424 default: 1425 break; 1426 } 1427 return (ENXIO); 1428 } 1429 1430 static int 1431 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1432 intptr_t *res) 1433 { 1434 switch (cmd) { 1435 case PUC_CFG_GET_OFS: 1436 *res = (port < 3) ? 0 : (port - 2) << 3; 1437 return (0); 1438 case PUC_CFG_GET_RID: 1439 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1440 return (0); 1441 default: 1442 break; 1443 } 1444 return (ENXIO); 1445 } 1446