1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_cronyx; 52 static puc_config_f puc_config_diva; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_quatech; 55 static puc_config_f puc_config_syba; 56 static puc_config_f puc_config_siig; 57 static puc_config_f puc_config_timedia; 58 static puc_config_f puc_config_titan; 59 static puc_config_f puc_config_oxford_pcie; 60 61 const struct puc_cfg puc_pci_devices[] = { 62 63 { 0x0009, 0x7168, 0xffff, 0, 64 "Sunix SUN1889", 65 DEFAULT_RCLK * 8, 66 PUC_PORT_2S, 0x10, 0, 8, 67 }, 68 69 { 0x103c, 0x1048, 0x103c, 0x1049, 70 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 71 DEFAULT_RCLK, 72 PUC_PORT_3S, 0x10, 0, -1, 73 .config_function = puc_config_diva 74 }, 75 76 { 0x103c, 0x1048, 0x103c, 0x104a, 77 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 78 DEFAULT_RCLK, 79 PUC_PORT_2S, 0x10, 0, -1, 80 .config_function = puc_config_diva 81 }, 82 83 { 0x103c, 0x1048, 0x103c, 0x104b, 84 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 85 DEFAULT_RCLK, 86 PUC_PORT_4S, 0x10, 0, -1, 87 .config_function = puc_config_diva 88 }, 89 90 { 0x103c, 0x1048, 0x103c, 0x1223, 91 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 92 DEFAULT_RCLK, 93 PUC_PORT_3S, 0x10, 0, -1, 94 .config_function = puc_config_diva 95 }, 96 97 { 0x103c, 0x1048, 0x103c, 0x1226, 98 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 99 DEFAULT_RCLK, 100 PUC_PORT_3S, 0x10, 0, -1, 101 .config_function = puc_config_diva 102 }, 103 104 { 0x103c, 0x1048, 0x103c, 0x1282, 105 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 106 DEFAULT_RCLK, 107 PUC_PORT_3S, 0x10, 0, -1, 108 .config_function = puc_config_diva 109 }, 110 111 { 0x10b5, 0x1076, 0x10b5, 0x1076, 112 "VScom PCI-800", 113 DEFAULT_RCLK * 8, 114 PUC_PORT_8S, 0x18, 0, 8, 115 }, 116 117 { 0x10b5, 0x1077, 0x10b5, 0x1077, 118 "VScom PCI-400", 119 DEFAULT_RCLK * 8, 120 PUC_PORT_4S, 0x18, 0, 8, 121 }, 122 123 { 0x10b5, 0x1103, 0x10b5, 0x1103, 124 "VScom PCI-200", 125 DEFAULT_RCLK * 8, 126 PUC_PORT_2S, 0x18, 4, 0, 127 }, 128 129 /* 130 * Boca Research Turbo Serial 658 (8 serial port) card. 131 * Appears to be the same as Chase Research PLC PCI-FAST8 132 * and Perle PCI-FAST8 Multi-Port serial cards. 133 */ 134 { 0x10b5, 0x9050, 0x12e0, 0x0021, 135 "Boca Research Turbo Serial 658", 136 DEFAULT_RCLK * 4, 137 PUC_PORT_8S, 0x18, 0, 8, 138 }, 139 140 { 0x10b5, 0x9050, 0x12e0, 0x0031, 141 "Boca Research Turbo Serial 654", 142 DEFAULT_RCLK * 4, 143 PUC_PORT_4S, 0x18, 0, 8, 144 }, 145 146 /* 147 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 148 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 149 * into the subsystem fields, and claims that it's a 150 * network/misc (0x02/0x80) device. 151 */ 152 { 0x10b5, 0x9050, 0xd84d, 0x6808, 153 "Dolphin Peripherals 4035", 154 DEFAULT_RCLK, 155 PUC_PORT_2S, 0x18, 4, 0, 156 }, 157 158 /* 159 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 160 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 161 * into the subsystem fields, and claims that it's a 162 * network/misc (0x02/0x80) device. 163 */ 164 { 0x10b5, 0x9050, 0xd84d, 0x6810, 165 "Dolphin Peripherals 4014", 166 0, 167 PUC_PORT_2P, 0x20, 4, 0, 168 }, 169 170 { 0x10e8, 0x818e, 0xffff, 0, 171 "Applied Micro Circuits 8 Port UART", 172 DEFAULT_RCLK, 173 PUC_PORT_8S, 0x14, -1, -1, 174 .config_function = puc_config_amc 175 }, 176 177 { 0x11fe, 0x8010, 0xffff, 0, 178 "Comtrol RocketPort 550/8 RJ11 part A", 179 DEFAULT_RCLK * 4, 180 PUC_PORT_4S, 0x10, 0, 8, 181 }, 182 183 { 0x11fe, 0x8011, 0xffff, 0, 184 "Comtrol RocketPort 550/8 RJ11 part B", 185 DEFAULT_RCLK * 4, 186 PUC_PORT_4S, 0x10, 0, 8, 187 }, 188 189 { 0x11fe, 0x8012, 0xffff, 0, 190 "Comtrol RocketPort 550/8 Octa part A", 191 DEFAULT_RCLK * 4, 192 PUC_PORT_4S, 0x10, 0, 8, 193 }, 194 195 { 0x11fe, 0x8013, 0xffff, 0, 196 "Comtrol RocketPort 550/8 Octa part B", 197 DEFAULT_RCLK * 4, 198 PUC_PORT_4S, 0x10, 0, 8, 199 }, 200 201 { 0x11fe, 0x8014, 0xffff, 0, 202 "Comtrol RocketPort 550/4 RJ45", 203 DEFAULT_RCLK * 4, 204 PUC_PORT_4S, 0x10, 0, 8, 205 }, 206 207 { 0x11fe, 0x8015, 0xffff, 0, 208 "Comtrol RocketPort 550/Quad", 209 DEFAULT_RCLK * 4, 210 PUC_PORT_4S, 0x10, 0, 8, 211 }, 212 213 { 0x11fe, 0x8016, 0xffff, 0, 214 "Comtrol RocketPort 550/16 part A", 215 DEFAULT_RCLK * 4, 216 PUC_PORT_4S, 0x10, 0, 8, 217 }, 218 219 { 0x11fe, 0x8017, 0xffff, 0, 220 "Comtrol RocketPort 550/16 part B", 221 DEFAULT_RCLK * 4, 222 PUC_PORT_12S, 0x10, 0, 8, 223 }, 224 225 { 0x11fe, 0x8018, 0xffff, 0, 226 "Comtrol RocketPort 550/8 part A", 227 DEFAULT_RCLK * 4, 228 PUC_PORT_4S, 0x10, 0, 8, 229 }, 230 231 { 0x11fe, 0x8019, 0xffff, 0, 232 "Comtrol RocketPort 550/8 part B", 233 DEFAULT_RCLK * 4, 234 PUC_PORT_4S, 0x10, 0, 8, 235 }, 236 237 /* 238 * IBM SurePOS 300 Series (481033H) serial ports 239 * Details can be found on the IBM RSS websites 240 */ 241 242 { 0x1014, 0x0297, 0xffff, 0, 243 "IBM SurePOS 300 Series (481033H) serial ports", 244 DEFAULT_RCLK, 245 PUC_PORT_4S, 0x10, 4, 0 246 }, 247 248 /* 249 * SIIG Boards. 250 * 251 * SIIG provides documentation for their boards at: 252 * <URL:http://www.siig.com/downloads.asp> 253 */ 254 255 { 0x131f, 0x1010, 0xffff, 0, 256 "SIIG Cyber I/O PCI 16C550 (10x family)", 257 DEFAULT_RCLK, 258 PUC_PORT_1S1P, 0x18, 4, 0, 259 }, 260 261 { 0x131f, 0x1011, 0xffff, 0, 262 "SIIG Cyber I/O PCI 16C650 (10x family)", 263 DEFAULT_RCLK, 264 PUC_PORT_1S1P, 0x18, 4, 0, 265 }, 266 267 { 0x131f, 0x1012, 0xffff, 0, 268 "SIIG Cyber I/O PCI 16C850 (10x family)", 269 DEFAULT_RCLK, 270 PUC_PORT_1S1P, 0x18, 4, 0, 271 }, 272 273 { 0x131f, 0x1021, 0xffff, 0, 274 "SIIG Cyber Parallel Dual PCI (10x family)", 275 0, 276 PUC_PORT_2P, 0x18, 8, 0, 277 }, 278 279 { 0x131f, 0x1030, 0xffff, 0, 280 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 281 DEFAULT_RCLK, 282 PUC_PORT_2S, 0x18, 4, 0, 283 }, 284 285 { 0x131f, 0x1031, 0xffff, 0, 286 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 287 DEFAULT_RCLK, 288 PUC_PORT_2S, 0x18, 4, 0, 289 }, 290 291 { 0x131f, 0x1032, 0xffff, 0, 292 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 293 DEFAULT_RCLK, 294 PUC_PORT_2S, 0x18, 4, 0, 295 }, 296 297 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 298 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 299 DEFAULT_RCLK, 300 PUC_PORT_2S1P, 0x18, 4, 0, 301 }, 302 303 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 304 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 305 DEFAULT_RCLK, 306 PUC_PORT_2S1P, 0x18, 4, 0, 307 }, 308 309 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 310 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 311 DEFAULT_RCLK, 312 PUC_PORT_2S1P, 0x18, 4, 0, 313 }, 314 315 { 0x131f, 0x1050, 0xffff, 0, 316 "SIIG Cyber 4S PCI 16C550 (10x family)", 317 DEFAULT_RCLK, 318 PUC_PORT_4S, 0x18, 4, 0, 319 }, 320 321 { 0x131f, 0x1051, 0xffff, 0, 322 "SIIG Cyber 4S PCI 16C650 (10x family)", 323 DEFAULT_RCLK, 324 PUC_PORT_4S, 0x18, 4, 0, 325 }, 326 327 { 0x131f, 0x1052, 0xffff, 0, 328 "SIIG Cyber 4S PCI 16C850 (10x family)", 329 DEFAULT_RCLK, 330 PUC_PORT_4S, 0x18, 4, 0, 331 }, 332 333 { 0x131f, 0x2010, 0xffff, 0, 334 "SIIG Cyber I/O PCI 16C550 (20x family)", 335 DEFAULT_RCLK, 336 PUC_PORT_1S1P, 0x10, 4, 0, 337 }, 338 339 { 0x131f, 0x2011, 0xffff, 0, 340 "SIIG Cyber I/O PCI 16C650 (20x family)", 341 DEFAULT_RCLK, 342 PUC_PORT_1S1P, 0x10, 4, 0, 343 }, 344 345 { 0x131f, 0x2012, 0xffff, 0, 346 "SIIG Cyber I/O PCI 16C850 (20x family)", 347 DEFAULT_RCLK, 348 PUC_PORT_1S1P, 0x10, 4, 0, 349 }, 350 351 { 0x131f, 0x2021, 0xffff, 0, 352 "SIIG Cyber Parallel Dual PCI (20x family)", 353 0, 354 PUC_PORT_2P, 0x10, 8, 0, 355 }, 356 357 { 0x131f, 0x2030, 0xffff, 0, 358 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 359 DEFAULT_RCLK, 360 PUC_PORT_2S, 0x10, 4, 0, 361 }, 362 363 { 0x131f, 0x2031, 0xffff, 0, 364 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 365 DEFAULT_RCLK, 366 PUC_PORT_2S, 0x10, 4, 0, 367 }, 368 369 { 0x131f, 0x2032, 0xffff, 0, 370 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 371 DEFAULT_RCLK, 372 PUC_PORT_2S, 0x10, 4, 0, 373 }, 374 375 { 0x131f, 0x2040, 0xffff, 0, 376 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 377 DEFAULT_RCLK, 378 PUC_PORT_1S2P, 0x10, -1, 0, 379 .config_function = puc_config_siig 380 }, 381 382 { 0x131f, 0x2041, 0xffff, 0, 383 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 384 DEFAULT_RCLK, 385 PUC_PORT_1S2P, 0x10, -1, 0, 386 .config_function = puc_config_siig 387 }, 388 389 { 0x131f, 0x2042, 0xffff, 0, 390 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 391 DEFAULT_RCLK, 392 PUC_PORT_1S2P, 0x10, -1, 0, 393 .config_function = puc_config_siig 394 }, 395 396 { 0x131f, 0x2050, 0xffff, 0, 397 "SIIG Cyber 4S PCI 16C550 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_4S, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2051, 0xffff, 0, 403 "SIIG Cyber 4S PCI 16C650 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_4S, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2052, 0xffff, 0, 409 "SIIG Cyber 4S PCI 16C850 (20x family)", 410 DEFAULT_RCLK, 411 PUC_PORT_4S, 0x10, 4, 0, 412 }, 413 414 { 0x131f, 0x2060, 0xffff, 0, 415 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S1P, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2061, 0xffff, 0, 421 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_2S1P, 0x10, 4, 0, 424 }, 425 426 { 0x131f, 0x2062, 0xffff, 0, 427 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 428 DEFAULT_RCLK, 429 PUC_PORT_2S1P, 0x10, 4, 0, 430 }, 431 432 { 0x131f, 0x2081, 0xffff, 0, 433 "SIIG PS8000 8S PCI 16C650 (20x family)", 434 DEFAULT_RCLK, 435 PUC_PORT_8S, 0x10, -1, -1, 436 .config_function = puc_config_siig 437 }, 438 439 { 0x135c, 0x0010, 0xffff, 0, 440 "Quatech QSC-100", 441 -3, /* max 8x clock rate */ 442 PUC_PORT_4S, 0x14, 0, 8, 443 .config_function = puc_config_quatech 444 }, 445 446 { 0x135c, 0x0020, 0xffff, 0, 447 "Quatech DSC-100", 448 -1, /* max 2x clock rate */ 449 PUC_PORT_2S, 0x14, 0, 8, 450 .config_function = puc_config_quatech 451 }, 452 453 { 0x135c, 0x0030, 0xffff, 0, 454 "Quatech DSC-200/300", 455 -1, /* max 2x clock rate */ 456 PUC_PORT_2S, 0x14, 0, 8, 457 .config_function = puc_config_quatech 458 }, 459 460 { 0x135c, 0x0040, 0xffff, 0, 461 "Quatech QSC-200/300", 462 -3, /* max 8x clock rate */ 463 PUC_PORT_4S, 0x14, 0, 8, 464 .config_function = puc_config_quatech 465 }, 466 467 { 0x135c, 0x0050, 0xffff, 0, 468 "Quatech ESC-100D", 469 -3, /* max 8x clock rate */ 470 PUC_PORT_8S, 0x14, 0, 8, 471 .config_function = puc_config_quatech 472 }, 473 474 { 0x135c, 0x0060, 0xffff, 0, 475 "Quatech ESC-100M", 476 -3, /* max 8x clock rate */ 477 PUC_PORT_8S, 0x14, 0, 8, 478 .config_function = puc_config_quatech 479 }, 480 481 { 0x135c, 0x0170, 0xffff, 0, 482 "Quatech QSCLP-100", 483 -1, /* max 2x clock rate */ 484 PUC_PORT_4S, 0x18, 0, 8, 485 .config_function = puc_config_quatech 486 }, 487 488 { 0x135c, 0x0180, 0xffff, 0, 489 "Quatech DSCLP-100", 490 -1, /* max 3x clock rate */ 491 PUC_PORT_2S, 0x18, 0, 8, 492 .config_function = puc_config_quatech 493 }, 494 495 { 0x135c, 0x01b0, 0xffff, 0, 496 "Quatech DSCLP-200/300", 497 -1, /* max 2x clock rate */ 498 PUC_PORT_2S, 0x18, 0, 8, 499 .config_function = puc_config_quatech 500 }, 501 502 { 0x135c, 0x01e0, 0xffff, 0, 503 "Quatech ESCLP-100", 504 -3, /* max 8x clock rate */ 505 PUC_PORT_8S, 0x10, 0, 8, 506 .config_function = puc_config_quatech 507 }, 508 509 { 0x1393, 0x1040, 0xffff, 0, 510 "Moxa Technologies, Smartio C104H/PCI", 511 DEFAULT_RCLK * 8, 512 PUC_PORT_4S, 0x18, 0, 8, 513 }, 514 515 { 0x1393, 0x1041, 0xffff, 0, 516 "Moxa Technologies, Smartio CP-104UL/PCI", 517 DEFAULT_RCLK * 8, 518 PUC_PORT_4S, 0x18, 0, 8, 519 }, 520 521 { 0x1393, 0x1043, 0xffff, 0, 522 "Moxa Technologies, Smartio CP-104EL/PCIe", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_4S, 0x18, 0, 8, 525 }, 526 527 { 0x1393, 0x1141, 0xffff, 0, 528 "Moxa Technologies, Industio CP-114", 529 DEFAULT_RCLK * 8, 530 PUC_PORT_4S, 0x18, 0, 8, 531 }, 532 533 { 0x1393, 0x1680, 0xffff, 0, 534 "Moxa Technologies, C168H/PCI", 535 DEFAULT_RCLK * 8, 536 PUC_PORT_8S, 0x18, 0, 8, 537 }, 538 539 { 0x1393, 0x1681, 0xffff, 0, 540 "Moxa Technologies, C168U/PCI", 541 DEFAULT_RCLK * 8, 542 PUC_PORT_8S, 0x18, 0, 8, 543 }, 544 545 { 0x1393, 0x1682, 0xffff, 0, 546 "Moxa Technologies, CP-168EL/PCIe", 547 DEFAULT_RCLK * 8, 548 PUC_PORT_8S, 0x18, 0, 8, 549 }, 550 551 { 0x13a8, 0x0158, 0xffff, 0, 552 "Cronyx Omega2-PCI", 553 DEFAULT_RCLK * 8, 554 PUC_PORT_8S, 0x10, 0, -1, 555 .config_function = puc_config_cronyx 556 }, 557 558 { 0x13a8, 0x0258, 0xffff, 0, 559 "Exar XR17V258IV", 560 DEFAULT_RCLK * 8, 561 PUC_PORT_8S, 0x10, 0, -1, 562 }, 563 564 { 0x1407, 0x0100, 0xffff, 0, 565 "Lava Computers Dual Serial", 566 DEFAULT_RCLK, 567 PUC_PORT_2S, 0x10, 4, 0, 568 }, 569 570 { 0x1407, 0x0101, 0xffff, 0, 571 "Lava Computers Quatro A", 572 DEFAULT_RCLK, 573 PUC_PORT_2S, 0x10, 4, 0, 574 }, 575 576 { 0x1407, 0x0102, 0xffff, 0, 577 "Lava Computers Quatro B", 578 DEFAULT_RCLK, 579 PUC_PORT_2S, 0x10, 4, 0, 580 }, 581 582 { 0x1407, 0x0120, 0xffff, 0, 583 "Lava Computers Quattro-PCI A", 584 DEFAULT_RCLK, 585 PUC_PORT_2S, 0x10, 4, 0, 586 }, 587 588 { 0x1407, 0x0121, 0xffff, 0, 589 "Lava Computers Quattro-PCI B", 590 DEFAULT_RCLK, 591 PUC_PORT_2S, 0x10, 4, 0, 592 }, 593 594 { 0x1407, 0x0180, 0xffff, 0, 595 "Lava Computers Octo A", 596 DEFAULT_RCLK, 597 PUC_PORT_4S, 0x10, 4, 0, 598 }, 599 600 { 0x1407, 0x0181, 0xffff, 0, 601 "Lava Computers Octo B", 602 DEFAULT_RCLK, 603 PUC_PORT_4S, 0x10, 4, 0, 604 }, 605 606 { 0x1409, 0x7268, 0xffff, 0, 607 "Sunix SUN1888", 608 0, 609 PUC_PORT_2P, 0x10, 0, 8, 610 }, 611 612 { 0x1409, 0x7168, 0xffff, 0, 613 NULL, 614 DEFAULT_RCLK * 8, 615 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 616 .config_function = puc_config_timedia 617 }, 618 619 /* 620 * Boards with an Oxford Semiconductor chip. 621 * 622 * Oxford Semiconductor provides documentation for their chip at: 623 * <URL:http://www.plxtech.com/products/uart/> 624 * 625 * As sold by Kouwell <URL:http://www.kouwell.com/>. 626 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 627 */ 628 629 { 0x1415, 0x9501, 0x131f, 0x2050, 630 "SIIG Cyber 4 PCI 16550", 631 DEFAULT_RCLK * 10, 632 PUC_PORT_4S, 0x10, 0, 8, 633 }, 634 635 { 0x1415, 0x9501, 0x131f, 0x2051, 636 "SIIG Cyber 4S PCI 16C650 (20x family)", 637 DEFAULT_RCLK * 10, 638 PUC_PORT_4S, 0x10, 0, 8, 639 }, 640 641 { 0x1415, 0x9501, 0x131f, 0x2052, 642 "SIIG Quartet Serial 850", 643 DEFAULT_RCLK * 10, 644 PUC_PORT_4S, 0x10, 0, 8, 645 }, 646 647 { 0x1415, 0x9501, 0x14db, 0x2150, 648 "Kuroutoshikou SERIAL4P-LPPCI2", 649 DEFAULT_RCLK * 10, 650 PUC_PORT_4S, 0x10, 0, 8, 651 }, 652 653 { 0x1415, 0x9501, 0xffff, 0, 654 "Oxford Semiconductor OX16PCI954 UARTs", 655 DEFAULT_RCLK, 656 PUC_PORT_4S, 0x10, 0, 8, 657 }, 658 659 { 0x1415, 0x950a, 0xffff, 0, 660 "Oxford Semiconductor OX16PCI954 UARTs", 661 DEFAULT_RCLK, 662 PUC_PORT_4S, 0x10, 0, 8, 663 }, 664 665 { 0x1415, 0x9511, 0xffff, 0, 666 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 667 DEFAULT_RCLK, 668 PUC_PORT_4S, 0x10, 0, 8, 669 }, 670 671 { 0x1415, 0x9521, 0xffff, 0, 672 "Oxford Semiconductor OX16PCI952 UARTs", 673 DEFAULT_RCLK, 674 PUC_PORT_2S, 0x10, 4, 0, 675 }, 676 677 { 0x1415, 0x9538, 0xffff, 0, 678 "Oxford Semiconductor OX16PCI958 UARTs", 679 DEFAULT_RCLK * 10, 680 PUC_PORT_8S, 0x18, 0, 8, 681 }, 682 683 /* 684 * Perle boards use Oxford Semiconductor chips, but they store the 685 * Oxford Semiconductor device ID as a subvendor device ID and use 686 * their own device IDs. 687 */ 688 689 { 0x155f, 0x0331, 0xffff, 0, 690 "Perle Speed4 LE", 691 DEFAULT_RCLK * 8, 692 PUC_PORT_4S, 0x10, 0, 8, 693 }, 694 695 /* 696 * Oxford Semiconductor PCI Express Expresso family 697 * 698 * Found in many 'native' PCI Express serial boards such as: 699 * 700 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 701 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 702 * 703 * Lindy 51189 (4 port) 704 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 705 * 706 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 707 * <URL:http://www.startech.com> 708 */ 709 710 { 0x1415, 0xc158, 0xffff, 0, 711 "Oxford Semiconductor OXPCIe952 UARTs", 712 DEFAULT_RCLK * 0x22, 713 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 714 .config_function = puc_config_oxford_pcie 715 }, 716 717 { 0x1415, 0xc15d, 0xffff, 0, 718 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 719 DEFAULT_RCLK * 0x22, 720 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 721 .config_function = puc_config_oxford_pcie 722 }, 723 724 { 0x1415, 0xc208, 0xffff, 0, 725 "Oxford Semiconductor OXPCIe954 UARTs", 726 DEFAULT_RCLK * 0x22, 727 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 728 .config_function = puc_config_oxford_pcie 729 }, 730 731 { 0x1415, 0xc20d, 0xffff, 0, 732 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 733 DEFAULT_RCLK * 0x22, 734 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 735 .config_function = puc_config_oxford_pcie 736 }, 737 738 { 0x1415, 0xc308, 0xffff, 0, 739 "Oxford Semiconductor OXPCIe958 UARTs", 740 DEFAULT_RCLK * 0x22, 741 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 742 .config_function = puc_config_oxford_pcie 743 }, 744 745 { 0x1415, 0xc30d, 0xffff, 0, 746 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 747 DEFAULT_RCLK * 0x22, 748 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 749 .config_function = puc_config_oxford_pcie 750 }, 751 752 { 0x14d2, 0x8010, 0xffff, 0, 753 "VScom PCI-100L", 754 DEFAULT_RCLK * 8, 755 PUC_PORT_1S, 0x14, 0, 0, 756 }, 757 758 { 0x14d2, 0x8020, 0xffff, 0, 759 "VScom PCI-200L", 760 DEFAULT_RCLK * 8, 761 PUC_PORT_2S, 0x14, 4, 0, 762 }, 763 764 { 0x14d2, 0x8028, 0xffff, 0, 765 "VScom 200Li", 766 DEFAULT_RCLK, 767 PUC_PORT_2S, 0x20, 0, 8, 768 }, 769 770 /* 771 * VScom (Titan?) PCI-800L. More modern variant of the 772 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 773 * two of them obviously implemented as macro cells in 774 * the ASIC. This causes the weird port access pattern 775 * below, where two of the IO port ranges each access 776 * one of the ASIC UARTs, and a block of IO addresses 777 * access the external UARTs. 778 */ 779 { 0x14d2, 0x8080, 0xffff, 0, 780 "Titan VScom PCI-800L", 781 DEFAULT_RCLK * 8, 782 PUC_PORT_8S, 0x14, -1, -1, 783 .config_function = puc_config_titan 784 }, 785 786 /* 787 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 788 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 789 * device ID 3 and PCI device 1 device ID 4. 790 */ 791 { 0x14d2, 0xa003, 0xffff, 0, 792 "Titan PCI-800H", 793 DEFAULT_RCLK * 8, 794 PUC_PORT_4S, 0x10, 0, 8, 795 }, 796 { 0x14d2, 0xa004, 0xffff, 0, 797 "Titan PCI-800H", 798 DEFAULT_RCLK * 8, 799 PUC_PORT_4S, 0x10, 0, 8, 800 }, 801 802 { 0x14d2, 0xa005, 0xffff, 0, 803 "Titan PCI-200H", 804 DEFAULT_RCLK * 8, 805 PUC_PORT_2S, 0x10, 0, 8, 806 }, 807 808 { 0x14d2, 0xe020, 0xffff, 0, 809 "Titan VScom PCI-200HV2", 810 DEFAULT_RCLK * 8, 811 PUC_PORT_2S, 0x10, 4, 0, 812 }, 813 814 { 0x14db, 0x2130, 0xffff, 0, 815 "Avlab Technology, PCI IO 2S", 816 DEFAULT_RCLK, 817 PUC_PORT_2S, 0x10, 4, 0, 818 }, 819 820 { 0x14db, 0x2150, 0xffff, 0, 821 "Avlab Low Profile PCI 4 Serial", 822 DEFAULT_RCLK, 823 PUC_PORT_4S, 0x10, 4, 0, 824 }, 825 826 { 0x14db, 0x2152, 0xffff, 0, 827 "Avlab Low Profile PCI 4 Serial", 828 DEFAULT_RCLK, 829 PUC_PORT_4S, 0x10, 4, 0, 830 }, 831 832 { 0x1592, 0x0781, 0xffff, 0, 833 "Syba Tech Ltd. PCI-4S2P-550-ECP", 834 DEFAULT_RCLK, 835 PUC_PORT_4S1P, 0x10, 0, -1, 836 .config_function = puc_config_syba 837 }, 838 839 { 0x6666, 0x0001, 0xffff, 0, 840 "Decision Computer Inc, PCCOM 4-port serial", 841 DEFAULT_RCLK, 842 PUC_PORT_4S, 0x1c, 0, 8, 843 }, 844 845 { 0x6666, 0x0002, 0xffff, 0, 846 "Decision Computer Inc, PCCOM 8-port serial", 847 DEFAULT_RCLK, 848 PUC_PORT_8S, 0x1c, 0, 8, 849 }, 850 851 { 0x6666, 0x0004, 0xffff, 0, 852 "PCCOM dual port RS232/422/485", 853 DEFAULT_RCLK, 854 PUC_PORT_2S, 0x1c, 0, 8, 855 }, 856 857 { 0x9710, 0x9815, 0xffff, 0, 858 "NetMos NM9815 Dual 1284 Printer port", 859 0, 860 PUC_PORT_2P, 0x10, 8, 0, 861 }, 862 863 /* 864 * This is more specific than the generic NM9835 entry that follows, and 865 * is placed here to _prevent_ puc from claiming this single port card. 866 * 867 * uart(4) will claim this device. 868 */ 869 { 0x9710, 0x9835, 0x1000, 1, 870 "NetMos NM9835 based 1-port serial", 871 DEFAULT_RCLK, 872 PUC_PORT_1S, 0x10, 4, 0, 873 }, 874 875 { 0x9710, 0x9835, 0x1000, 2, 876 "NetMos NM9835 based 2-port serial", 877 DEFAULT_RCLK, 878 PUC_PORT_2S, 0x10, 4, 0, 879 }, 880 881 { 0x9710, 0x9835, 0xffff, 0, 882 "NetMos NM9835 Dual UART and 1284 Printer port", 883 DEFAULT_RCLK, 884 PUC_PORT_2S1P, 0x10, 4, 0, 885 }, 886 887 { 0x9710, 0x9845, 0x1000, 0x0006, 888 "NetMos NM9845 6 Port UART", 889 DEFAULT_RCLK, 890 PUC_PORT_6S, 0x10, 4, 0, 891 }, 892 893 { 0x9710, 0x9845, 0xffff, 0, 894 "NetMos NM9845 Quad UART and 1284 Printer port", 895 DEFAULT_RCLK, 896 PUC_PORT_4S1P, 0x10, 4, 0, 897 }, 898 899 { 0x9710, 0x9865, 0xa000, 0x3002, 900 "NetMos NM9865 Dual UART", 901 DEFAULT_RCLK, 902 PUC_PORT_2S, 0x10, 4, 0, 903 }, 904 905 { 0x9710, 0x9865, 0xa000, 0x3003, 906 "NetMos NM9865 Triple UART", 907 DEFAULT_RCLK, 908 PUC_PORT_3S, 0x10, 4, 0, 909 }, 910 911 { 0x9710, 0x9865, 0xa000, 0x3004, 912 "NetMos NM9865 Quad UART", 913 DEFAULT_RCLK, 914 PUC_PORT_4S, 0x10, 4, 0,0 915 }, 916 917 { 0x9710, 0x9865, 0xa000, 0x3011, 918 "NetMos NM9865 Single UART and 1284 Printer port", 919 DEFAULT_RCLK, 920 PUC_PORT_1S1P, 0x10, 4, 0, 921 }, 922 923 { 0x9710, 0x9865, 0xa000, 0x3012, 924 "NetMos NM9865 Dual UART and 1284 Printer port", 925 DEFAULT_RCLK, 926 PUC_PORT_2S1P, 0x10, 4, 0, 927 }, 928 929 { 0x9710, 0x9865, 0xa000, 0x3020, 930 "NetMos NM9865 Dual 1284 Printer port", 931 DEFAULT_RCLK, 932 PUC_PORT_2P, 0x10, 4, 0, 933 }, 934 935 { 0xb00c, 0x021c, 0xffff, 0, 936 "IC Book Labs Gunboat x4 Lite", 937 DEFAULT_RCLK, 938 PUC_PORT_4S, 0x10, 0, 8, 939 .config_function = puc_config_icbook 940 }, 941 942 { 0xb00c, 0x031c, 0xffff, 0, 943 "IC Book Labs Gunboat x4 Pro", 944 DEFAULT_RCLK, 945 PUC_PORT_4S, 0x10, 0, 8, 946 .config_function = puc_config_icbook 947 }, 948 949 { 0xb00c, 0x041c, 0xffff, 0, 950 "IC Book Labs Ironclad x8 Lite", 951 DEFAULT_RCLK, 952 PUC_PORT_8S, 0x10, 0, 8, 953 .config_function = puc_config_icbook 954 }, 955 956 { 0xb00c, 0x051c, 0xffff, 0, 957 "IC Book Labs Ironclad x8 Pro", 958 DEFAULT_RCLK, 959 PUC_PORT_8S, 0x10, 0, 8, 960 .config_function = puc_config_icbook 961 }, 962 963 { 0xb00c, 0x081c, 0xffff, 0, 964 "IC Book Labs Dreadnought x16 Pro", 965 DEFAULT_RCLK * 8, 966 PUC_PORT_16S, 0x10, 0, 8, 967 .config_function = puc_config_icbook 968 }, 969 970 { 0xb00c, 0x091c, 0xffff, 0, 971 "IC Book Labs Dreadnought x16 Lite", 972 DEFAULT_RCLK, 973 PUC_PORT_16S, 0x10, 0, 8, 974 .config_function = puc_config_icbook 975 }, 976 977 { 0xb00c, 0x0a1c, 0xffff, 0, 978 "IC Book Labs Gunboat x2 Low Profile", 979 DEFAULT_RCLK, 980 PUC_PORT_2S, 0x10, 0, 8, 981 }, 982 983 { 0xb00c, 0x0b1c, 0xffff, 0, 984 "IC Book Labs Gunboat x4 Low Profile", 985 DEFAULT_RCLK, 986 PUC_PORT_4S, 0x10, 0, 8, 987 .config_function = puc_config_icbook 988 }, 989 990 { 0xffff, 0, 0xffff, 0, NULL, 0 } 991 }; 992 993 static int 994 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 995 intptr_t *res) 996 { 997 switch (cmd) { 998 case PUC_CFG_GET_OFS: 999 *res = 8 * (port & 1); 1000 return (0); 1001 case PUC_CFG_GET_RID: 1002 *res = 0x14 + (port >> 1) * 4; 1003 return (0); 1004 default: 1005 break; 1006 } 1007 return (ENXIO); 1008 } 1009 1010 static int 1011 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1012 intptr_t *res) 1013 { 1014 if (cmd == PUC_CFG_GET_OFS) { 1015 *res = port * 0x200; 1016 return (0); 1017 } 1018 return (ENXIO); 1019 } 1020 1021 static int 1022 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1023 intptr_t *res) 1024 { 1025 const struct puc_cfg *cfg = sc->sc_cfg; 1026 1027 if (cmd == PUC_CFG_GET_OFS) { 1028 if (cfg->subdevice == 0x1282) /* Everest SP */ 1029 port <<= 1; 1030 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1031 port = (port == 3) ? 4 : port; 1032 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1033 return (0); 1034 } 1035 return (ENXIO); 1036 } 1037 1038 static int 1039 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1040 intptr_t *res) 1041 { 1042 if (cmd == PUC_CFG_GET_ILR) { 1043 *res = PUC_ILR_DIGI; 1044 return (0); 1045 } 1046 return (ENXIO); 1047 } 1048 1049 static int 1050 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1051 intptr_t *res) 1052 { 1053 const struct puc_cfg *cfg = sc->sc_cfg; 1054 struct puc_bar *bar; 1055 uint8_t v0, v1; 1056 1057 switch (cmd) { 1058 case PUC_CFG_SETUP: 1059 /* 1060 * Check if the scratchpad register is enabled or if the 1061 * interrupt status and options registers are active. 1062 */ 1063 bar = puc_get_bar(sc, cfg->rid); 1064 if (bar == NULL) 1065 return (ENXIO); 1066 /* Set DLAB in the LCR register of UART 0. */ 1067 bus_write_1(bar->b_res, 3, 0x80); 1068 /* Write 0 to the SPR register of UART 0. */ 1069 bus_write_1(bar->b_res, 7, 0); 1070 /* Read back the contents of the SPR register of UART 0. */ 1071 v0 = bus_read_1(bar->b_res, 7); 1072 /* Write a specific value to the SPR register of UART 0. */ 1073 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 1074 /* Read back the contents of the SPR register of UART 0. */ 1075 v1 = bus_read_1(bar->b_res, 7); 1076 /* Clear DLAB in the LCR register of UART 0. */ 1077 bus_write_1(bar->b_res, 3, 0); 1078 /* Save the two values read-back from the SPR register. */ 1079 sc->sc_cfg_data = (v0 << 8) | v1; 1080 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1081 /* 1082 * The SPR register echoed the two values written 1083 * by us. This means that the SPAD jumper is set. 1084 */ 1085 device_printf(sc->sc_dev, "warning: extra features " 1086 "not usable -- SPAD compatibility enabled\n"); 1087 return (0); 1088 } 1089 if (v0 != 0) { 1090 /* 1091 * The first value doesn't match. This can only mean 1092 * that the SPAD jumper is not set and that a non- 1093 * standard fixed clock multiplier jumper is set. 1094 */ 1095 if (bootverbose) 1096 device_printf(sc->sc_dev, "fixed clock rate " 1097 "multiplier of %d\n", 1 << v0); 1098 if (v0 < -cfg->clock) 1099 device_printf(sc->sc_dev, "warning: " 1100 "suboptimal fixed clock rate multiplier " 1101 "setting\n"); 1102 return (0); 1103 } 1104 /* 1105 * The first value matched, but the second didn't. We know 1106 * that the SPAD jumper is not set. We also know that the 1107 * clock rate multiplier is software controlled *and* that 1108 * we just programmed it to the maximum allowed. 1109 */ 1110 if (bootverbose) 1111 device_printf(sc->sc_dev, "clock rate multiplier of " 1112 "%d selected\n", 1 << -cfg->clock); 1113 return (0); 1114 case PUC_CFG_GET_CLOCK: 1115 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1116 v1 = sc->sc_cfg_data & 0xff; 1117 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1118 /* 1119 * XXX With the SPAD jumper applied, there's no 1120 * easy way of knowing if there's also a clock 1121 * rate multiplier jumper installed. Let's hope 1122 * not... 1123 */ 1124 *res = DEFAULT_RCLK; 1125 } else if (v0 == 0) { 1126 /* 1127 * No clock rate multiplier jumper installed, 1128 * so we programmed the board with the maximum 1129 * multiplier allowed as given to us in the 1130 * clock field of the config record (negated). 1131 */ 1132 *res = DEFAULT_RCLK << -cfg->clock; 1133 } else 1134 *res = DEFAULT_RCLK << v0; 1135 return (0); 1136 case PUC_CFG_GET_ILR: 1137 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1138 v1 = sc->sc_cfg_data & 0xff; 1139 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 1140 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 1141 return (0); 1142 default: 1143 break; 1144 } 1145 return (ENXIO); 1146 } 1147 1148 static int 1149 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1150 intptr_t *res) 1151 { 1152 static int base[] = { 0x251, 0x3f0, 0 }; 1153 const struct puc_cfg *cfg = sc->sc_cfg; 1154 struct puc_bar *bar; 1155 int efir, idx, ofs; 1156 uint8_t v; 1157 1158 switch (cmd) { 1159 case PUC_CFG_SETUP: 1160 bar = puc_get_bar(sc, cfg->rid); 1161 if (bar == NULL) 1162 return (ENXIO); 1163 1164 /* configure both W83877TFs */ 1165 bus_write_1(bar->b_res, 0x250, 0x89); 1166 bus_write_1(bar->b_res, 0x3f0, 0x87); 1167 bus_write_1(bar->b_res, 0x3f0, 0x87); 1168 idx = 0; 1169 while (base[idx] != 0) { 1170 efir = base[idx]; 1171 bus_write_1(bar->b_res, efir, 0x09); 1172 v = bus_read_1(bar->b_res, efir + 1); 1173 if ((v & 0x0f) != 0x0c) 1174 return (ENXIO); 1175 bus_write_1(bar->b_res, efir, 0x16); 1176 v = bus_read_1(bar->b_res, efir + 1); 1177 bus_write_1(bar->b_res, efir, 0x16); 1178 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1179 bus_write_1(bar->b_res, efir, 0x16); 1180 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1181 ofs = base[idx] & 0x300; 1182 bus_write_1(bar->b_res, efir, 0x23); 1183 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1184 bus_write_1(bar->b_res, efir, 0x24); 1185 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1186 bus_write_1(bar->b_res, efir, 0x25); 1187 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1188 bus_write_1(bar->b_res, efir, 0x17); 1189 bus_write_1(bar->b_res, efir + 1, 0x03); 1190 bus_write_1(bar->b_res, efir, 0x28); 1191 bus_write_1(bar->b_res, efir + 1, 0x43); 1192 idx++; 1193 } 1194 bus_write_1(bar->b_res, 0x250, 0xaa); 1195 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1196 return (0); 1197 case PUC_CFG_GET_OFS: 1198 switch (port) { 1199 case 0: 1200 *res = 0x2f8; 1201 return (0); 1202 case 1: 1203 *res = 0x2e8; 1204 return (0); 1205 case 2: 1206 *res = 0x3f8; 1207 return (0); 1208 case 3: 1209 *res = 0x3e8; 1210 return (0); 1211 case 4: 1212 *res = 0x278; 1213 return (0); 1214 } 1215 break; 1216 default: 1217 break; 1218 } 1219 return (ENXIO); 1220 } 1221 1222 static int 1223 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1224 intptr_t *res) 1225 { 1226 const struct puc_cfg *cfg = sc->sc_cfg; 1227 1228 switch (cmd) { 1229 case PUC_CFG_GET_OFS: 1230 if (cfg->ports == PUC_PORT_8S) { 1231 *res = (port > 4) ? 8 * (port - 4) : 0; 1232 return (0); 1233 } 1234 break; 1235 case PUC_CFG_GET_RID: 1236 if (cfg->ports == PUC_PORT_8S) { 1237 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1238 return (0); 1239 } 1240 if (cfg->ports == PUC_PORT_2S1P) { 1241 switch (port) { 1242 case 0: *res = 0x10; return (0); 1243 case 1: *res = 0x14; return (0); 1244 case 2: *res = 0x1c; return (0); 1245 } 1246 } 1247 break; 1248 default: 1249 break; 1250 } 1251 return (ENXIO); 1252 } 1253 1254 static int 1255 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1256 intptr_t *res) 1257 { 1258 static uint16_t dual[] = { 1259 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1260 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1261 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1262 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1263 0xD079, 0 1264 }; 1265 static uint16_t quad[] = { 1266 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1267 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1268 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1269 0xB157, 0 1270 }; 1271 static uint16_t octa[] = { 1272 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1273 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1274 }; 1275 static struct { 1276 int ports; 1277 uint16_t *ids; 1278 } subdevs[] = { 1279 { 2, dual }, 1280 { 4, quad }, 1281 { 8, octa }, 1282 { 0, NULL } 1283 }; 1284 static char desc[64]; 1285 int dev, id; 1286 uint16_t subdev; 1287 1288 switch (cmd) { 1289 case PUC_CFG_GET_DESC: 1290 snprintf(desc, sizeof(desc), 1291 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1292 *res = (intptr_t)desc; 1293 return (0); 1294 case PUC_CFG_GET_NPORTS: 1295 subdev = pci_get_subdevice(sc->sc_dev); 1296 dev = 0; 1297 while (subdevs[dev].ports != 0) { 1298 id = 0; 1299 while (subdevs[dev].ids[id] != 0) { 1300 if (subdev == subdevs[dev].ids[id]) { 1301 sc->sc_cfg_data = subdevs[dev].ports; 1302 *res = sc->sc_cfg_data; 1303 return (0); 1304 } 1305 id++; 1306 } 1307 dev++; 1308 } 1309 return (ENXIO); 1310 case PUC_CFG_GET_OFS: 1311 *res = (port == 1 || port == 3) ? 8 : 0; 1312 return (0); 1313 case PUC_CFG_GET_RID: 1314 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1315 return (0); 1316 case PUC_CFG_GET_TYPE: 1317 *res = PUC_TYPE_SERIAL; 1318 return (0); 1319 default: 1320 break; 1321 } 1322 return (ENXIO); 1323 } 1324 1325 static int 1326 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1327 intptr_t *res) 1328 { 1329 const struct puc_cfg *cfg = sc->sc_cfg; 1330 int idx; 1331 struct puc_bar *bar; 1332 uint8_t value; 1333 1334 switch (cmd) { 1335 case PUC_CFG_SETUP: 1336 device_printf(sc->sc_dev, "%d UARTs detected\n", 1337 sc->sc_nports); 1338 1339 /* Set UARTs to enhanced mode */ 1340 bar = puc_get_bar(sc, cfg->rid); 1341 if (bar == NULL) 1342 return (ENXIO); 1343 1344 for (idx = 0; idx < sc->sc_nports; idx++) { 1345 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) 1346 + 0x92); 1347 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1348 value | 0x10); 1349 } 1350 1351 return (0); 1352 case PUC_CFG_GET_LEN: 1353 *res = 0x200; 1354 return (0); 1355 case PUC_CFG_GET_NPORTS: 1356 /* 1357 * Check if we are being called from puc_bfe_attach() 1358 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1359 * puc_get_bar(), so we return a value of 16. This has cosmetic 1360 * side-effects at worst; in PUC_CFG_GET_DESC, 1361 * (int)sc->sc_cfg_data will not contain the true number of 1362 * ports in PUC_CFG_GET_DESC, but we are not implementing that 1363 * call for this device family anyway. 1364 * 1365 * The check is for initialisation of sc->sc_bar[idx], which is 1366 * only done in puc_bfe_attach(). 1367 */ 1368 idx = 0; 1369 do { 1370 if (sc->sc_bar[idx++].b_rid != -1) { 1371 sc->sc_cfg_data = 16; 1372 *res = sc->sc_cfg_data; 1373 return (0); 1374 } 1375 } while (idx < PUC_PCI_BARS); 1376 1377 bar = puc_get_bar(sc, cfg->rid); 1378 if (bar == NULL) 1379 return (ENXIO); 1380 1381 value = bus_read_1(bar->b_res, 0x04); 1382 if (value == 0) 1383 return (ENXIO); 1384 1385 sc->sc_cfg_data = value; 1386 *res = sc->sc_cfg_data; 1387 return (0); 1388 case PUC_CFG_GET_OFS: 1389 *res = 0x1000 + (port << 9); 1390 return (0); 1391 case PUC_CFG_GET_TYPE: 1392 *res = PUC_TYPE_SERIAL; 1393 return (0); 1394 default: 1395 break; 1396 } 1397 return (ENXIO); 1398 } 1399 1400 static int 1401 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1402 intptr_t *res) 1403 { 1404 switch (cmd) { 1405 case PUC_CFG_GET_OFS: 1406 *res = (port < 3) ? 0 : (port - 2) << 3; 1407 return (0); 1408 case PUC_CFG_GET_RID: 1409 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1410 return (0); 1411 default: 1412 break; 1413 } 1414 return (ENXIO); 1415 } 1416