1 /*- 2 * Copyright (c) 2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/puc/puc_bus.h> 47 #include <dev/puc/puc_cfg.h> 48 #include <dev/puc/puc_bfe.h> 49 50 static puc_config_f puc_config_amc; 51 static puc_config_f puc_config_cronyx; 52 static puc_config_f puc_config_diva; 53 static puc_config_f puc_config_icbook; 54 static puc_config_f puc_config_quatech; 55 static puc_config_f puc_config_syba; 56 static puc_config_f puc_config_siig; 57 static puc_config_f puc_config_timedia; 58 static puc_config_f puc_config_titan; 59 60 const struct puc_cfg puc_pci_devices[] = { 61 62 { 0x0009, 0x7168, 0xffff, 0, 63 "Sunix SUN1889", 64 DEFAULT_RCLK * 8, 65 PUC_PORT_2S, 0x10, 0, 8, 66 }, 67 68 { 0x103c, 0x1048, 0x103c, 0x1049, 69 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 70 DEFAULT_RCLK, 71 PUC_PORT_3S, 0x10, 0, -1, 72 .config_function = puc_config_diva 73 }, 74 75 { 0x103c, 0x1048, 0x103c, 0x104a, 76 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 77 DEFAULT_RCLK, 78 PUC_PORT_2S, 0x10, 0, -1, 79 .config_function = puc_config_diva 80 }, 81 82 { 0x103c, 0x1048, 0x103c, 0x104b, 83 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 84 DEFAULT_RCLK, 85 PUC_PORT_4S, 0x10, 0, -1, 86 .config_function = puc_config_diva 87 }, 88 89 { 0x103c, 0x1048, 0x103c, 0x1223, 90 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 91 DEFAULT_RCLK, 92 PUC_PORT_3S, 0x10, 0, -1, 93 .config_function = puc_config_diva 94 }, 95 96 { 0x103c, 0x1048, 0x103c, 0x1226, 97 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 98 DEFAULT_RCLK, 99 PUC_PORT_3S, 0x10, 0, -1, 100 .config_function = puc_config_diva 101 }, 102 103 { 0x103c, 0x1048, 0x103c, 0x1282, 104 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 105 DEFAULT_RCLK, 106 PUC_PORT_3S, 0x10, 0, -1, 107 .config_function = puc_config_diva 108 }, 109 110 { 0x10b5, 0x1076, 0x10b5, 0x1076, 111 "VScom PCI-800", 112 DEFAULT_RCLK * 8, 113 PUC_PORT_8S, 0x18, 0, 8, 114 }, 115 116 { 0x10b5, 0x1077, 0x10b5, 0x1077, 117 "VScom PCI-400", 118 DEFAULT_RCLK * 8, 119 PUC_PORT_4S, 0x18, 0, 8, 120 }, 121 122 { 0x10b5, 0x1103, 0x10b5, 0x1103, 123 "VScom PCI-200", 124 DEFAULT_RCLK * 8, 125 PUC_PORT_2S, 0x18, 4, 0, 126 }, 127 128 /* 129 * Boca Research Turbo Serial 658 (8 serial port) card. 130 * Appears to be the same as Chase Research PLC PCI-FAST8 131 * and Perle PCI-FAST8 Multi-Port serial cards. 132 */ 133 { 0x10b5, 0x9050, 0x12e0, 0x0021, 134 "Boca Research Turbo Serial 658", 135 DEFAULT_RCLK * 4, 136 PUC_PORT_8S, 0x18, 0, 8, 137 }, 138 139 { 0x10b5, 0x9050, 0x12e0, 0x0031, 140 "Boca Research Turbo Serial 654", 141 DEFAULT_RCLK * 4, 142 PUC_PORT_4S, 0x18, 0, 8, 143 }, 144 145 /* 146 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 147 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 148 * into the subsystem fields, and claims that it's a 149 * network/misc (0x02/0x80) device. 150 */ 151 { 0x10b5, 0x9050, 0xd84d, 0x6808, 152 "Dolphin Peripherals 4035", 153 DEFAULT_RCLK, 154 PUC_PORT_2S, 0x18, 4, 0, 155 }, 156 157 /* 158 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 159 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 160 * into the subsystem fields, and claims that it's a 161 * network/misc (0x02/0x80) device. 162 */ 163 { 0x10b5, 0x9050, 0xd84d, 0x6810, 164 "Dolphin Peripherals 4014", 165 0, 166 PUC_PORT_2P, 0x20, 4, 0, 167 }, 168 169 { 0x10e8, 0x818e, 0xffff, 0, 170 "Applied Micro Circuits 8 Port UART", 171 DEFAULT_RCLK, 172 PUC_PORT_8S, 0x14, -1, -1, 173 .config_function = puc_config_amc 174 }, 175 176 { 0x11fe, 0x8010, 0xffff, 0, 177 "Comtrol RocketPort 550/8 RJ11 part A", 178 DEFAULT_RCLK * 4, 179 PUC_PORT_4S, 0x10, 0, 8, 180 }, 181 182 { 0x11fe, 0x8011, 0xffff, 0, 183 "Comtrol RocketPort 550/8 RJ11 part B", 184 DEFAULT_RCLK * 4, 185 PUC_PORT_4S, 0x10, 0, 8, 186 }, 187 188 { 0x11fe, 0x8012, 0xffff, 0, 189 "Comtrol RocketPort 550/8 Octa part A", 190 DEFAULT_RCLK * 4, 191 PUC_PORT_4S, 0x10, 0, 8, 192 }, 193 194 { 0x11fe, 0x8013, 0xffff, 0, 195 "Comtrol RocketPort 550/8 Octa part B", 196 DEFAULT_RCLK * 4, 197 PUC_PORT_4S, 0x10, 0, 8, 198 }, 199 200 { 0x11fe, 0x8014, 0xffff, 0, 201 "Comtrol RocketPort 550/4 RJ45", 202 DEFAULT_RCLK * 4, 203 PUC_PORT_4S, 0x10, 0, 8, 204 }, 205 206 { 0x11fe, 0x8015, 0xffff, 0, 207 "Comtrol RocketPort 550/Quad", 208 DEFAULT_RCLK * 4, 209 PUC_PORT_4S, 0x10, 0, 8, 210 }, 211 212 { 0x11fe, 0x8016, 0xffff, 0, 213 "Comtrol RocketPort 550/16 part A", 214 DEFAULT_RCLK * 4, 215 PUC_PORT_4S, 0x10, 0, 8, 216 }, 217 218 { 0x11fe, 0x8017, 0xffff, 0, 219 "Comtrol RocketPort 550/16 part B", 220 DEFAULT_RCLK * 4, 221 PUC_PORT_12S, 0x10, 0, 8, 222 }, 223 224 { 0x11fe, 0x8018, 0xffff, 0, 225 "Comtrol RocketPort 550/8 part A", 226 DEFAULT_RCLK * 4, 227 PUC_PORT_4S, 0x10, 0, 8, 228 }, 229 230 { 0x11fe, 0x8019, 0xffff, 0, 231 "Comtrol RocketPort 550/8 part B", 232 DEFAULT_RCLK * 4, 233 PUC_PORT_4S, 0x10, 0, 8, 234 }, 235 236 /* 237 * SIIG Boards. 238 * 239 * SIIG provides documentation for their boards at: 240 * <URL:http://www.siig.com/downloads.asp> 241 */ 242 243 { 0x131f, 0x1010, 0xffff, 0, 244 "SIIG Cyber I/O PCI 16C550 (10x family)", 245 DEFAULT_RCLK, 246 PUC_PORT_1S1P, 0x18, 4, 0, 247 }, 248 249 { 0x131f, 0x1011, 0xffff, 0, 250 "SIIG Cyber I/O PCI 16C650 (10x family)", 251 DEFAULT_RCLK, 252 PUC_PORT_1S1P, 0x18, 4, 0, 253 }, 254 255 { 0x131f, 0x1012, 0xffff, 0, 256 "SIIG Cyber I/O PCI 16C850 (10x family)", 257 DEFAULT_RCLK, 258 PUC_PORT_1S1P, 0x18, 4, 0, 259 }, 260 261 { 0x131f, 0x1021, 0xffff, 0, 262 "SIIG Cyber Parallel Dual PCI (10x family)", 263 0, 264 PUC_PORT_2P, 0x18, 8, 0, 265 }, 266 267 { 0x131f, 0x1030, 0xffff, 0, 268 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 269 DEFAULT_RCLK, 270 PUC_PORT_2S, 0x18, 4, 0, 271 }, 272 273 { 0x131f, 0x1031, 0xffff, 0, 274 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 275 DEFAULT_RCLK, 276 PUC_PORT_2S, 0x18, 4, 0, 277 }, 278 279 { 0x131f, 0x1032, 0xffff, 0, 280 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 281 DEFAULT_RCLK, 282 PUC_PORT_2S, 0x18, 4, 0, 283 }, 284 285 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 286 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 287 DEFAULT_RCLK, 288 PUC_PORT_2S1P, 0x18, 4, 0, 289 }, 290 291 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 292 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 293 DEFAULT_RCLK, 294 PUC_PORT_2S1P, 0x18, 4, 0, 295 }, 296 297 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 298 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 299 DEFAULT_RCLK, 300 PUC_PORT_2S1P, 0x18, 4, 0, 301 }, 302 303 { 0x131f, 0x1050, 0xffff, 0, 304 "SIIG Cyber 4S PCI 16C550 (10x family)", 305 DEFAULT_RCLK, 306 PUC_PORT_4S, 0x18, 4, 0, 307 }, 308 309 { 0x131f, 0x1051, 0xffff, 0, 310 "SIIG Cyber 4S PCI 16C650 (10x family)", 311 DEFAULT_RCLK, 312 PUC_PORT_4S, 0x18, 4, 0, 313 }, 314 315 { 0x131f, 0x1052, 0xffff, 0, 316 "SIIG Cyber 4S PCI 16C850 (10x family)", 317 DEFAULT_RCLK, 318 PUC_PORT_4S, 0x18, 4, 0, 319 }, 320 321 { 0x131f, 0x2010, 0xffff, 0, 322 "SIIG Cyber I/O PCI 16C550 (20x family)", 323 DEFAULT_RCLK, 324 PUC_PORT_1S1P, 0x10, 4, 0, 325 }, 326 327 { 0x131f, 0x2011, 0xffff, 0, 328 "SIIG Cyber I/O PCI 16C650 (20x family)", 329 DEFAULT_RCLK, 330 PUC_PORT_1S1P, 0x10, 4, 0, 331 }, 332 333 { 0x131f, 0x2012, 0xffff, 0, 334 "SIIG Cyber I/O PCI 16C850 (20x family)", 335 DEFAULT_RCLK, 336 PUC_PORT_1S1P, 0x10, 4, 0, 337 }, 338 339 { 0x131f, 0x2021, 0xffff, 0, 340 "SIIG Cyber Parallel Dual PCI (20x family)", 341 0, 342 PUC_PORT_2P, 0x10, 8, 0, 343 }, 344 345 { 0x131f, 0x2030, 0xffff, 0, 346 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 347 DEFAULT_RCLK, 348 PUC_PORT_2S, 0x10, 4, 0, 349 }, 350 351 { 0x131f, 0x2031, 0xffff, 0, 352 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 353 DEFAULT_RCLK, 354 PUC_PORT_2S, 0x10, 4, 0, 355 }, 356 357 { 0x131f, 0x2032, 0xffff, 0, 358 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 359 DEFAULT_RCLK, 360 PUC_PORT_2S, 0x10, 4, 0, 361 }, 362 363 { 0x131f, 0x2040, 0xffff, 0, 364 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 365 DEFAULT_RCLK, 366 PUC_PORT_1S2P, 0x10, -1, 0, 367 .config_function = puc_config_siig 368 }, 369 370 { 0x131f, 0x2041, 0xffff, 0, 371 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 372 DEFAULT_RCLK, 373 PUC_PORT_1S2P, 0x10, -1, 0, 374 .config_function = puc_config_siig 375 }, 376 377 { 0x131f, 0x2042, 0xffff, 0, 378 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 379 DEFAULT_RCLK, 380 PUC_PORT_1S2P, 0x10, -1, 0, 381 .config_function = puc_config_siig 382 }, 383 384 { 0x131f, 0x2050, 0xffff, 0, 385 "SIIG Cyber 4S PCI 16C550 (20x family)", 386 DEFAULT_RCLK, 387 PUC_PORT_4S, 0x10, 4, 0, 388 }, 389 390 { 0x131f, 0x2051, 0xffff, 0, 391 "SIIG Cyber 4S PCI 16C650 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_4S, 0x10, 4, 0, 394 }, 395 396 { 0x131f, 0x2052, 0xffff, 0, 397 "SIIG Cyber 4S PCI 16C850 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_4S, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2060, 0xffff, 0, 403 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_2S1P, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2061, 0xffff, 0, 409 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 410 DEFAULT_RCLK, 411 PUC_PORT_2S1P, 0x10, 4, 0, 412 }, 413 414 { 0x131f, 0x2062, 0xffff, 0, 415 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S1P, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2081, 0xffff, 0, 421 "SIIG PS8000 8S PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_8S, 0x10, -1, -1, 424 .config_function = puc_config_siig 425 }, 426 427 { 0x135c, 0x0010, 0xffff, 0, 428 "Quatech QSC-100", 429 -3, /* max 8x clock rate */ 430 PUC_PORT_4S, 0x14, 0, 8, 431 .config_function = puc_config_quatech 432 }, 433 434 { 0x135c, 0x0020, 0xffff, 0, 435 "Quatech DSC-100", 436 -1, /* max 2x clock rate */ 437 PUC_PORT_2S, 0x14, 0, 8, 438 .config_function = puc_config_quatech 439 }, 440 441 { 0x135c, 0x0030, 0xffff, 0, 442 "Quatech DSC-200/300", 443 -1, /* max 2x clock rate */ 444 PUC_PORT_2S, 0x14, 0, 8, 445 .config_function = puc_config_quatech 446 }, 447 448 { 0x135c, 0x0040, 0xffff, 0, 449 "Quatech QSC-200/300", 450 -3, /* max 8x clock rate */ 451 PUC_PORT_4S, 0x14, 0, 8, 452 .config_function = puc_config_quatech 453 }, 454 455 { 0x135c, 0x0050, 0xffff, 0, 456 "Quatech ESC-100D", 457 -3, /* max 8x clock rate */ 458 PUC_PORT_8S, 0x14, 0, 8, 459 .config_function = puc_config_quatech 460 }, 461 462 { 0x135c, 0x0060, 0xffff, 0, 463 "Quatech ESC-100M", 464 -3, /* max 8x clock rate */ 465 PUC_PORT_8S, 0x14, 0, 8, 466 .config_function = puc_config_quatech 467 }, 468 469 { 0x135c, 0x0170, 0xffff, 0, 470 "Quatech QSCLP-100", 471 -1, /* max 2x clock rate */ 472 PUC_PORT_4S, 0x18, 0, 8, 473 .config_function = puc_config_quatech 474 }, 475 476 { 0x135c, 0x0180, 0xffff, 0, 477 "Quatech DSCLP-100", 478 -1, /* max 3x clock rate */ 479 PUC_PORT_2S, 0x18, 0, 8, 480 .config_function = puc_config_quatech 481 }, 482 483 { 0x135c, 0x01b0, 0xffff, 0, 484 "Quatech DSCLP-200/300", 485 -1, /* max 2x clock rate */ 486 PUC_PORT_2S, 0x18, 0, 8, 487 .config_function = puc_config_quatech 488 }, 489 490 { 0x135c, 0x01e0, 0xffff, 0, 491 "Quatech ESCLP-100", 492 -3, /* max 8x clock rate */ 493 PUC_PORT_8S, 0x10, 0, 8, 494 .config_function = puc_config_quatech 495 }, 496 497 { 0x1393, 0x1040, 0xffff, 0, 498 "Moxa Technologies, Smartio C104H/PCI", 499 DEFAULT_RCLK * 8, 500 PUC_PORT_4S, 0x18, 0, 8, 501 }, 502 503 { 0x1393, 0x1041, 0xffff, 0, 504 "Moxa Technologies, Smartio CP-104UL/PCI", 505 DEFAULT_RCLK * 8, 506 PUC_PORT_4S, 0x18, 0, 8, 507 }, 508 509 { 0x1393, 0x1043, 0xffff, 0, 510 "Moxa Technologies, Smartio CP-104EL/PCIe", 511 DEFAULT_RCLK * 8, 512 PUC_PORT_4S, 0x18, 0, 8, 513 }, 514 515 { 0x1393, 0x1141, 0xffff, 0, 516 "Moxa Technologies, Industio CP-114", 517 DEFAULT_RCLK * 8, 518 PUC_PORT_4S, 0x18, 0, 8, 519 }, 520 521 { 0x1393, 0x1680, 0xffff, 0, 522 "Moxa Technologies, C168H/PCI", 523 DEFAULT_RCLK * 8, 524 PUC_PORT_8S, 0x18, 0, 8, 525 }, 526 527 { 0x1393, 0x1681, 0xffff, 0, 528 "Moxa Technologies, C168U/PCI", 529 DEFAULT_RCLK * 8, 530 PUC_PORT_8S, 0x18, 0, 8, 531 }, 532 533 { 0x13a8, 0x0158, 0xffff, 0, 534 "Cronyx Omega2-PCI", 535 DEFAULT_RCLK * 8, 536 PUC_PORT_8S, 0x10, 0, -1, 537 .config_function = puc_config_cronyx 538 }, 539 540 { 0x1407, 0x0100, 0xffff, 0, 541 "Lava Computers Dual Serial", 542 DEFAULT_RCLK, 543 PUC_PORT_2S, 0x10, 4, 0, 544 }, 545 546 { 0x1407, 0x0101, 0xffff, 0, 547 "Lava Computers Quatro A", 548 DEFAULT_RCLK, 549 PUC_PORT_2S, 0x10, 4, 0, 550 }, 551 552 { 0x1407, 0x0102, 0xffff, 0, 553 "Lava Computers Quatro B", 554 DEFAULT_RCLK, 555 PUC_PORT_2S, 0x10, 4, 0, 556 }, 557 558 { 0x1407, 0x0120, 0xffff, 0, 559 "Lava Computers Quattro-PCI A", 560 DEFAULT_RCLK, 561 PUC_PORT_2S, 0x10, 4, 0, 562 }, 563 564 { 0x1407, 0x0121, 0xffff, 0, 565 "Lava Computers Quattro-PCI B", 566 DEFAULT_RCLK, 567 PUC_PORT_2S, 0x10, 4, 0, 568 }, 569 570 { 0x1407, 0x0180, 0xffff, 0, 571 "Lava Computers Octo A", 572 DEFAULT_RCLK, 573 PUC_PORT_4S, 0x10, 4, 0, 574 }, 575 576 { 0x1407, 0x0181, 0xffff, 0, 577 "Lava Computers Octo B", 578 DEFAULT_RCLK, 579 PUC_PORT_4S, 0x10, 4, 0, 580 }, 581 582 { 0x1409, 0x7168, 0xffff, 0, 583 NULL, 584 DEFAULT_RCLK * 8, 585 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 586 .config_function = puc_config_timedia 587 }, 588 589 /* 590 * Boards with an Oxford Semiconductor chip. 591 * 592 * Oxford Semiconductor provides documentation for their chip at: 593 * <URL:http://www.oxsemi.com/products/uarts/index.html> 594 * 595 * As sold by Kouwell <URL:http://www.kouwell.com/>. 596 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 597 */ 598 599 { 0x1415, 0x9501, 0x131f, 0x2051, 600 "SIIG Cyber 4S PCI 16C650 (20x family)", 601 DEFAULT_RCLK * 10, 602 PUC_PORT_4S, 0x10, 0, 8, 603 }, 604 605 { 0x1415, 0x9501, 0xffff, 0, 606 "Oxford Semiconductor OX16PCI954 UARTs", 607 DEFAULT_RCLK, 608 PUC_PORT_4S, 0x10, 0, 8, 609 }, 610 611 { 0x1415, 0x950a, 0xffff, 0, 612 "Oxford Semiconductor OX16PCI954 UARTs", 613 DEFAULT_RCLK, 614 PUC_PORT_4S, 0x10, 0, 8, 615 }, 616 617 { 0x1415, 0x9511, 0xffff, 0, 618 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 619 DEFAULT_RCLK, 620 PUC_PORT_4S, 0x10, 0, 8, 621 }, 622 623 { 0x1415, 0x9521, 0xffff, 0, 624 "Oxford Semiconductor OX16PCI952 UARTs", 625 DEFAULT_RCLK, 626 PUC_PORT_2S, 0x10, 4, 0, 627 }, 628 629 { 0x14d2, 0x8010, 0xffff, 0, 630 "VScom PCI-100L", 631 DEFAULT_RCLK * 8, 632 PUC_PORT_1S, 0x14, 0, 0, 633 }, 634 635 { 0x14d2, 0x8020, 0xffff, 0, 636 "VScom PCI-200L", 637 DEFAULT_RCLK * 8, 638 PUC_PORT_2S, 0x14, 4, 0, 639 }, 640 641 { 0x14d2, 0x8028, 0xffff, 0, 642 "VScom 200Li", 643 DEFAULT_RCLK, 644 PUC_PORT_2S, 0x20, 0, 8, 645 }, 646 647 /* 648 * VScom (Titan?) PCI-800L. More modern variant of the 649 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 650 * two of them obviously implemented as macro cells in 651 * the ASIC. This causes the weird port access pattern 652 * below, where two of the IO port ranges each access 653 * one of the ASIC UARTs, and a block of IO addresses 654 * access the external UARTs. 655 */ 656 { 0x14d2, 0x8080, 0xffff, 0, 657 "Titan VScom PCI-800L", 658 DEFAULT_RCLK * 8, 659 PUC_PORT_8S, 0x14, -1, -1, 660 .config_function = puc_config_titan 661 }, 662 663 /* 664 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 665 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 666 * device ID 3 and PCI device 1 device ID 4. 667 */ 668 { 0x14d2, 0xa003, 0xffff, 0, 669 "Titan PCI-800H", 670 DEFAULT_RCLK * 8, 671 PUC_PORT_4S, 0x10, 0, 8, 672 }, 673 { 0x14d2, 0xa004, 0xffff, 0, 674 "Titan PCI-800H", 675 DEFAULT_RCLK * 8, 676 PUC_PORT_4S, 0x10, 0, 8, 677 }, 678 679 { 0x14d2, 0xa005, 0xffff, 0, 680 "Titan PCI-200H", 681 DEFAULT_RCLK * 8, 682 PUC_PORT_2S, 0x10, 0, 8, 683 }, 684 685 { 0x14d2, 0xe020, 0xffff, 0, 686 "Titan VScom PCI-200HV2", 687 DEFAULT_RCLK * 8, 688 PUC_PORT_2S, 0x10, 4, 0, 689 }, 690 691 { 0x14db, 0x2130, 0xffff, 0, 692 "Avlab Technology, PCI IO 2S", 693 DEFAULT_RCLK, 694 PUC_PORT_2S, 0x10, 4, 0, 695 }, 696 697 { 0x14db, 0x2150, 0xffff, 0, 698 "Avlab Low Profile PCI 4 Serial", 699 DEFAULT_RCLK, 700 PUC_PORT_4S, 0x10, 4, 0, 701 }, 702 703 { 0x14db, 0x2152, 0xffff, 0, 704 "Avlab Low Profile PCI 4 Serial", 705 DEFAULT_RCLK, 706 PUC_PORT_4S, 0x10, 4, 0, 707 }, 708 709 { 0x1592, 0x0781, 0xffff, 0, 710 "Syba Tech Ltd. PCI-4S2P-550-ECP", 711 DEFAULT_RCLK, 712 PUC_PORT_4S1P, 0x10, 0, -1, 713 .config_function = puc_config_syba 714 }, 715 716 { 0x6666, 0x0001, 0xffff, 0, 717 "Decision Computer Inc, PCCOM 4-port serial", 718 DEFAULT_RCLK, 719 PUC_PORT_4S, 0x1c, 0, 8, 720 }, 721 722 { 0x6666, 0x0002, 0xffff, 0, 723 "Decision Computer Inc, PCCOM 8-port serial", 724 DEFAULT_RCLK, 725 PUC_PORT_8S, 0x1c, 0, 8, 726 }, 727 728 { 0x6666, 0x0004, 0xffff, 0, 729 "PCCOM dual port RS232/422/485", 730 DEFAULT_RCLK, 731 PUC_PORT_2S, 0x1c, 0, 8, 732 }, 733 734 { 0x9710, 0x9815, 0xffff, 0, 735 "NetMos NM9815 Dual 1284 Printer port", 736 0, 737 PUC_PORT_2P, 0x10, 8, 0, 738 }, 739 740 { 0x9710, 0x9835, 0xffff, 0, 741 "NetMos NM9835 Dual UART and 1284 Printer port", 742 DEFAULT_RCLK, 743 PUC_PORT_2S1P, 0x10, 4, 0, 744 }, 745 746 { 0x9710, 0x9845, 0x1000, 0x0006, 747 "NetMos NM9845 6 Port UART", 748 DEFAULT_RCLK, 749 PUC_PORT_6S, 0x10, 4, 0, 750 }, 751 752 { 0x9710, 0x9845, 0xffff, 0, 753 "NetMos NM9845 Quad UART and 1284 Printer port", 754 DEFAULT_RCLK, 755 PUC_PORT_4S1P, 0x10, 4, 0, 756 }, 757 758 { 0xb00c, 0x021c, 0xffff, 0, 759 "IC Book Labs Gunboat x4 Lite", 760 DEFAULT_RCLK, 761 PUC_PORT_4S, 0x10, 0, 8, 762 .config_function = puc_config_icbook 763 }, 764 765 { 0xb00c, 0x031c, 0xffff, 0, 766 "IC Book Labs Gunboat x4 Pro", 767 DEFAULT_RCLK, 768 PUC_PORT_4S, 0x10, 0, 8, 769 .config_function = puc_config_icbook 770 }, 771 772 { 0xb00c, 0x041c, 0xffff, 0, 773 "IC Book Labs Ironclad x8 Lite", 774 DEFAULT_RCLK, 775 PUC_PORT_8S, 0x10, 0, 8, 776 .config_function = puc_config_icbook 777 }, 778 779 { 0xb00c, 0x051c, 0xffff, 0, 780 "IC Book Labs Ironclad x8 Pro", 781 DEFAULT_RCLK, 782 PUC_PORT_8S, 0x10, 0, 8, 783 .config_function = puc_config_icbook 784 }, 785 786 { 0xb00c, 0x081c, 0xffff, 0, 787 "IC Book Labs Dreadnought x16 Pro", 788 DEFAULT_RCLK * 8, 789 PUC_PORT_16S, 0x10, 0, 8, 790 .config_function = puc_config_icbook 791 }, 792 793 { 0xb00c, 0x091c, 0xffff, 0, 794 "IC Book Labs Dreadnought x16 Lite", 795 DEFAULT_RCLK, 796 PUC_PORT_16S, 0x10, 0, 8, 797 .config_function = puc_config_icbook 798 }, 799 800 { 0xb00c, 0x0a1c, 0xffff, 0, 801 "IC Book Labs Gunboat x2 Low Profile", 802 DEFAULT_RCLK, 803 PUC_PORT_2S, 0x10, 0, 8, 804 }, 805 806 { 0xb00c, 0x0b1c, 0xffff, 0, 807 "IC Book Labs Gunboat x4 Low Profile", 808 DEFAULT_RCLK, 809 PUC_PORT_4S, 0x10, 0, 8, 810 .config_function = puc_config_icbook 811 }, 812 813 { 0xffff, 0, 0xffff, 0, NULL, 0 } 814 }; 815 816 static int 817 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 818 intptr_t *res) 819 { 820 switch (cmd) { 821 case PUC_CFG_GET_OFS: 822 *res = 8 * (port & 1); 823 return (0); 824 case PUC_CFG_GET_RID: 825 *res = 0x14 + (port >> 1) * 4; 826 return (0); 827 default: 828 break; 829 } 830 return (ENXIO); 831 } 832 833 static int 834 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 835 intptr_t *res) 836 { 837 if (cmd == PUC_CFG_GET_OFS) { 838 *res = port * 0x200; 839 return (0); 840 } 841 return (ENXIO); 842 } 843 844 static int 845 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 846 intptr_t *res) 847 { 848 const struct puc_cfg *cfg = sc->sc_cfg; 849 850 if (cmd == PUC_CFG_GET_OFS) { 851 if (cfg->subdevice == 0x1282) /* Everest SP */ 852 port <<= 1; 853 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 854 port = (port == 3) ? 4 : port; 855 *res = port * 8 + ((port > 2) ? 0x18 : 0); 856 return (0); 857 } 858 return (ENXIO); 859 } 860 861 static int 862 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 863 intptr_t *res) 864 { 865 if (cmd == PUC_CFG_GET_ILR) { 866 *res = PUC_ILR_DIGI; 867 return (0); 868 } 869 return (ENXIO); 870 } 871 872 static int 873 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 874 intptr_t *res) 875 { 876 const struct puc_cfg *cfg = sc->sc_cfg; 877 struct puc_bar *bar; 878 uint8_t v0, v1; 879 880 switch (cmd) { 881 case PUC_CFG_SETUP: 882 /* 883 * Check if the scratchpad register is enabled or if the 884 * interrupt status and options registers are active. 885 */ 886 bar = puc_get_bar(sc, cfg->rid); 887 if (bar == NULL) 888 return (ENXIO); 889 /* Set DLAB in the LCR register of UART 0. */ 890 bus_write_1(bar->b_res, 3, 0x80); 891 /* Write 0 to the SPR register of UART 0. */ 892 bus_write_1(bar->b_res, 7, 0); 893 /* Read back the contents of the SPR register of UART 0. */ 894 v0 = bus_read_1(bar->b_res, 7); 895 /* Write a specific value to the SPR register of UART 0. */ 896 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock); 897 /* Read back the contents of the SPR register of UART 0. */ 898 v1 = bus_read_1(bar->b_res, 7); 899 /* Clear DLAB in the LCR register of UART 0. */ 900 bus_write_1(bar->b_res, 3, 0); 901 /* Save the two values read-back from the SPR register. */ 902 sc->sc_cfg_data = (v0 << 8) | v1; 903 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 904 /* 905 * The SPR register echoed the two values written 906 * by us. This means that the SPAD jumper is set. 907 */ 908 device_printf(sc->sc_dev, "warning: extra features " 909 "not usable -- SPAD compatibility enabled\n"); 910 return (0); 911 } 912 if (v0 != 0) { 913 /* 914 * The first value doesn't match. This can only mean 915 * that the SPAD jumper is not set and that a non- 916 * standard fixed clock multiplier jumper is set. 917 */ 918 if (bootverbose) 919 device_printf(sc->sc_dev, "fixed clock rate " 920 "multiplier of %d\n", 1 << v0); 921 if (v0 < -cfg->clock) 922 device_printf(sc->sc_dev, "warning: " 923 "suboptimal fixed clock rate multiplier " 924 "setting\n"); 925 return (0); 926 } 927 /* 928 * The first value matched, but the second didn't. We know 929 * that the SPAD jumper is not set. We also know that the 930 * clock rate multiplier is software controlled *and* that 931 * we just programmed it to the maximum allowed. 932 */ 933 if (bootverbose) 934 device_printf(sc->sc_dev, "clock rate multiplier of " 935 "%d selected\n", 1 << -cfg->clock); 936 return (0); 937 case PUC_CFG_GET_CLOCK: 938 v0 = (sc->sc_cfg_data >> 8) & 0xff; 939 v1 = sc->sc_cfg_data & 0xff; 940 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 941 /* 942 * XXX With the SPAD jumper applied, there's no 943 * easy way of knowing if there's also a clock 944 * rate multiplier jumper installed. Let's hope 945 * not... 946 */ 947 *res = DEFAULT_RCLK; 948 } else if (v0 == 0) { 949 /* 950 * No clock rate multiplier jumper installed, 951 * so we programmed the board with the maximum 952 * multiplier allowed as given to us in the 953 * clock field of the config record (negated). 954 */ 955 *res = DEFAULT_RCLK << -cfg->clock; 956 } else 957 *res = DEFAULT_RCLK << v0; 958 return (0); 959 case PUC_CFG_GET_ILR: 960 v0 = (sc->sc_cfg_data >> 8) & 0xff; 961 v1 = sc->sc_cfg_data & 0xff; 962 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) 963 ? PUC_ILR_NONE : PUC_ILR_QUATECH; 964 return (0); 965 default: 966 break; 967 } 968 return (ENXIO); 969 } 970 971 static int 972 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 973 intptr_t *res) 974 { 975 static int base[] = { 0x251, 0x3f0, 0 }; 976 const struct puc_cfg *cfg = sc->sc_cfg; 977 struct puc_bar *bar; 978 int efir, idx, ofs; 979 uint8_t v; 980 981 switch (cmd) { 982 case PUC_CFG_SETUP: 983 bar = puc_get_bar(sc, cfg->rid); 984 if (bar == NULL) 985 return (ENXIO); 986 987 /* configure both W83877TFs */ 988 bus_write_1(bar->b_res, 0x250, 0x89); 989 bus_write_1(bar->b_res, 0x3f0, 0x87); 990 bus_write_1(bar->b_res, 0x3f0, 0x87); 991 idx = 0; 992 while (base[idx] != 0) { 993 efir = base[idx]; 994 bus_write_1(bar->b_res, efir, 0x09); 995 v = bus_read_1(bar->b_res, efir + 1); 996 if ((v & 0x0f) != 0x0c) 997 return (ENXIO); 998 bus_write_1(bar->b_res, efir, 0x16); 999 v = bus_read_1(bar->b_res, efir + 1); 1000 bus_write_1(bar->b_res, efir, 0x16); 1001 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1002 bus_write_1(bar->b_res, efir, 0x16); 1003 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1004 ofs = base[idx] & 0x300; 1005 bus_write_1(bar->b_res, efir, 0x23); 1006 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1007 bus_write_1(bar->b_res, efir, 0x24); 1008 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1009 bus_write_1(bar->b_res, efir, 0x25); 1010 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1011 bus_write_1(bar->b_res, efir, 0x17); 1012 bus_write_1(bar->b_res, efir + 1, 0x03); 1013 bus_write_1(bar->b_res, efir, 0x28); 1014 bus_write_1(bar->b_res, efir + 1, 0x43); 1015 idx++; 1016 } 1017 bus_write_1(bar->b_res, 0x250, 0xaa); 1018 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1019 return (0); 1020 case PUC_CFG_GET_OFS: 1021 switch (port) { 1022 case 0: 1023 *res = 0x2f8; 1024 return (0); 1025 case 1: 1026 *res = 0x2e8; 1027 return (0); 1028 case 2: 1029 *res = 0x3f8; 1030 return (0); 1031 case 3: 1032 *res = 0x3e8; 1033 return (0); 1034 case 4: 1035 *res = 0x278; 1036 return (0); 1037 } 1038 break; 1039 default: 1040 break; 1041 } 1042 return (ENXIO); 1043 } 1044 1045 static int 1046 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1047 intptr_t *res) 1048 { 1049 const struct puc_cfg *cfg = sc->sc_cfg; 1050 1051 switch (cmd) { 1052 case PUC_CFG_GET_OFS: 1053 if (cfg->ports == PUC_PORT_8S) { 1054 *res = (port > 4) ? 8 * (port - 4) : 0; 1055 return (0); 1056 } 1057 break; 1058 case PUC_CFG_GET_RID: 1059 if (cfg->ports == PUC_PORT_8S) { 1060 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1061 return (0); 1062 } 1063 if (cfg->ports == PUC_PORT_2S1P) { 1064 switch (port) { 1065 case 0: *res = 0x10; return (0); 1066 case 1: *res = 0x14; return (0); 1067 case 2: *res = 0x1c; return (0); 1068 } 1069 } 1070 break; 1071 default: 1072 break; 1073 } 1074 return (ENXIO); 1075 } 1076 1077 static int 1078 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1079 intptr_t *res) 1080 { 1081 static uint16_t dual[] = { 1082 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1083 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1084 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1085 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1086 0xD079, 0 1087 }; 1088 static uint16_t quad[] = { 1089 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1090 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1091 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1092 0xB157, 0 1093 }; 1094 static uint16_t octa[] = { 1095 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1096 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1097 }; 1098 static struct { 1099 int ports; 1100 uint16_t *ids; 1101 } subdevs[] = { 1102 { 2, dual }, 1103 { 4, quad }, 1104 { 8, octa }, 1105 { 0, NULL } 1106 }; 1107 static char desc[64]; 1108 int dev, id; 1109 uint16_t subdev; 1110 1111 switch (cmd) { 1112 case PUC_CFG_GET_DESC: 1113 snprintf(desc, sizeof(desc), 1114 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1115 *res = (intptr_t)desc; 1116 return (0); 1117 case PUC_CFG_GET_NPORTS: 1118 subdev = pci_get_subdevice(sc->sc_dev); 1119 dev = 0; 1120 while (subdevs[dev].ports != 0) { 1121 id = 0; 1122 while (subdevs[dev].ids[id] != 0) { 1123 if (subdev == subdevs[dev].ids[id]) { 1124 sc->sc_cfg_data = subdevs[dev].ports; 1125 *res = sc->sc_cfg_data; 1126 return (0); 1127 } 1128 id++; 1129 } 1130 dev++; 1131 } 1132 return (ENXIO); 1133 case PUC_CFG_GET_OFS: 1134 *res = (port == 1 || port == 3) ? 8 : 0; 1135 return (0); 1136 case PUC_CFG_GET_RID: 1137 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1138 return (0); 1139 case PUC_CFG_GET_TYPE: 1140 *res = PUC_TYPE_SERIAL; 1141 return (0); 1142 default: 1143 break; 1144 } 1145 return (ENXIO); 1146 } 1147 1148 static int 1149 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1150 intptr_t *res) 1151 { 1152 switch (cmd) { 1153 case PUC_CFG_GET_OFS: 1154 *res = (port < 3) ? 0 : (port - 2) << 3; 1155 return (0); 1156 case PUC_CFG_GET_RID: 1157 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1158 return (0); 1159 default: 1160 break; 1161 } 1162 return (ENXIO); 1163 } 1164