1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 45 #include <dev/ic/ns16550.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <dev/puc/puc_bus.h> 51 #include <dev/puc/puc_cfg.h> 52 #include <dev/puc/puc_bfe.h> 53 54 static puc_config_f puc_config_advantech; 55 static puc_config_f puc_config_amc; 56 static puc_config_f puc_config_diva; 57 static puc_config_f puc_config_exar; 58 static puc_config_f puc_config_exar_pcie; 59 static puc_config_f puc_config_icbook; 60 static puc_config_f puc_config_moxa; 61 static puc_config_f puc_config_oxford_pci954; 62 static puc_config_f puc_config_oxford_pcie; 63 static puc_config_f puc_config_quatech; 64 static puc_config_f puc_config_syba; 65 static puc_config_f puc_config_siig; 66 static puc_config_f puc_config_sunix; 67 static puc_config_f puc_config_timedia; 68 static puc_config_f puc_config_titan; 69 70 const struct puc_cfg puc_pci_devices[] = { 71 { 0x0009, 0x7168, 0xffff, 0, 72 "Sunix SUN1889", 73 DEFAULT_RCLK * 8, 74 PUC_PORT_2S, 0x10, 0, 8, 75 }, 76 77 { 0x103c, 0x1048, 0x103c, 0x1049, 78 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 79 DEFAULT_RCLK, 80 PUC_PORT_3S, 0x10, 0, -1, 81 .config_function = puc_config_diva 82 }, 83 84 { 0x103c, 0x1048, 0x103c, 0x104a, 85 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 86 DEFAULT_RCLK, 87 PUC_PORT_2S, 0x10, 0, -1, 88 .config_function = puc_config_diva 89 }, 90 91 { 0x103c, 0x1048, 0x103c, 0x104b, 92 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 93 DEFAULT_RCLK, 94 PUC_PORT_4S, 0x10, 0, -1, 95 .config_function = puc_config_diva 96 }, 97 98 { 0x103c, 0x1048, 0x103c, 0x1223, 99 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 100 DEFAULT_RCLK, 101 PUC_PORT_3S, 0x10, 0, -1, 102 .config_function = puc_config_diva 103 }, 104 105 { 0x103c, 0x1048, 0x103c, 0x1226, 106 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 107 DEFAULT_RCLK, 108 PUC_PORT_3S, 0x10, 0, -1, 109 .config_function = puc_config_diva 110 }, 111 112 { 0x103c, 0x1048, 0x103c, 0x1282, 113 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 114 DEFAULT_RCLK, 115 PUC_PORT_3S, 0x10, 0, -1, 116 .config_function = puc_config_diva 117 }, 118 119 { 0x10b5, 0x1076, 0x10b5, 0x1076, 120 "VScom PCI-800", 121 DEFAULT_RCLK * 8, 122 PUC_PORT_8S, 0x18, 0, 8, 123 }, 124 125 { 0x10b5, 0x1077, 0x10b5, 0x1077, 126 "VScom PCI-400", 127 DEFAULT_RCLK * 8, 128 PUC_PORT_4S, 0x18, 0, 8, 129 }, 130 131 { 0x10b5, 0x1103, 0x10b5, 0x1103, 132 "VScom PCI-200", 133 DEFAULT_RCLK * 8, 134 PUC_PORT_2S, 0x18, 4, 0, 135 }, 136 137 /* 138 * Boca Research Turbo Serial 658 (8 serial port) card. 139 * Appears to be the same as Chase Research PLC PCI-FAST8 140 * and Perle PCI-FAST8 Multi-Port serial cards. 141 */ 142 { 0x10b5, 0x9050, 0x12e0, 0x0021, 143 "Boca Research Turbo Serial 658", 144 DEFAULT_RCLK * 4, 145 PUC_PORT_8S, 0x18, 0, 8, 146 }, 147 148 { 0x10b5, 0x9050, 0x12e0, 0x0031, 149 "Boca Research Turbo Serial 654", 150 DEFAULT_RCLK * 4, 151 PUC_PORT_4S, 0x18, 0, 8, 152 }, 153 154 /* 155 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 156 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 157 * into the subsystem fields, and claims that it's a 158 * network/misc (0x02/0x80) device. 159 */ 160 { 0x10b5, 0x9050, 0xd84d, 0x6808, 161 "Dolphin Peripherals 4035", 162 DEFAULT_RCLK, 163 PUC_PORT_2S, 0x18, 4, 0, 164 }, 165 166 /* 167 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 168 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 169 * into the subsystem fields, and claims that it's a 170 * network/misc (0x02/0x80) device. 171 */ 172 { 0x10b5, 0x9050, 0xd84d, 0x6810, 173 "Dolphin Peripherals 4014", 174 0, 175 PUC_PORT_2P, 0x20, 4, 0, 176 }, 177 178 { 0x10e8, 0x818e, 0xffff, 0, 179 "Applied Micro Circuits 8 Port UART", 180 DEFAULT_RCLK, 181 PUC_PORT_8S, 0x14, -1, -1, 182 .config_function = puc_config_amc 183 }, 184 185 /* 186 * The following members of the Digi International Neo series are 187 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV. 188 * Accordingly, the PCIe versions of these cards incorporate a PLX 189 * PCIe-PCI-bridge. 190 */ 191 192 { 0x114f, 0x00b0, 0xffff, 0, 193 "Digi Neo PCI 4 Port", 194 DEFAULT_RCLK * 8, 195 PUC_PORT_4S, 0x10, 0, -1, 196 .config_function = puc_config_exar 197 }, 198 199 { 0x114f, 0x00b1, 0xffff, 0, 200 "Digi Neo PCI 8 Port", 201 DEFAULT_RCLK * 8, 202 PUC_PORT_8S, 0x10, 0, -1, 203 .config_function = puc_config_exar 204 }, 205 206 { 0x114f, 0x00f0, 0xffff, 0, 207 "Digi Neo PCIe 8 Port", 208 DEFAULT_RCLK * 8, 209 PUC_PORT_8S, 0x10, 0, -1, 210 .config_function = puc_config_exar 211 }, 212 213 { 0x114f, 0x00f1, 0xffff, 0, 214 "Digi Neo PCIe 4 Port", 215 DEFAULT_RCLK * 8, 216 PUC_PORT_4S, 0x10, 0, -1, 217 .config_function = puc_config_exar 218 }, 219 220 { 0x114f, 0x00f2, 0xffff, 0, 221 "Digi Neo PCIe 4 Port RJ45", 222 DEFAULT_RCLK * 8, 223 PUC_PORT_4S, 0x10, 0, -1, 224 .config_function = puc_config_exar 225 }, 226 227 { 0x114f, 0x00f3, 0xffff, 0, 228 "Digi Neo PCIe 8 Port RJ45", 229 DEFAULT_RCLK * 8, 230 PUC_PORT_8S, 0x10, 0, -1, 231 .config_function = puc_config_exar 232 }, 233 234 { 0x11fe, 0x8010, 0xffff, 0, 235 "Comtrol RocketPort 550/8 RJ11 part A", 236 DEFAULT_RCLK * 4, 237 PUC_PORT_4S, 0x10, 0, 8, 238 }, 239 240 { 0x11fe, 0x8011, 0xffff, 0, 241 "Comtrol RocketPort 550/8 RJ11 part B", 242 DEFAULT_RCLK * 4, 243 PUC_PORT_4S, 0x10, 0, 8, 244 }, 245 246 { 0x11fe, 0x8012, 0xffff, 0, 247 "Comtrol RocketPort 550/8 Octa part A", 248 DEFAULT_RCLK * 4, 249 PUC_PORT_4S, 0x10, 0, 8, 250 }, 251 252 { 0x11fe, 0x8013, 0xffff, 0, 253 "Comtrol RocketPort 550/8 Octa part B", 254 DEFAULT_RCLK * 4, 255 PUC_PORT_4S, 0x10, 0, 8, 256 }, 257 258 { 0x11fe, 0x8014, 0xffff, 0, 259 "Comtrol RocketPort 550/4 RJ45", 260 DEFAULT_RCLK * 4, 261 PUC_PORT_4S, 0x10, 0, 8, 262 }, 263 264 { 0x11fe, 0x8015, 0xffff, 0, 265 "Comtrol RocketPort 550/Quad", 266 DEFAULT_RCLK * 4, 267 PUC_PORT_4S, 0x10, 0, 8, 268 }, 269 270 { 0x11fe, 0x8016, 0xffff, 0, 271 "Comtrol RocketPort 550/16 part A", 272 DEFAULT_RCLK * 4, 273 PUC_PORT_4S, 0x10, 0, 8, 274 }, 275 276 { 0x11fe, 0x8017, 0xffff, 0, 277 "Comtrol RocketPort 550/16 part B", 278 DEFAULT_RCLK * 4, 279 PUC_PORT_12S, 0x10, 0, 8, 280 }, 281 282 { 0x11fe, 0x8018, 0xffff, 0, 283 "Comtrol RocketPort 550/8 part A", 284 DEFAULT_RCLK * 4, 285 PUC_PORT_4S, 0x10, 0, 8, 286 }, 287 288 { 0x11fe, 0x8019, 0xffff, 0, 289 "Comtrol RocketPort 550/8 part B", 290 DEFAULT_RCLK * 4, 291 PUC_PORT_4S, 0x10, 0, 8, 292 }, 293 294 /* 295 * IBM SurePOS 300 Series (481033H) serial ports 296 * Details can be found on the IBM RSS websites 297 */ 298 299 { 0x1014, 0x0297, 0xffff, 0, 300 "IBM SurePOS 300 Series (481033H) serial ports", 301 DEFAULT_RCLK, 302 PUC_PORT_4S, 0x10, 4, 0 303 }, 304 305 /* 306 * SIIG Boards. 307 * 308 * SIIG provides documentation for their boards at: 309 * <URL:http://www.siig.com/downloads.asp> 310 */ 311 312 { 0x131f, 0x1010, 0xffff, 0, 313 "SIIG Cyber I/O PCI 16C550 (10x family)", 314 DEFAULT_RCLK, 315 PUC_PORT_1S1P, 0x18, 4, 0, 316 }, 317 318 { 0x131f, 0x1011, 0xffff, 0, 319 "SIIG Cyber I/O PCI 16C650 (10x family)", 320 DEFAULT_RCLK, 321 PUC_PORT_1S1P, 0x18, 4, 0, 322 }, 323 324 { 0x131f, 0x1012, 0xffff, 0, 325 "SIIG Cyber I/O PCI 16C850 (10x family)", 326 DEFAULT_RCLK, 327 PUC_PORT_1S1P, 0x18, 4, 0, 328 }, 329 330 { 0x131f, 0x1021, 0xffff, 0, 331 "SIIG Cyber Parallel Dual PCI (10x family)", 332 0, 333 PUC_PORT_2P, 0x18, 8, 0, 334 }, 335 336 { 0x131f, 0x1030, 0xffff, 0, 337 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 338 DEFAULT_RCLK, 339 PUC_PORT_2S, 0x18, 4, 0, 340 }, 341 342 { 0x131f, 0x1031, 0xffff, 0, 343 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 344 DEFAULT_RCLK, 345 PUC_PORT_2S, 0x18, 4, 0, 346 }, 347 348 { 0x131f, 0x1032, 0xffff, 0, 349 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 350 DEFAULT_RCLK, 351 PUC_PORT_2S, 0x18, 4, 0, 352 }, 353 354 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 355 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 356 DEFAULT_RCLK, 357 PUC_PORT_2S1P, 0x18, 4, 0, 358 }, 359 360 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 361 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 362 DEFAULT_RCLK, 363 PUC_PORT_2S1P, 0x18, 4, 0, 364 }, 365 366 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 367 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 368 DEFAULT_RCLK, 369 PUC_PORT_2S1P, 0x18, 4, 0, 370 }, 371 372 { 0x131f, 0x1050, 0xffff, 0, 373 "SIIG Cyber 4S PCI 16C550 (10x family)", 374 DEFAULT_RCLK, 375 PUC_PORT_4S, 0x18, 4, 0, 376 }, 377 378 { 0x131f, 0x1051, 0xffff, 0, 379 "SIIG Cyber 4S PCI 16C650 (10x family)", 380 DEFAULT_RCLK, 381 PUC_PORT_4S, 0x18, 4, 0, 382 }, 383 384 { 0x131f, 0x1052, 0xffff, 0, 385 "SIIG Cyber 4S PCI 16C850 (10x family)", 386 DEFAULT_RCLK, 387 PUC_PORT_4S, 0x18, 4, 0, 388 }, 389 390 { 0x131f, 0x2010, 0xffff, 0, 391 "SIIG Cyber I/O PCI 16C550 (20x family)", 392 DEFAULT_RCLK, 393 PUC_PORT_1S1P, 0x10, 4, 0, 394 }, 395 396 { 0x131f, 0x2011, 0xffff, 0, 397 "SIIG Cyber I/O PCI 16C650 (20x family)", 398 DEFAULT_RCLK, 399 PUC_PORT_1S1P, 0x10, 4, 0, 400 }, 401 402 { 0x131f, 0x2012, 0xffff, 0, 403 "SIIG Cyber I/O PCI 16C850 (20x family)", 404 DEFAULT_RCLK, 405 PUC_PORT_1S1P, 0x10, 4, 0, 406 }, 407 408 { 0x131f, 0x2021, 0xffff, 0, 409 "SIIG Cyber Parallel Dual PCI (20x family)", 410 0, 411 PUC_PORT_2P, 0x10, 8, 0, 412 }, 413 414 { 0x131f, 0x2030, 0xffff, 0, 415 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 416 DEFAULT_RCLK, 417 PUC_PORT_2S, 0x10, 4, 0, 418 }, 419 420 { 0x131f, 0x2031, 0xffff, 0, 421 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 422 DEFAULT_RCLK, 423 PUC_PORT_2S, 0x10, 4, 0, 424 }, 425 426 { 0x131f, 0x2032, 0xffff, 0, 427 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 428 DEFAULT_RCLK, 429 PUC_PORT_2S, 0x10, 4, 0, 430 }, 431 432 { 0x131f, 0x2040, 0xffff, 0, 433 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 434 DEFAULT_RCLK, 435 PUC_PORT_1S2P, 0x10, -1, 0, 436 .config_function = puc_config_siig 437 }, 438 439 { 0x131f, 0x2041, 0xffff, 0, 440 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 441 DEFAULT_RCLK, 442 PUC_PORT_1S2P, 0x10, -1, 0, 443 .config_function = puc_config_siig 444 }, 445 446 { 0x131f, 0x2042, 0xffff, 0, 447 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 448 DEFAULT_RCLK, 449 PUC_PORT_1S2P, 0x10, -1, 0, 450 .config_function = puc_config_siig 451 }, 452 453 { 0x131f, 0x2050, 0xffff, 0, 454 "SIIG Cyber 4S PCI 16C550 (20x family)", 455 DEFAULT_RCLK, 456 PUC_PORT_4S, 0x10, 4, 0, 457 }, 458 459 { 0x131f, 0x2051, 0xffff, 0, 460 "SIIG Cyber 4S PCI 16C650 (20x family)", 461 DEFAULT_RCLK, 462 PUC_PORT_4S, 0x10, 4, 0, 463 }, 464 465 { 0x131f, 0x2052, 0xffff, 0, 466 "SIIG Cyber 4S PCI 16C850 (20x family)", 467 DEFAULT_RCLK, 468 PUC_PORT_4S, 0x10, 4, 0, 469 }, 470 471 { 0x131f, 0x2060, 0xffff, 0, 472 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 473 DEFAULT_RCLK, 474 PUC_PORT_2S1P, 0x10, 4, 0, 475 }, 476 477 { 0x131f, 0x2061, 0xffff, 0, 478 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 479 DEFAULT_RCLK, 480 PUC_PORT_2S1P, 0x10, 4, 0, 481 }, 482 483 { 0x131f, 0x2062, 0xffff, 0, 484 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 485 DEFAULT_RCLK, 486 PUC_PORT_2S1P, 0x10, 4, 0, 487 }, 488 489 { 0x131f, 0x2081, 0xffff, 0, 490 "SIIG PS8000 8S PCI 16C650 (20x family)", 491 DEFAULT_RCLK, 492 PUC_PORT_8S, 0x10, -1, -1, 493 .config_function = puc_config_siig 494 }, 495 496 { 0x135c, 0x0010, 0xffff, 0, 497 "Quatech QSC-100", 498 -3, /* max 8x clock rate */ 499 PUC_PORT_4S, 0x14, 0, 8, 500 .config_function = puc_config_quatech 501 }, 502 503 { 0x135c, 0x0020, 0xffff, 0, 504 "Quatech DSC-100", 505 -1, /* max 2x clock rate */ 506 PUC_PORT_2S, 0x14, 0, 8, 507 .config_function = puc_config_quatech 508 }, 509 510 { 0x135c, 0x0030, 0xffff, 0, 511 "Quatech DSC-200/300", 512 -1, /* max 2x clock rate */ 513 PUC_PORT_2S, 0x14, 0, 8, 514 .config_function = puc_config_quatech 515 }, 516 517 { 0x135c, 0x0040, 0xffff, 0, 518 "Quatech QSC-200/300", 519 -3, /* max 8x clock rate */ 520 PUC_PORT_4S, 0x14, 0, 8, 521 .config_function = puc_config_quatech 522 }, 523 524 { 0x135c, 0x0050, 0xffff, 0, 525 "Quatech ESC-100D", 526 -3, /* max 8x clock rate */ 527 PUC_PORT_8S, 0x14, 0, 8, 528 .config_function = puc_config_quatech 529 }, 530 531 { 0x135c, 0x0060, 0xffff, 0, 532 "Quatech ESC-100M", 533 -3, /* max 8x clock rate */ 534 PUC_PORT_8S, 0x14, 0, 8, 535 .config_function = puc_config_quatech 536 }, 537 538 { 0x135c, 0x0170, 0xffff, 0, 539 "Quatech QSCLP-100", 540 -1, /* max 2x clock rate */ 541 PUC_PORT_4S, 0x18, 0, 8, 542 .config_function = puc_config_quatech 543 }, 544 545 { 0x135c, 0x0180, 0xffff, 0, 546 "Quatech DSCLP-100", 547 -1, /* max 3x clock rate */ 548 PUC_PORT_2S, 0x18, 0, 8, 549 .config_function = puc_config_quatech 550 }, 551 552 { 0x135c, 0x01b0, 0xffff, 0, 553 "Quatech DSCLP-200/300", 554 -1, /* max 2x clock rate */ 555 PUC_PORT_2S, 0x18, 0, 8, 556 .config_function = puc_config_quatech 557 }, 558 559 { 0x135c, 0x01e0, 0xffff, 0, 560 "Quatech ESCLP-100", 561 -3, /* max 8x clock rate */ 562 PUC_PORT_8S, 0x10, 0, 8, 563 .config_function = puc_config_quatech 564 }, 565 566 { 0x1393, 0x1024, 0xffff, 0, 567 "Moxa Technologies, Smartio CP-102E/PCIe", 568 DEFAULT_RCLK * 8, 569 PUC_PORT_2S, 0x14, 0, -1, 570 .config_function = puc_config_moxa 571 }, 572 573 { 0x1393, 0x1025, 0xffff, 0, 574 "Moxa Technologies, Smartio CP-102EL/PCIe", 575 DEFAULT_RCLK * 8, 576 PUC_PORT_2S, 0x14, 0, -1, 577 .config_function = puc_config_moxa 578 }, 579 580 { 0x1393, 0x1040, 0xffff, 0, 581 "Moxa Technologies, Smartio C104H/PCI", 582 DEFAULT_RCLK * 8, 583 PUC_PORT_4S, 0x18, 0, 8, 584 }, 585 586 { 0x1393, 0x1041, 0xffff, 0, 587 "Moxa Technologies, Smartio CP-104UL/PCI", 588 DEFAULT_RCLK * 8, 589 PUC_PORT_4S, 0x18, 0, 8, 590 }, 591 592 { 0x1393, 0x1042, 0xffff, 0, 593 "Moxa Technologies, Smartio CP-104JU/PCI", 594 DEFAULT_RCLK * 8, 595 PUC_PORT_4S, 0x18, 0, 8, 596 }, 597 598 { 0x1393, 0x1043, 0xffff, 0, 599 "Moxa Technologies, Smartio CP-104EL/PCIe", 600 DEFAULT_RCLK * 8, 601 PUC_PORT_4S, 0x18, 0, 8, 602 }, 603 604 { 0x1393, 0x1045, 0xffff, 0, 605 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 606 DEFAULT_RCLK * 8, 607 PUC_PORT_4S, 0x14, 0, -1, 608 .config_function = puc_config_moxa 609 }, 610 611 { 0x1393, 0x1120, 0xffff, 0, 612 "Moxa Technologies, CP-112UL", 613 DEFAULT_RCLK * 8, 614 PUC_PORT_2S, 0x18, 0, 8, 615 }, 616 617 { 0x1393, 0x1141, 0xffff, 0, 618 "Moxa Technologies, Industio CP-114", 619 DEFAULT_RCLK * 8, 620 PUC_PORT_4S, 0x18, 0, 8, 621 }, 622 623 { 0x1393, 0x1144, 0xffff, 0, 624 "Moxa Technologies, Smartio CP-114EL/PCIe", 625 DEFAULT_RCLK * 8, 626 PUC_PORT_4S, 0x14, 0, -1, 627 .config_function = puc_config_moxa 628 }, 629 630 { 0x1393, 0x1182, 0xffff, 0, 631 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 632 DEFAULT_RCLK * 8, 633 PUC_PORT_8S, 0x14, 0, -1, 634 .config_function = puc_config_moxa 635 }, 636 637 { 0x1393, 0x1680, 0xffff, 0, 638 "Moxa Technologies, C168H/PCI", 639 DEFAULT_RCLK * 8, 640 PUC_PORT_8S, 0x18, 0, 8, 641 }, 642 643 { 0x1393, 0x1681, 0xffff, 0, 644 "Moxa Technologies, C168U/PCI", 645 DEFAULT_RCLK * 8, 646 PUC_PORT_8S, 0x18, 0, 8, 647 }, 648 649 { 0x1393, 0x1682, 0xffff, 0, 650 "Moxa Technologies, CP-168EL/PCIe", 651 DEFAULT_RCLK * 8, 652 PUC_PORT_8S, 0x18, 0, 8, 653 }, 654 655 { 0x1393, 0x1683, 0xffff, 0, 656 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 657 DEFAULT_RCLK * 8, 658 PUC_PORT_8S, 0x14, 0, -1, 659 .config_function = puc_config_moxa 660 }, 661 662 { 0x13a8, 0x0152, 0xffff, 0, 663 "Exar XR17C/D152", 664 DEFAULT_RCLK * 8, 665 PUC_PORT_2S, 0x10, 0, -1, 666 .config_function = puc_config_exar 667 }, 668 669 { 0x13a8, 0x0154, 0xffff, 0, 670 "Exar XR17C154", 671 DEFAULT_RCLK * 8, 672 PUC_PORT_4S, 0x10, 0, -1, 673 .config_function = puc_config_exar 674 }, 675 676 { 0x13a8, 0x0158, 0xffff, 0, 677 "Exar XR17C158", 678 DEFAULT_RCLK * 8, 679 PUC_PORT_8S, 0x10, 0, -1, 680 .config_function = puc_config_exar 681 }, 682 683 { 0x13a8, 0x0258, 0xffff, 0, 684 "Exar XR17V258IV", 685 DEFAULT_RCLK * 8, 686 PUC_PORT_8S, 0x10, 0, -1, 687 .config_function = puc_config_exar 688 }, 689 690 { 0x13a8, 0x0352, 0xffff, 0, 691 "Exar XR17V352", 692 125000000, 693 PUC_PORT_2S, 0x10, 0, -1, 694 .config_function = puc_config_exar_pcie 695 }, 696 697 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 698 { 0x13a8, 0x0358, 0xffff, 0, 699 "Exar XR17V358", 700 125000000, 701 PUC_PORT_8S, 0x10, 0, -1, 702 .config_function = puc_config_exar_pcie 703 }, 704 705 /* 706 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford 707 * Semiconductor OXuPCI954. Note these boards have a hardware bug in 708 * that they drive the RS-422/485 transmitters after power-on until a 709 * driver initializes the UARTs. 710 */ 711 { 0x13fe, 0x1600, 0x1602, 0x0002, 712 "Advantech PCI-1602 Rev. A", 713 DEFAULT_RCLK * 8, 714 PUC_PORT_2S, 0x10, 0, 8, 715 .config_function = puc_config_advantech 716 }, 717 718 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */ 719 { 0x13fe, 0xa102, 0x13fe, 0xa102, 720 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)", 721 DEFAULT_RCLK * 8, 722 PUC_PORT_2S, 0x10, 4, 0, 723 .config_function = puc_config_advantech 724 }, 725 726 { 0x1407, 0x0100, 0xffff, 0, 727 "Lava Computers Dual Serial", 728 DEFAULT_RCLK, 729 PUC_PORT_2S, 0x10, 4, 0, 730 }, 731 732 { 0x1407, 0x0101, 0xffff, 0, 733 "Lava Computers Quatro A", 734 DEFAULT_RCLK, 735 PUC_PORT_2S, 0x10, 4, 0, 736 }, 737 738 { 0x1407, 0x0102, 0xffff, 0, 739 "Lava Computers Quatro B", 740 DEFAULT_RCLK, 741 PUC_PORT_2S, 0x10, 4, 0, 742 }, 743 744 { 0x1407, 0x0120, 0xffff, 0, 745 "Lava Computers Quattro-PCI A", 746 DEFAULT_RCLK, 747 PUC_PORT_2S, 0x10, 4, 0, 748 }, 749 750 { 0x1407, 0x0121, 0xffff, 0, 751 "Lava Computers Quattro-PCI B", 752 DEFAULT_RCLK, 753 PUC_PORT_2S, 0x10, 4, 0, 754 }, 755 756 { 0x1407, 0x0180, 0xffff, 0, 757 "Lava Computers Octo A", 758 DEFAULT_RCLK, 759 PUC_PORT_4S, 0x10, 4, 0, 760 }, 761 762 { 0x1407, 0x0181, 0xffff, 0, 763 "Lava Computers Octo B", 764 DEFAULT_RCLK, 765 PUC_PORT_4S, 0x10, 4, 0, 766 }, 767 768 { 0x1409, 0x7268, 0xffff, 0, 769 "Sunix SUN1888", 770 0, 771 PUC_PORT_2P, 0x10, 0, 8, 772 }, 773 774 { 0x1409, 0x7168, 0xffff, 0, 775 NULL, 776 DEFAULT_RCLK * 8, 777 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 778 .config_function = puc_config_timedia 779 }, 780 781 /* 782 * Boards with an Oxford Semiconductor chip. 783 * 784 * Oxford Semiconductor provides documentation for their chip at: 785 * <URL:http://www.plxtech.com/products/uart/> 786 * 787 * As sold by Kouwell <URL:http://www.kouwell.com/>. 788 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 789 */ 790 { 791 0x1415, 0x9501, 0x10fc, 0xc070, 792 "I-O DATA RSA-PCI2/R", 793 DEFAULT_RCLK * 8, 794 PUC_PORT_2S, 0x10, 0, 8, 795 }, 796 797 { 0x1415, 0x9501, 0x131f, 0x2050, 798 "SIIG Cyber 4 PCI 16550", 799 DEFAULT_RCLK * 10, 800 PUC_PORT_4S, 0x10, 0, 8, 801 }, 802 803 { 0x1415, 0x9501, 0x131f, 0x2051, 804 "SIIG Cyber 4S PCI 16C650 (20x family)", 805 DEFAULT_RCLK * 10, 806 PUC_PORT_4S, 0x10, 0, 8, 807 }, 808 809 { 0x1415, 0x9501, 0x131f, 0x2052, 810 "SIIG Quartet Serial 850", 811 DEFAULT_RCLK * 10, 812 PUC_PORT_4S, 0x10, 0, 8, 813 }, 814 815 { 0x1415, 0x9501, 0x14db, 0x2150, 816 "Kuroutoshikou SERIAL4P-LPPCI2", 817 DEFAULT_RCLK * 10, 818 PUC_PORT_4S, 0x10, 0, 8, 819 }, 820 821 { 0x1415, 0x9501, 0xffff, 0, 822 "Oxford Semiconductor OX16PCI954 UARTs", 823 0, 824 PUC_PORT_4S, 0x10, 0, 8, 825 .config_function = puc_config_oxford_pci954 826 }, 827 828 { 0x1415, 0x950a, 0x131f, 0x2030, 829 "SIIG Cyber 2S PCIe", 830 DEFAULT_RCLK * 10, 831 PUC_PORT_2S, 0x10, 0, 8, 832 }, 833 834 { 0x1415, 0x950a, 0x131f, 0x2032, 835 "SIIG Cyber Serial Dual PCI 16C850", 836 DEFAULT_RCLK * 10, 837 PUC_PORT_4S, 0x10, 0, 8, 838 }, 839 840 { 0x1415, 0x950a, 0x131f, 0x2061, 841 "SIIG Cyber 2SP1 PCIe", 842 DEFAULT_RCLK * 10, 843 PUC_PORT_2S, 0x10, 0, 8, 844 }, 845 846 { 0x1415, 0x950a, 0xffff, 0, 847 "Oxford Semiconductor OX16PCI954 UARTs", 848 DEFAULT_RCLK, 849 PUC_PORT_4S, 0x10, 0, 8, 850 }, 851 852 { 0x1415, 0x9511, 0xffff, 0, 853 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 854 DEFAULT_RCLK, 855 PUC_PORT_4S, 0x10, 0, 8, 856 }, 857 858 { 0x1415, 0x9521, 0xffff, 0, 859 "Oxford Semiconductor OX16PCI952 UARTs", 860 DEFAULT_RCLK, 861 PUC_PORT_2S, 0x10, 4, 0, 862 }, 863 864 { 0x1415, 0x9538, 0xffff, 0, 865 "Oxford Semiconductor OX16PCI958 UARTs", 866 DEFAULT_RCLK, 867 PUC_PORT_8S, 0x18, 0, 8, 868 }, 869 870 /* 871 * Perle boards use Oxford Semiconductor chips, but they store the 872 * Oxford Semiconductor device ID as a subvendor device ID and use 873 * their own device IDs. 874 */ 875 876 { 0x155f, 0x0331, 0xffff, 0, 877 "Perle Ultraport4 Express", 878 DEFAULT_RCLK * 8, 879 PUC_PORT_4S, 0x10, 0, 8, 880 }, 881 882 { 0x155f, 0xB012, 0xffff, 0, 883 "Perle Speed2 LE", 884 DEFAULT_RCLK * 8, 885 PUC_PORT_2S, 0x10, 0, 8, 886 }, 887 888 { 0x155f, 0xB022, 0xffff, 0, 889 "Perle Speed2 LE", 890 DEFAULT_RCLK * 8, 891 PUC_PORT_2S, 0x10, 0, 8, 892 }, 893 894 { 0x155f, 0xB004, 0xffff, 0, 895 "Perle Speed4 LE", 896 DEFAULT_RCLK * 8, 897 PUC_PORT_4S, 0x10, 0, 8, 898 }, 899 900 { 0x155f, 0xB008, 0xffff, 0, 901 "Perle Speed8 LE", 902 DEFAULT_RCLK * 8, 903 PUC_PORT_8S, 0x10, 0, 8, 904 }, 905 906 /* 907 * Oxford Semiconductor PCI Express Expresso family 908 * 909 * Found in many 'native' PCI Express serial boards such as: 910 * 911 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 912 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 913 * 914 * Lindy 51189 (4 port) 915 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 916 * 917 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 918 * <URL:http://www.startech.com> 919 */ 920 921 { 0x1415, 0xc11b, 0xffff, 0, 922 "Oxford Semiconductor OXPCIe952 1S1P", 923 DEFAULT_RCLK * 0x22, 924 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 925 .config_function = puc_config_oxford_pcie 926 }, 927 928 { 0x1415, 0xc138, 0xffff, 0, 929 "Oxford Semiconductor OXPCIe952 UARTs", 930 DEFAULT_RCLK * 0x22, 931 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 932 .config_function = puc_config_oxford_pcie 933 }, 934 935 { 0x1415, 0xc158, 0xffff, 0, 936 "Oxford Semiconductor OXPCIe952 UARTs", 937 DEFAULT_RCLK * 0x22, 938 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 939 .config_function = puc_config_oxford_pcie 940 }, 941 942 { 0x1415, 0xc15d, 0xffff, 0, 943 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 944 DEFAULT_RCLK * 0x22, 945 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 946 .config_function = puc_config_oxford_pcie 947 }, 948 949 { 0x1415, 0xc208, 0xffff, 0, 950 "Oxford Semiconductor OXPCIe954 UARTs", 951 DEFAULT_RCLK * 0x22, 952 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 953 .config_function = puc_config_oxford_pcie 954 }, 955 956 { 0x1415, 0xc20d, 0xffff, 0, 957 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 958 DEFAULT_RCLK * 0x22, 959 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 960 .config_function = puc_config_oxford_pcie 961 }, 962 963 { 0x1415, 0xc308, 0xffff, 0, 964 "Oxford Semiconductor OXPCIe958 UARTs", 965 DEFAULT_RCLK * 0x22, 966 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 967 .config_function = puc_config_oxford_pcie 968 }, 969 970 { 0x1415, 0xc30d, 0xffff, 0, 971 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 972 DEFAULT_RCLK * 0x22, 973 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 974 .config_function = puc_config_oxford_pcie 975 }, 976 977 { 0x14d2, 0x8010, 0xffff, 0, 978 "VScom PCI-100L", 979 DEFAULT_RCLK * 8, 980 PUC_PORT_1S, 0x14, 0, 0, 981 }, 982 983 { 0x14d2, 0x8020, 0xffff, 0, 984 "VScom PCI-200L", 985 DEFAULT_RCLK * 8, 986 PUC_PORT_2S, 0x14, 4, 0, 987 }, 988 989 { 0x14d2, 0x8028, 0xffff, 0, 990 "VScom 200Li", 991 DEFAULT_RCLK, 992 PUC_PORT_2S, 0x20, 0, 8, 993 }, 994 995 /* 996 * VScom (Titan?) PCI-800L. More modern variant of the 997 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 998 * two of them obviously implemented as macro cells in 999 * the ASIC. This causes the weird port access pattern 1000 * below, where two of the IO port ranges each access 1001 * one of the ASIC UARTs, and a block of IO addresses 1002 * access the external UARTs. 1003 */ 1004 { 0x14d2, 0x8080, 0xffff, 0, 1005 "Titan VScom PCI-800L", 1006 DEFAULT_RCLK * 8, 1007 PUC_PORT_8S, 0x14, -1, -1, 1008 .config_function = puc_config_titan 1009 }, 1010 1011 /* 1012 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 1013 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 1014 * device ID 3 and PCI device 1 device ID 4. 1015 */ 1016 { 0x14d2, 0xa003, 0xffff, 0, 1017 "Titan PCI-800H", 1018 DEFAULT_RCLK * 8, 1019 PUC_PORT_4S, 0x10, 0, 8, 1020 }, 1021 1022 { 0x14d2, 0xa004, 0xffff, 0, 1023 "Titan PCI-800H", 1024 DEFAULT_RCLK * 8, 1025 PUC_PORT_4S, 0x10, 0, 8, 1026 }, 1027 1028 { 0x14d2, 0xa005, 0xffff, 0, 1029 "Titan PCI-200H", 1030 DEFAULT_RCLK * 8, 1031 PUC_PORT_2S, 0x10, 0, 8, 1032 }, 1033 1034 { 0x14d2, 0xe020, 0xffff, 0, 1035 "Titan VScom PCI-200HV2", 1036 DEFAULT_RCLK * 8, 1037 PUC_PORT_2S, 0x10, 4, 0, 1038 }, 1039 1040 { 0x14d2, 0xa007, 0xffff, 0, 1041 "Titan VScom PCIex-800H", 1042 DEFAULT_RCLK * 8, 1043 PUC_PORT_4S, 0x10, 0, 8, 1044 }, 1045 1046 { 0x14d2, 0xa008, 0xffff, 0, 1047 "Titan VScom PCIex-800H", 1048 DEFAULT_RCLK * 8, 1049 PUC_PORT_4S, 0x10, 0, 8, 1050 }, 1051 1052 { 0x14db, 0x2130, 0xffff, 0, 1053 "Avlab Technology, PCI IO 2S", 1054 DEFAULT_RCLK, 1055 PUC_PORT_2S, 0x10, 4, 0, 1056 }, 1057 1058 { 0x14db, 0x2150, 0xffff, 0, 1059 "Avlab Low Profile PCI 4 Serial", 1060 DEFAULT_RCLK, 1061 PUC_PORT_4S, 0x10, 4, 0, 1062 }, 1063 1064 { 0x14db, 0x2152, 0xffff, 0, 1065 "Avlab Low Profile PCI 4 Serial", 1066 DEFAULT_RCLK, 1067 PUC_PORT_4S, 0x10, 4, 0, 1068 }, 1069 1070 { 0x1592, 0x0781, 0xffff, 0, 1071 "Syba Tech Ltd. PCI-4S2P-550-ECP", 1072 DEFAULT_RCLK, 1073 PUC_PORT_4S1P, 0x10, 0, -1, 1074 .config_function = puc_config_syba 1075 }, 1076 1077 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 1078 "Sunix SER5xxxx 2-port serial", 1079 DEFAULT_RCLK * 8, 1080 PUC_PORT_2S, 0x10, 0, 8, 1081 }, 1082 1083 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1084 "Sunix SER5xxxx 4-port serial", 1085 DEFAULT_RCLK * 8, 1086 PUC_PORT_4S, 0x10, 0, 8, 1087 }, 1088 1089 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1090 "Sunix SER5xxxx 8-port serial", 1091 DEFAULT_RCLK * 8, 1092 PUC_PORT_8S, -1, -1, -1, 1093 .config_function = puc_config_sunix 1094 }, 1095 1096 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1097 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1098 DEFAULT_RCLK * 8, 1099 PUC_PORT_1S1P, -1, -1, -1, 1100 .config_function = puc_config_sunix 1101 }, 1102 1103 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1104 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1105 DEFAULT_RCLK * 8, 1106 PUC_PORT_2S1P, -1, -1, -1, 1107 .config_function = puc_config_sunix 1108 }, 1109 1110 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1111 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1112 DEFAULT_RCLK * 8, 1113 PUC_PORT_4S1P, -1, -1, -1, 1114 .config_function = puc_config_sunix 1115 }, 1116 1117 { 0x5372, 0x6872, 0xffff, 0, 1118 "Feasso PCI FPP-02 2S1P", 1119 DEFAULT_RCLK, 1120 PUC_PORT_2S1P, 0x10, 4, 0, 1121 }, 1122 1123 { 0x5372, 0x6873, 0xffff, 0, 1124 "Sun 1040 PCI Quad Serial", 1125 DEFAULT_RCLK, 1126 PUC_PORT_4S, 0x10, 4, 0, 1127 }, 1128 1129 { 0x6666, 0x0001, 0xffff, 0, 1130 "Decision Computer Inc, PCCOM 4-port serial", 1131 DEFAULT_RCLK, 1132 PUC_PORT_4S, 0x1c, 0, 8, 1133 }, 1134 1135 { 0x6666, 0x0002, 0xffff, 0, 1136 "Decision Computer Inc, PCCOM 8-port serial", 1137 DEFAULT_RCLK, 1138 PUC_PORT_8S, 0x1c, 0, 8, 1139 }, 1140 1141 { 0x6666, 0x0004, 0xffff, 0, 1142 "PCCOM dual port RS232/422/485", 1143 DEFAULT_RCLK, 1144 PUC_PORT_2S, 0x1c, 0, 8, 1145 }, 1146 1147 { 0x9710, 0x9815, 0xffff, 0, 1148 "NetMos NM9815 Dual 1284 Printer port", 1149 0, 1150 PUC_PORT_2P, 0x10, 8, 0, 1151 }, 1152 1153 /* 1154 * This is more specific than the generic NM9835 entry, and is placed 1155 * here to _prevent_ puc(4) from claiming this single port card. 1156 * 1157 * uart(4) will claim this device. 1158 */ 1159 { 0x9710, 0x9835, 0x1000, 1, 1160 "NetMos NM9835 based 1-port serial", 1161 DEFAULT_RCLK, 1162 PUC_PORT_1S, 0x10, 4, 0, 1163 }, 1164 1165 { 0x9710, 0x9835, 0x1000, 2, 1166 "NetMos NM9835 based 2-port serial", 1167 DEFAULT_RCLK, 1168 PUC_PORT_2S, 0x10, 4, 0, 1169 }, 1170 1171 { 0x9710, 0x9835, 0xffff, 0, 1172 "NetMos NM9835 Dual UART and 1284 Printer port", 1173 DEFAULT_RCLK, 1174 PUC_PORT_2S1P, 0x10, 4, 0, 1175 }, 1176 1177 { 0x9710, 0x9845, 0x1000, 0x0006, 1178 "NetMos NM9845 6 Port UART", 1179 DEFAULT_RCLK, 1180 PUC_PORT_6S, 0x10, 4, 0, 1181 }, 1182 1183 { 0x9710, 0x9845, 0xffff, 0, 1184 "NetMos NM9845 Quad UART and 1284 Printer port", 1185 DEFAULT_RCLK, 1186 PUC_PORT_4S1P, 0x10, 4, 0, 1187 }, 1188 1189 { 0x9710, 0x9865, 0xa000, 0x3002, 1190 "NetMos NM9865 Dual UART", 1191 DEFAULT_RCLK, 1192 PUC_PORT_2S, 0x10, 4, 0, 1193 }, 1194 1195 { 0x9710, 0x9865, 0xa000, 0x3003, 1196 "NetMos NM9865 Triple UART", 1197 DEFAULT_RCLK, 1198 PUC_PORT_3S, 0x10, 4, 0, 1199 }, 1200 1201 { 0x9710, 0x9865, 0xa000, 0x3004, 1202 "NetMos NM9865 Quad UART", 1203 DEFAULT_RCLK, 1204 PUC_PORT_4S, 0x10, 4, 0, 1205 }, 1206 1207 { 0x9710, 0x9865, 0xa000, 0x3011, 1208 "NetMos NM9865 Single UART and 1284 Printer port", 1209 DEFAULT_RCLK, 1210 PUC_PORT_1S1P, 0x10, 4, 0, 1211 }, 1212 1213 { 0x9710, 0x9865, 0xa000, 0x3012, 1214 "NetMos NM9865 Dual UART and 1284 Printer port", 1215 DEFAULT_RCLK, 1216 PUC_PORT_2S1P, 0x10, 4, 0, 1217 }, 1218 1219 { 0x9710, 0x9865, 0xa000, 0x3020, 1220 "NetMos NM9865 Dual 1284 Printer port", 1221 DEFAULT_RCLK, 1222 PUC_PORT_2P, 0x10, 4, 0, 1223 }, 1224 1225 { 0xb00c, 0x021c, 0xffff, 0, 1226 "IC Book Labs Gunboat x4 Lite", 1227 DEFAULT_RCLK, 1228 PUC_PORT_4S, 0x10, 0, 8, 1229 .config_function = puc_config_icbook 1230 }, 1231 1232 { 0xb00c, 0x031c, 0xffff, 0, 1233 "IC Book Labs Gunboat x4 Pro", 1234 DEFAULT_RCLK, 1235 PUC_PORT_4S, 0x10, 0, 8, 1236 .config_function = puc_config_icbook 1237 }, 1238 1239 { 0xb00c, 0x041c, 0xffff, 0, 1240 "IC Book Labs Ironclad x8 Lite", 1241 DEFAULT_RCLK, 1242 PUC_PORT_8S, 0x10, 0, 8, 1243 .config_function = puc_config_icbook 1244 }, 1245 1246 { 0xb00c, 0x051c, 0xffff, 0, 1247 "IC Book Labs Ironclad x8 Pro", 1248 DEFAULT_RCLK, 1249 PUC_PORT_8S, 0x10, 0, 8, 1250 .config_function = puc_config_icbook 1251 }, 1252 1253 { 0xb00c, 0x081c, 0xffff, 0, 1254 "IC Book Labs Dreadnought x16 Pro", 1255 DEFAULT_RCLK * 8, 1256 PUC_PORT_16S, 0x10, 0, 8, 1257 .config_function = puc_config_icbook 1258 }, 1259 1260 { 0xb00c, 0x091c, 0xffff, 0, 1261 "IC Book Labs Dreadnought x16 Lite", 1262 DEFAULT_RCLK, 1263 PUC_PORT_16S, 0x10, 0, 8, 1264 .config_function = puc_config_icbook 1265 }, 1266 1267 { 0xb00c, 0x0a1c, 0xffff, 0, 1268 "IC Book Labs Gunboat x2 Low Profile", 1269 DEFAULT_RCLK, 1270 PUC_PORT_2S, 0x10, 0, 8, 1271 }, 1272 1273 { 0xb00c, 0x0b1c, 0xffff, 0, 1274 "IC Book Labs Gunboat x4 Low Profile", 1275 DEFAULT_RCLK, 1276 PUC_PORT_4S, 0x10, 0, 8, 1277 .config_function = puc_config_icbook 1278 }, 1279 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1280 }; 1281 1282 static int 1283 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1284 intptr_t *res __unused) 1285 { 1286 const struct puc_cfg *cfg; 1287 struct resource *cres; 1288 struct puc_bar *bar; 1289 device_t cdev, dev; 1290 bus_size_t off; 1291 int base, crtype, fixed, high, i, oxpcie; 1292 uint8_t acr, func, mask; 1293 1294 if (cmd != PUC_CFG_SETUP) 1295 return (ENXIO); 1296 1297 base = fixed = oxpcie = 0; 1298 crtype = SYS_RES_IOPORT; 1299 acr = mask = 0x0; 1300 func = high = 1; 1301 off = 0x60; 1302 1303 cfg = sc->sc_cfg; 1304 switch (cfg->subvendor) { 1305 case 0x13fe: 1306 switch (cfg->device) { 1307 case 0xa102: 1308 high = 0; 1309 break; 1310 default: 1311 break; 1312 } 1313 default: 1314 break; 1315 } 1316 if (fixed == 1) 1317 goto setup; 1318 1319 dev = sc->sc_dev; 1320 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1321 pci_get_slot(dev), func); 1322 if (cdev == NULL) { 1323 device_printf(dev, "could not find config function\n"); 1324 return (ENXIO); 1325 } 1326 1327 i = PCIR_BAR(0); 1328 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE); 1329 if (cres == NULL) { 1330 device_printf(dev, "could not allocate config resource\n"); 1331 return (ENXIO); 1332 } 1333 1334 if (oxpcie == 0) { 1335 mask = bus_read_1(cres, off); 1336 if (pci_get_function(dev) == 1) 1337 base = 4; 1338 } 1339 1340 setup: 1341 for (i = 0; i < sc->sc_nports; ++i) { 1342 device_printf(dev, "port %d: ", i); 1343 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); 1344 if (bar == NULL) { 1345 printf("could not get BAR\n"); 1346 continue; 1347 } 1348 1349 if (fixed == 0) { 1350 if ((mask & (1 << (base + i))) == 0) { 1351 acr = 0; 1352 printf("RS-232\n"); 1353 } else { 1354 acr = (high == 1 ? 0x18 : 0x10); 1355 printf("RS-422/RS-485, active-%s auto-DTR\n", 1356 high == 1 ? "high" : "low"); 1357 } 1358 } 1359 1360 bus_write_1(bar->b_res, REG_SPR, REG_ACR); 1361 bus_write_1(bar->b_res, REG_ICR, acr); 1362 } 1363 1364 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres); 1365 return (0); 1366 } 1367 1368 static int 1369 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port, 1370 intptr_t *res) 1371 { 1372 1373 switch (cmd) { 1374 case PUC_CFG_GET_OFS: 1375 *res = 8 * (port & 1); 1376 return (0); 1377 case PUC_CFG_GET_RID: 1378 *res = 0x14 + (port >> 1) * 4; 1379 return (0); 1380 default: 1381 break; 1382 } 1383 return (ENXIO); 1384 } 1385 1386 static int 1387 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1388 intptr_t *res) 1389 { 1390 const struct puc_cfg *cfg = sc->sc_cfg; 1391 1392 if (cmd == PUC_CFG_GET_OFS) { 1393 if (cfg->subdevice == 0x1282) /* Everest SP */ 1394 port <<= 1; 1395 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1396 port = (port == 3) ? 4 : port; 1397 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1398 return (0); 1399 } 1400 return (ENXIO); 1401 } 1402 1403 static int 1404 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1405 int port, intptr_t *res) 1406 { 1407 1408 if (cmd == PUC_CFG_GET_OFS) { 1409 *res = port * 0x200; 1410 return (0); 1411 } 1412 return (ENXIO); 1413 } 1414 1415 static int 1416 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1417 int port, intptr_t *res) 1418 { 1419 1420 if (cmd == PUC_CFG_GET_OFS) { 1421 *res = port * 0x400; 1422 return (0); 1423 } 1424 return (ENXIO); 1425 } 1426 1427 static int 1428 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1429 int port __unused, intptr_t *res) 1430 { 1431 1432 if (cmd == PUC_CFG_GET_ILR) { 1433 *res = PUC_ILR_DIGI; 1434 return (0); 1435 } 1436 return (ENXIO); 1437 } 1438 1439 static int 1440 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1441 intptr_t *res) 1442 { 1443 const struct puc_cfg *cfg = sc->sc_cfg; 1444 1445 if (cmd == PUC_CFG_GET_OFS) { 1446 if (port == 3 && (cfg->device == 0x1045 || 1447 cfg->device == 0x1144)) 1448 port = 7; 1449 *res = port * 0x200; 1450 1451 return 0; 1452 } 1453 return (ENXIO); 1454 } 1455 1456 static int 1457 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1458 int port __unused, intptr_t *res) 1459 { 1460 const struct puc_cfg *cfg = sc->sc_cfg; 1461 struct puc_bar *bar; 1462 uint8_t v0, v1; 1463 1464 switch (cmd) { 1465 case PUC_CFG_SETUP: 1466 /* 1467 * Check if the scratchpad register is enabled or if the 1468 * interrupt status and options registers are active. 1469 */ 1470 bar = puc_get_bar(sc, cfg->rid); 1471 if (bar == NULL) 1472 return (ENXIO); 1473 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); 1474 bus_write_1(bar->b_res, REG_SPR, 0); 1475 v0 = bus_read_1(bar->b_res, REG_SPR); 1476 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); 1477 v1 = bus_read_1(bar->b_res, REG_SPR); 1478 bus_write_1(bar->b_res, REG_LCR, 0); 1479 sc->sc_cfg_data = (v0 << 8) | v1; 1480 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1481 /* 1482 * The SPR register echoed the two values written 1483 * by us. This means that the SPAD jumper is set. 1484 */ 1485 device_printf(sc->sc_dev, "warning: extra features " 1486 "not usable -- SPAD compatibility enabled\n"); 1487 return (0); 1488 } 1489 if (v0 != 0) { 1490 /* 1491 * The first value doesn't match. This can only mean 1492 * that the SPAD jumper is not set and that a non- 1493 * standard fixed clock multiplier jumper is set. 1494 */ 1495 if (bootverbose) 1496 device_printf(sc->sc_dev, "fixed clock rate " 1497 "multiplier of %d\n", 1 << v0); 1498 if (v0 < -cfg->clock) 1499 device_printf(sc->sc_dev, "warning: " 1500 "suboptimal fixed clock rate multiplier " 1501 "setting\n"); 1502 return (0); 1503 } 1504 /* 1505 * The first value matched, but the second didn't. We know 1506 * that the SPAD jumper is not set. We also know that the 1507 * clock rate multiplier is software controlled *and* that 1508 * we just programmed it to the maximum allowed. 1509 */ 1510 if (bootverbose) 1511 device_printf(sc->sc_dev, "clock rate multiplier of " 1512 "%d selected\n", 1 << -cfg->clock); 1513 return (0); 1514 case PUC_CFG_GET_CLOCK: 1515 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1516 v1 = sc->sc_cfg_data & 0xff; 1517 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1518 /* 1519 * XXX With the SPAD jumper applied, there's no 1520 * easy way of knowing if there's also a clock 1521 * rate multiplier jumper installed. Let's hope 1522 * not ... 1523 */ 1524 *res = DEFAULT_RCLK; 1525 } else if (v0 == 0) { 1526 /* 1527 * No clock rate multiplier jumper installed, 1528 * so we programmed the board with the maximum 1529 * multiplier allowed as given to us in the 1530 * clock field of the config record (negated). 1531 */ 1532 *res = DEFAULT_RCLK << -cfg->clock; 1533 } else 1534 *res = DEFAULT_RCLK << v0; 1535 return (0); 1536 case PUC_CFG_GET_ILR: 1537 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1538 v1 = sc->sc_cfg_data & 0xff; 1539 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? 1540 PUC_ILR_NONE : PUC_ILR_QUATECH; 1541 return (0); 1542 default: 1543 break; 1544 } 1545 return (ENXIO); 1546 } 1547 1548 static int 1549 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1550 intptr_t *res) 1551 { 1552 static int base[] = { 0x251, 0x3f0, 0 }; 1553 const struct puc_cfg *cfg = sc->sc_cfg; 1554 struct puc_bar *bar; 1555 int efir, idx, ofs; 1556 uint8_t v; 1557 1558 switch (cmd) { 1559 case PUC_CFG_SETUP: 1560 bar = puc_get_bar(sc, cfg->rid); 1561 if (bar == NULL) 1562 return (ENXIO); 1563 1564 /* configure both W83877TFs */ 1565 bus_write_1(bar->b_res, 0x250, 0x89); 1566 bus_write_1(bar->b_res, 0x3f0, 0x87); 1567 bus_write_1(bar->b_res, 0x3f0, 0x87); 1568 idx = 0; 1569 while (base[idx] != 0) { 1570 efir = base[idx]; 1571 bus_write_1(bar->b_res, efir, 0x09); 1572 v = bus_read_1(bar->b_res, efir + 1); 1573 if ((v & 0x0f) != 0x0c) 1574 return (ENXIO); 1575 bus_write_1(bar->b_res, efir, 0x16); 1576 v = bus_read_1(bar->b_res, efir + 1); 1577 bus_write_1(bar->b_res, efir, 0x16); 1578 bus_write_1(bar->b_res, efir + 1, v | 0x04); 1579 bus_write_1(bar->b_res, efir, 0x16); 1580 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1581 ofs = base[idx] & 0x300; 1582 bus_write_1(bar->b_res, efir, 0x23); 1583 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1584 bus_write_1(bar->b_res, efir, 0x24); 1585 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1586 bus_write_1(bar->b_res, efir, 0x25); 1587 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1588 bus_write_1(bar->b_res, efir, 0x17); 1589 bus_write_1(bar->b_res, efir + 1, 0x03); 1590 bus_write_1(bar->b_res, efir, 0x28); 1591 bus_write_1(bar->b_res, efir + 1, 0x43); 1592 idx++; 1593 } 1594 bus_write_1(bar->b_res, 0x250, 0xaa); 1595 bus_write_1(bar->b_res, 0x3f0, 0xaa); 1596 return (0); 1597 case PUC_CFG_GET_OFS: 1598 switch (port) { 1599 case 0: 1600 *res = 0x2f8; 1601 return (0); 1602 case 1: 1603 *res = 0x2e8; 1604 return (0); 1605 case 2: 1606 *res = 0x3f8; 1607 return (0); 1608 case 3: 1609 *res = 0x3e8; 1610 return (0); 1611 case 4: 1612 *res = 0x278; 1613 return (0); 1614 } 1615 break; 1616 default: 1617 break; 1618 } 1619 return (ENXIO); 1620 } 1621 1622 static int 1623 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1624 intptr_t *res) 1625 { 1626 const struct puc_cfg *cfg = sc->sc_cfg; 1627 1628 switch (cmd) { 1629 case PUC_CFG_GET_OFS: 1630 if (cfg->ports == PUC_PORT_8S) { 1631 *res = (port > 4) ? 8 * (port - 4) : 0; 1632 return (0); 1633 } 1634 break; 1635 case PUC_CFG_GET_RID: 1636 if (cfg->ports == PUC_PORT_8S) { 1637 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1638 return (0); 1639 } 1640 if (cfg->ports == PUC_PORT_2S1P) { 1641 switch (port) { 1642 case 0: *res = 0x10; return (0); 1643 case 1: *res = 0x14; return (0); 1644 case 2: *res = 0x1c; return (0); 1645 } 1646 } 1647 break; 1648 default: 1649 break; 1650 } 1651 return (ENXIO); 1652 } 1653 1654 static int 1655 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1656 intptr_t *res) 1657 { 1658 static const uint16_t dual[] = { 1659 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1660 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1661 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1662 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1663 0xD079, 0 1664 }; 1665 static const uint16_t quad[] = { 1666 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1667 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1668 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1669 0xB157, 0 1670 }; 1671 static const uint16_t octa[] = { 1672 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1673 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1674 }; 1675 static const struct { 1676 int ports; 1677 const uint16_t *ids; 1678 } subdevs[] = { 1679 { 2, dual }, 1680 { 4, quad }, 1681 { 8, octa }, 1682 { 0, NULL } 1683 }; 1684 static char desc[64]; 1685 int dev, id; 1686 uint16_t subdev; 1687 1688 switch (cmd) { 1689 case PUC_CFG_GET_CLOCK: 1690 if (port < 2) 1691 *res = DEFAULT_RCLK * 8; 1692 else 1693 *res = DEFAULT_RCLK; 1694 return (0); 1695 case PUC_CFG_GET_DESC: 1696 snprintf(desc, sizeof(desc), 1697 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1698 *res = (intptr_t)desc; 1699 return (0); 1700 case PUC_CFG_GET_NPORTS: 1701 subdev = pci_get_subdevice(sc->sc_dev); 1702 dev = 0; 1703 while (subdevs[dev].ports != 0) { 1704 id = 0; 1705 while (subdevs[dev].ids[id] != 0) { 1706 if (subdev == subdevs[dev].ids[id]) { 1707 sc->sc_cfg_data = subdevs[dev].ports; 1708 *res = sc->sc_cfg_data; 1709 return (0); 1710 } 1711 id++; 1712 } 1713 dev++; 1714 } 1715 return (ENXIO); 1716 case PUC_CFG_GET_OFS: 1717 *res = (port == 1 || port == 3) ? 8 : 0; 1718 return (0); 1719 case PUC_CFG_GET_RID: 1720 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1721 return (0); 1722 case PUC_CFG_GET_TYPE: 1723 *res = PUC_TYPE_SERIAL; 1724 return (0); 1725 default: 1726 break; 1727 } 1728 return (ENXIO); 1729 } 1730 1731 static int 1732 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1733 int port __unused, intptr_t *res) 1734 { 1735 1736 switch (cmd) { 1737 case PUC_CFG_GET_CLOCK: 1738 /* 1739 * OXu16PCI954 use a 14.7456 MHz clock by default while 1740 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1741 */ 1742 if (pci_get_revid(sc->sc_dev) == 1) 1743 *res = DEFAULT_RCLK * 8; 1744 else 1745 *res = DEFAULT_RCLK; 1746 return (0); 1747 default: 1748 break; 1749 } 1750 return (ENXIO); 1751 } 1752 1753 static int 1754 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1755 intptr_t *res) 1756 { 1757 const struct puc_cfg *cfg = sc->sc_cfg; 1758 int idx; 1759 struct puc_bar *bar; 1760 uint8_t value; 1761 1762 switch (cmd) { 1763 case PUC_CFG_SETUP: 1764 device_printf(sc->sc_dev, "%d UARTs detected\n", 1765 sc->sc_nports); 1766 1767 /* Set UARTs to enhanced mode */ 1768 bar = puc_get_bar(sc, cfg->rid); 1769 if (bar == NULL) 1770 return (ENXIO); 1771 for (idx = 0; idx < sc->sc_nports; idx++) { 1772 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1773 0x92); 1774 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1775 value | 0x10); 1776 } 1777 return (0); 1778 case PUC_CFG_GET_LEN: 1779 *res = 0x200; 1780 return (0); 1781 case PUC_CFG_GET_NPORTS: 1782 /* 1783 * Check if we are being called from puc_bfe_attach() 1784 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1785 * puc_get_bar(), so we return a value of 16. This has 1786 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, 1787 * sc->sc_cfg_data will not contain the true number of 1788 * ports in PUC_CFG_GET_DESC, but we are not implementing 1789 * that call for this device family anyway. 1790 * 1791 * The check is for initialization of sc->sc_bar[idx], 1792 * which is only done in puc_bfe_attach(). 1793 */ 1794 idx = 0; 1795 do { 1796 if (sc->sc_bar[idx++].b_rid != -1) { 1797 sc->sc_cfg_data = 16; 1798 *res = sc->sc_cfg_data; 1799 return (0); 1800 } 1801 } while (idx < PUC_PCI_BARS); 1802 1803 bar = puc_get_bar(sc, cfg->rid); 1804 if (bar == NULL) 1805 return (ENXIO); 1806 1807 value = bus_read_1(bar->b_res, 0x04); 1808 if (value == 0) 1809 return (ENXIO); 1810 1811 sc->sc_cfg_data = value; 1812 *res = sc->sc_cfg_data; 1813 return (0); 1814 case PUC_CFG_GET_OFS: 1815 *res = 0x1000 + (port << 9); 1816 return (0); 1817 case PUC_CFG_GET_TYPE: 1818 *res = PUC_TYPE_SERIAL; 1819 return (0); 1820 default: 1821 break; 1822 } 1823 return (ENXIO); 1824 } 1825 1826 static int 1827 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1828 intptr_t *res) 1829 { 1830 int error; 1831 1832 switch (cmd) { 1833 case PUC_CFG_GET_OFS: 1834 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1835 if (error != 0) 1836 return (error); 1837 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1838 return (0); 1839 case PUC_CFG_GET_RID: 1840 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1841 if (error != 0) 1842 return (error); 1843 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1844 return (0); 1845 default: 1846 break; 1847 } 1848 return (ENXIO); 1849 } 1850 1851 static int 1852 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1853 int port, intptr_t *res) 1854 { 1855 1856 switch (cmd) { 1857 case PUC_CFG_GET_OFS: 1858 *res = (port < 3) ? 0 : (port - 2) << 3; 1859 return (0); 1860 case PUC_CFG_GET_RID: 1861 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1862 return (0); 1863 default: 1864 break; 1865 } 1866 return (ENXIO); 1867 } 1868