xref: /freebsd/sys/dev/puc/pucdata.c (revision 1714dcab20dae184e4b2fc01857f26912f3ee792)
1 /*-
2  * Copyright (c) 2006 Marcel Moolenaar
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 /*
31  * PCI "universal" communications card driver configuration data (used to
32  * match/attach the cards).
33  */
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/bus.h>
39 #include <sys/sysctl.h>
40 
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 
45 #include <dev/pci/pcivar.h>
46 
47 #include <dev/puc/puc_bus.h>
48 #include <dev/puc/puc_cfg.h>
49 #include <dev/puc/puc_bfe.h>
50 
51 static puc_config_f puc_config_amc;
52 static puc_config_f puc_config_diva;
53 static puc_config_f puc_config_exar;
54 static puc_config_f puc_config_exar_pcie;
55 static puc_config_f puc_config_icbook;
56 static puc_config_f puc_config_moxa;
57 static puc_config_f puc_config_oxford_pci954;
58 static puc_config_f puc_config_oxford_pcie;
59 static puc_config_f puc_config_quatech;
60 static puc_config_f puc_config_syba;
61 static puc_config_f puc_config_siig;
62 static puc_config_f puc_config_sunix;
63 static puc_config_f puc_config_timedia;
64 static puc_config_f puc_config_titan;
65 
66 const struct puc_cfg puc_pci_devices[] = {
67 
68 	{   0x0009, 0x7168, 0xffff, 0,
69 	    "Sunix SUN1889",
70 	    DEFAULT_RCLK * 8,
71 	    PUC_PORT_2S, 0x10, 0, 8,
72 	},
73 
74 	{   0x103c, 0x1048, 0x103c, 0x1049,
75 	    "HP Diva Serial [GSP] Multiport UART - Tosca Console",
76 	    DEFAULT_RCLK,
77 	    PUC_PORT_3S, 0x10, 0, -1,
78 	    .config_function = puc_config_diva
79 	},
80 
81 	{   0x103c, 0x1048, 0x103c, 0x104a,
82 	    "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
83 	    DEFAULT_RCLK,
84 	    PUC_PORT_2S, 0x10, 0, -1,
85 	    .config_function = puc_config_diva
86 	},
87 
88 	{   0x103c, 0x1048, 0x103c, 0x104b,
89 	    "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
90 	    DEFAULT_RCLK,
91 	    PUC_PORT_4S, 0x10, 0, -1,
92 	    .config_function = puc_config_diva
93 	},
94 
95 	{   0x103c, 0x1048, 0x103c, 0x1223,
96 	    "HP Diva Serial [GSP] Multiport UART - Superdome Console",
97 	    DEFAULT_RCLK,
98 	    PUC_PORT_3S, 0x10, 0, -1,
99 	    .config_function = puc_config_diva
100 	},
101 
102 	{   0x103c, 0x1048, 0x103c, 0x1226,
103 	    "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
104 	    DEFAULT_RCLK,
105 	    PUC_PORT_3S, 0x10, 0, -1,
106 	    .config_function = puc_config_diva
107 	},
108 
109 	{   0x103c, 0x1048, 0x103c, 0x1282,
110 	    "HP Diva Serial [GSP] Multiport UART - Everest SP2",
111 	    DEFAULT_RCLK,
112 	    PUC_PORT_3S, 0x10, 0, -1,
113 	    .config_function = puc_config_diva
114 	},
115 
116 	{   0x10b5, 0x1076, 0x10b5, 0x1076,
117 	    "VScom PCI-800",
118 	    DEFAULT_RCLK * 8,
119 	    PUC_PORT_8S, 0x18, 0, 8,
120 	},
121 
122 	{   0x10b5, 0x1077, 0x10b5, 0x1077,
123 	    "VScom PCI-400",
124 	    DEFAULT_RCLK * 8,
125 	    PUC_PORT_4S, 0x18, 0, 8,
126 	},
127 
128 	{   0x10b5, 0x1103, 0x10b5, 0x1103,
129 	    "VScom PCI-200",
130 	    DEFAULT_RCLK * 8,
131 	    PUC_PORT_2S, 0x18, 4, 0,
132 	},
133 
134 	/*
135 	 * Boca Research Turbo Serial 658 (8 serial port) card.
136 	 * Appears to be the same as Chase Research PLC PCI-FAST8
137 	 * and Perle PCI-FAST8 Multi-Port serial cards.
138 	 */
139 	{   0x10b5, 0x9050, 0x12e0, 0x0021,
140 	    "Boca Research Turbo Serial 658",
141 	    DEFAULT_RCLK * 4,
142 	    PUC_PORT_8S, 0x18, 0, 8,
143 	},
144 
145 	{   0x10b5, 0x9050, 0x12e0, 0x0031,
146 	    "Boca Research Turbo Serial 654",
147 	    DEFAULT_RCLK * 4,
148 	    PUC_PORT_4S, 0x18, 0, 8,
149 	},
150 
151 	/*
152 	 * Dolphin Peripherals 4035 (dual serial port) card.  PLX 9050, with
153 	 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
154 	 * into the subsystem fields, and claims that it's a
155 	 * network/misc (0x02/0x80) device.
156 	 */
157 	{   0x10b5, 0x9050, 0xd84d, 0x6808,
158 	    "Dolphin Peripherals 4035",
159 	    DEFAULT_RCLK,
160 	    PUC_PORT_2S, 0x18, 4, 0,
161 	},
162 
163 	/*
164 	 * Dolphin Peripherals 4014 (dual parallel port) card.  PLX 9050, with
165 	 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
166 	 * into the subsystem fields, and claims that it's a
167 	 * network/misc (0x02/0x80) device.
168 	 */
169 	{   0x10b5, 0x9050, 0xd84d, 0x6810,
170 	    "Dolphin Peripherals 4014",
171 	    0,
172 	    PUC_PORT_2P, 0x20, 4, 0,
173 	},
174 
175 	{   0x10e8, 0x818e, 0xffff, 0,
176 	    "Applied Micro Circuits 8 Port UART",
177 	    DEFAULT_RCLK,
178 	    PUC_PORT_8S, 0x14, -1, -1,
179 	    .config_function = puc_config_amc
180 	},
181 
182 	{   0x11fe, 0x8010, 0xffff, 0,
183 	    "Comtrol RocketPort 550/8 RJ11 part A",
184 	    DEFAULT_RCLK * 4,
185 	    PUC_PORT_4S, 0x10, 0, 8,
186 	},
187 
188 	{   0x11fe, 0x8011, 0xffff, 0,
189 	    "Comtrol RocketPort 550/8 RJ11 part B",
190 	    DEFAULT_RCLK * 4,
191 	    PUC_PORT_4S, 0x10, 0, 8,
192 	},
193 
194 	{   0x11fe, 0x8012, 0xffff, 0,
195 	    "Comtrol RocketPort 550/8 Octa part A",
196 	    DEFAULT_RCLK * 4,
197 	    PUC_PORT_4S, 0x10, 0, 8,
198 	},
199 
200 	{   0x11fe, 0x8013, 0xffff, 0,
201 	    "Comtrol RocketPort 550/8 Octa part B",
202 	    DEFAULT_RCLK * 4,
203 	    PUC_PORT_4S, 0x10, 0, 8,
204 	},
205 
206 	{   0x11fe, 0x8014, 0xffff, 0,
207 	    "Comtrol RocketPort 550/4 RJ45",
208 	    DEFAULT_RCLK * 4,
209 	    PUC_PORT_4S, 0x10, 0, 8,
210 	},
211 
212 	{   0x11fe, 0x8015, 0xffff, 0,
213 	    "Comtrol RocketPort 550/Quad",
214 	    DEFAULT_RCLK * 4,
215 	    PUC_PORT_4S, 0x10, 0, 8,
216 	},
217 
218 	{   0x11fe, 0x8016, 0xffff, 0,
219 	    "Comtrol RocketPort 550/16 part A",
220 	    DEFAULT_RCLK * 4,
221 	    PUC_PORT_4S, 0x10, 0, 8,
222 	},
223 
224 	{   0x11fe, 0x8017, 0xffff, 0,
225 	    "Comtrol RocketPort 550/16 part B",
226 	    DEFAULT_RCLK * 4,
227 	    PUC_PORT_12S, 0x10, 0, 8,
228 	},
229 
230 	{   0x11fe, 0x8018, 0xffff, 0,
231 	    "Comtrol RocketPort 550/8 part A",
232 	    DEFAULT_RCLK * 4,
233 	    PUC_PORT_4S, 0x10, 0, 8,
234 	},
235 
236 	{   0x11fe, 0x8019, 0xffff, 0,
237 	    "Comtrol RocketPort 550/8 part B",
238 	    DEFAULT_RCLK * 4,
239 	    PUC_PORT_4S, 0x10, 0, 8,
240 	},
241 
242 	/*
243 	 * IBM SurePOS 300 Series (481033H) serial ports
244 	 * Details can be found on the IBM RSS websites
245 	 */
246 
247 	{   0x1014, 0x0297, 0xffff, 0,
248 	    "IBM SurePOS 300 Series (481033H) serial ports",
249 	    DEFAULT_RCLK,
250 	    PUC_PORT_4S, 0x10, 4, 0
251 	},
252 
253 	/*
254 	 * SIIG Boards.
255 	 *
256 	 * SIIG provides documentation for their boards at:
257 	 * <URL:http://www.siig.com/downloads.asp>
258 	 */
259 
260 	{   0x131f, 0x1010, 0xffff, 0,
261 	    "SIIG Cyber I/O PCI 16C550 (10x family)",
262 	    DEFAULT_RCLK,
263 	    PUC_PORT_1S1P, 0x18, 4, 0,
264 	},
265 
266 	{   0x131f, 0x1011, 0xffff, 0,
267 	    "SIIG Cyber I/O PCI 16C650 (10x family)",
268 	    DEFAULT_RCLK,
269 	    PUC_PORT_1S1P, 0x18, 4, 0,
270 	},
271 
272 	{   0x131f, 0x1012, 0xffff, 0,
273 	    "SIIG Cyber I/O PCI 16C850 (10x family)",
274 	    DEFAULT_RCLK,
275 	    PUC_PORT_1S1P, 0x18, 4, 0,
276 	},
277 
278 	{   0x131f, 0x1021, 0xffff, 0,
279 	    "SIIG Cyber Parallel Dual PCI (10x family)",
280 	    0,
281 	    PUC_PORT_2P, 0x18, 8, 0,
282 	},
283 
284 	{   0x131f, 0x1030, 0xffff, 0,
285 	    "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
286 	    DEFAULT_RCLK,
287 	    PUC_PORT_2S, 0x18, 4, 0,
288 	},
289 
290 	{   0x131f, 0x1031, 0xffff, 0,
291 	    "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
292 	    DEFAULT_RCLK,
293 	    PUC_PORT_2S, 0x18, 4, 0,
294 	},
295 
296 	{   0x131f, 0x1032, 0xffff, 0,
297 	    "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
298 	    DEFAULT_RCLK,
299 	    PUC_PORT_2S, 0x18, 4, 0,
300 	},
301 
302 	{   0x131f, 0x1034, 0xffff, 0,	/* XXX really? */
303 	    "SIIG Cyber 2S1P PCI 16C550 (10x family)",
304 	    DEFAULT_RCLK,
305 	    PUC_PORT_2S1P, 0x18, 4, 0,
306 	},
307 
308 	{   0x131f, 0x1035, 0xffff, 0,	/* XXX really? */
309 	    "SIIG Cyber 2S1P PCI 16C650 (10x family)",
310 	    DEFAULT_RCLK,
311 	    PUC_PORT_2S1P, 0x18, 4, 0,
312 	},
313 
314 	{   0x131f, 0x1036, 0xffff, 0,	/* XXX really? */
315 	    "SIIG Cyber 2S1P PCI 16C850 (10x family)",
316 	    DEFAULT_RCLK,
317 	    PUC_PORT_2S1P, 0x18, 4, 0,
318 	},
319 
320 	{   0x131f, 0x1050, 0xffff, 0,
321 	    "SIIG Cyber 4S PCI 16C550 (10x family)",
322 	    DEFAULT_RCLK,
323 	    PUC_PORT_4S, 0x18, 4, 0,
324 	},
325 
326 	{   0x131f, 0x1051, 0xffff, 0,
327 	    "SIIG Cyber 4S PCI 16C650 (10x family)",
328 	    DEFAULT_RCLK,
329 	    PUC_PORT_4S, 0x18, 4, 0,
330 	},
331 
332 	{   0x131f, 0x1052, 0xffff, 0,
333 	    "SIIG Cyber 4S PCI 16C850 (10x family)",
334 	    DEFAULT_RCLK,
335 	    PUC_PORT_4S, 0x18, 4, 0,
336 	},
337 
338 	{   0x131f, 0x2010, 0xffff, 0,
339 	    "SIIG Cyber I/O PCI 16C550 (20x family)",
340 	    DEFAULT_RCLK,
341 	    PUC_PORT_1S1P, 0x10, 4, 0,
342 	},
343 
344 	{   0x131f, 0x2011, 0xffff, 0,
345 	    "SIIG Cyber I/O PCI 16C650 (20x family)",
346 	    DEFAULT_RCLK,
347 	    PUC_PORT_1S1P, 0x10, 4, 0,
348 	},
349 
350 	{   0x131f, 0x2012, 0xffff, 0,
351 	    "SIIG Cyber I/O PCI 16C850 (20x family)",
352 	    DEFAULT_RCLK,
353 	    PUC_PORT_1S1P, 0x10, 4, 0,
354 	},
355 
356 	{   0x131f, 0x2021, 0xffff, 0,
357 	    "SIIG Cyber Parallel Dual PCI (20x family)",
358 	    0,
359 	    PUC_PORT_2P, 0x10, 8, 0,
360 	},
361 
362 	{   0x131f, 0x2030, 0xffff, 0,
363 	    "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
364 	    DEFAULT_RCLK,
365 	    PUC_PORT_2S, 0x10, 4, 0,
366 	},
367 
368 	{   0x131f, 0x2031, 0xffff, 0,
369 	    "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
370 	    DEFAULT_RCLK,
371 	    PUC_PORT_2S, 0x10, 4, 0,
372 	},
373 
374 	{   0x131f, 0x2032, 0xffff, 0,
375 	    "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
376 	    DEFAULT_RCLK,
377 	    PUC_PORT_2S, 0x10, 4, 0,
378 	},
379 
380 	{   0x131f, 0x2040, 0xffff, 0,
381 	    "SIIG Cyber 2P1S PCI 16C550 (20x family)",
382 	    DEFAULT_RCLK,
383 	    PUC_PORT_1S2P, 0x10, -1, 0,
384 	    .config_function = puc_config_siig
385 	},
386 
387 	{   0x131f, 0x2041, 0xffff, 0,
388 	    "SIIG Cyber 2P1S PCI 16C650 (20x family)",
389 	    DEFAULT_RCLK,
390 	    PUC_PORT_1S2P, 0x10, -1, 0,
391 	    .config_function = puc_config_siig
392 	},
393 
394 	{   0x131f, 0x2042, 0xffff, 0,
395 	    "SIIG Cyber 2P1S PCI 16C850 (20x family)",
396 	    DEFAULT_RCLK,
397 	    PUC_PORT_1S2P, 0x10, -1, 0,
398 	    .config_function = puc_config_siig
399 	},
400 
401 	{   0x131f, 0x2050, 0xffff, 0,
402 	    "SIIG Cyber 4S PCI 16C550 (20x family)",
403 	    DEFAULT_RCLK,
404 	    PUC_PORT_4S, 0x10, 4, 0,
405 	},
406 
407 	{   0x131f, 0x2051, 0xffff, 0,
408 	    "SIIG Cyber 4S PCI 16C650 (20x family)",
409 	    DEFAULT_RCLK,
410 	    PUC_PORT_4S, 0x10, 4, 0,
411 	},
412 
413 	{   0x131f, 0x2052, 0xffff, 0,
414 	    "SIIG Cyber 4S PCI 16C850 (20x family)",
415 	    DEFAULT_RCLK,
416 	    PUC_PORT_4S, 0x10, 4, 0,
417 	},
418 
419 	{   0x131f, 0x2060, 0xffff, 0,
420 	    "SIIG Cyber 2S1P PCI 16C550 (20x family)",
421 	    DEFAULT_RCLK,
422 	    PUC_PORT_2S1P, 0x10, 4, 0,
423 	},
424 
425 	{   0x131f, 0x2061, 0xffff, 0,
426 	    "SIIG Cyber 2S1P PCI 16C650 (20x family)",
427 	    DEFAULT_RCLK,
428 	    PUC_PORT_2S1P, 0x10, 4, 0,
429 	},
430 
431 	{   0x131f, 0x2062, 0xffff, 0,
432 	    "SIIG Cyber 2S1P PCI 16C850 (20x family)",
433 	    DEFAULT_RCLK,
434 	    PUC_PORT_2S1P, 0x10, 4, 0,
435 	},
436 
437 	{   0x131f, 0x2081, 0xffff, 0,
438 	    "SIIG PS8000 8S PCI 16C650 (20x family)",
439 	    DEFAULT_RCLK,
440 	    PUC_PORT_8S, 0x10, -1, -1,
441 	    .config_function = puc_config_siig
442 	},
443 
444 	{   0x135c, 0x0010, 0xffff, 0,
445 	    "Quatech QSC-100",
446 	    -3,	/* max 8x clock rate */
447 	    PUC_PORT_4S, 0x14, 0, 8,
448 	    .config_function = puc_config_quatech
449 	},
450 
451 	{   0x135c, 0x0020, 0xffff, 0,
452 	    "Quatech DSC-100",
453 	    -1, /* max 2x clock rate */
454 	    PUC_PORT_2S, 0x14, 0, 8,
455 	    .config_function = puc_config_quatech
456 	},
457 
458 	{   0x135c, 0x0030, 0xffff, 0,
459 	    "Quatech DSC-200/300",
460 	    -1, /* max 2x clock rate */
461 	    PUC_PORT_2S, 0x14, 0, 8,
462 	    .config_function = puc_config_quatech
463 	},
464 
465 	{   0x135c, 0x0040, 0xffff, 0,
466 	    "Quatech QSC-200/300",
467 	    -3, /* max 8x clock rate */
468 	    PUC_PORT_4S, 0x14, 0, 8,
469 	    .config_function = puc_config_quatech
470 	},
471 
472 	{   0x135c, 0x0050, 0xffff, 0,
473 	    "Quatech ESC-100D",
474 	    -3, /* max 8x clock rate */
475 	    PUC_PORT_8S, 0x14, 0, 8,
476 	    .config_function = puc_config_quatech
477 	},
478 
479 	{   0x135c, 0x0060, 0xffff, 0,
480 	    "Quatech ESC-100M",
481 	    -3, /* max 8x clock rate */
482 	    PUC_PORT_8S, 0x14, 0, 8,
483 	    .config_function = puc_config_quatech
484 	},
485 
486 	{   0x135c, 0x0170, 0xffff, 0,
487 	    "Quatech QSCLP-100",
488 	    -1, /* max 2x clock rate */
489 	    PUC_PORT_4S, 0x18, 0, 8,
490 	    .config_function = puc_config_quatech
491 	},
492 
493 	{   0x135c, 0x0180, 0xffff, 0,
494 	    "Quatech DSCLP-100",
495 	    -1, /* max 3x clock rate */
496 	    PUC_PORT_2S, 0x18, 0, 8,
497 	    .config_function = puc_config_quatech
498 	},
499 
500 	{   0x135c, 0x01b0, 0xffff, 0,
501 	    "Quatech DSCLP-200/300",
502 	    -1, /* max 2x clock rate */
503 	    PUC_PORT_2S, 0x18, 0, 8,
504 	    .config_function = puc_config_quatech
505 	},
506 
507 	{   0x135c, 0x01e0, 0xffff, 0,
508 	    "Quatech ESCLP-100",
509 	    -3, /* max 8x clock rate */
510 	    PUC_PORT_8S, 0x10, 0, 8,
511 	    .config_function = puc_config_quatech
512 	},
513 
514 	{   0x1393, 0x1024, 0xffff, 0,
515 	    "Moxa Technologies, Smartio CP-102E/PCIe",
516 	    DEFAULT_RCLK * 8,
517 	    PUC_PORT_2S, 0x14, 0, -1,
518 	    .config_function = puc_config_moxa
519 	},
520 
521 	{   0x1393, 0x1025, 0xffff, 0,
522 	    "Moxa Technologies, Smartio CP-102EL/PCIe",
523 	    DEFAULT_RCLK * 8,
524 	    PUC_PORT_2S, 0x14, 0, -1,
525 	    .config_function = puc_config_moxa
526 	},
527 
528 	{   0x1393, 0x1040, 0xffff, 0,
529 	    "Moxa Technologies, Smartio C104H/PCI",
530 	    DEFAULT_RCLK * 8,
531 	    PUC_PORT_4S, 0x18, 0, 8,
532 	},
533 
534 	{   0x1393, 0x1041, 0xffff, 0,
535 	    "Moxa Technologies, Smartio CP-104UL/PCI",
536 	    DEFAULT_RCLK * 8,
537 	    PUC_PORT_4S, 0x18, 0, 8,
538 	},
539 
540 	{   0x1393, 0x1042, 0xffff, 0,
541 	    "Moxa Technologies, Smartio CP-104JU/PCI",
542 	    DEFAULT_RCLK * 8,
543 	    PUC_PORT_4S, 0x18, 0, 8,
544 	},
545 
546 	{   0x1393, 0x1043, 0xffff, 0,
547 	    "Moxa Technologies, Smartio CP-104EL/PCIe",
548 	    DEFAULT_RCLK * 8,
549 	    PUC_PORT_4S, 0x18, 0, 8,
550 	},
551 
552 	{   0x1393, 0x1045, 0xffff, 0,
553 	    "Moxa Technologies, Smartio CP-104EL-A/PCIe",
554 	    DEFAULT_RCLK * 8,
555 	    PUC_PORT_4S, 0x14, 0, -1,
556 	    .config_function = puc_config_moxa
557 	},
558 
559 	{   0x1393, 0x1120, 0xffff, 0,
560 	    "Moxa Technologies, CP-112UL",
561 	    DEFAULT_RCLK * 8,
562 	    PUC_PORT_2S, 0x18, 0, 8,
563 	},
564 
565 	{   0x1393, 0x1141, 0xffff, 0,
566 	    "Moxa Technologies, Industio CP-114",
567 	    DEFAULT_RCLK * 8,
568 	    PUC_PORT_4S, 0x18, 0, 8,
569 	},
570 
571 	{   0x1393, 0x1144, 0xffff, 0,
572 	    "Moxa Technologies, Smartio CP-114EL/PCIe",
573 	    DEFAULT_RCLK * 8,
574 	    PUC_PORT_4S, 0x14, 0, -1,
575 	    .config_function = puc_config_moxa
576 	},
577 
578 	{   0x1393, 0x1182, 0xffff, 0,
579 	    "Moxa Technologies, Smartio CP-118EL-A/PCIe",
580 	    DEFAULT_RCLK * 8,
581 	    PUC_PORT_8S, 0x14, 0, -1,
582 	    .config_function = puc_config_moxa
583 	},
584 
585 	{   0x1393, 0x1680, 0xffff, 0,
586 	    "Moxa Technologies, C168H/PCI",
587 	    DEFAULT_RCLK * 8,
588 	    PUC_PORT_8S, 0x18, 0, 8,
589 	},
590 
591 	{   0x1393, 0x1681, 0xffff, 0,
592 	    "Moxa Technologies, C168U/PCI",
593 	    DEFAULT_RCLK * 8,
594 	    PUC_PORT_8S, 0x18, 0, 8,
595 	},
596 
597 	{   0x1393, 0x1682, 0xffff, 0,
598 	    "Moxa Technologies, CP-168EL/PCIe",
599 	    DEFAULT_RCLK * 8,
600 	    PUC_PORT_8S, 0x18, 0, 8,
601 	},
602 
603 	{   0x1393, 0x1683, 0xffff, 0,
604 	    "Moxa Technologies, Smartio CP-168EL-A/PCIe",
605 	    DEFAULT_RCLK * 8,
606 	    PUC_PORT_8S, 0x14, 0, -1,
607 	    .config_function = puc_config_moxa
608 	},
609 
610 	{   0x13a8, 0x0152, 0xffff, 0,
611 	    "Exar XR17C/D152",
612 	    DEFAULT_RCLK * 8,
613 	    PUC_PORT_2S, 0x10, 0, -1,
614 	    .config_function = puc_config_exar
615 	},
616 
617 	{   0x13a8, 0x0154, 0xffff, 0,
618 	    "Exar XR17C154",
619 	    DEFAULT_RCLK * 8,
620 	    PUC_PORT_4S, 0x10, 0, -1,
621 	    .config_function = puc_config_exar
622 	},
623 
624 	{   0x13a8, 0x0158, 0xffff, 0,
625 	    "Exar XR17C158",
626 	    DEFAULT_RCLK * 8,
627 	    PUC_PORT_8S, 0x10, 0, -1,
628 	    .config_function = puc_config_exar
629 	},
630 
631 	{   0x13a8, 0x0258, 0xffff, 0,
632 	    "Exar XR17V258IV",
633 	    DEFAULT_RCLK * 8,
634 	    PUC_PORT_8S, 0x10, 0, -1,
635 	    .config_function = puc_config_exar
636 	},
637 
638 	/* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
639 	{   0x13a8, 0x0358, 0xffff, 0,
640 	    "Exar XR17V358",
641 	    125000000,
642 	    PUC_PORT_8S, 0x10, 0, -1,
643 	    .config_function = puc_config_exar_pcie
644 	},
645 
646 	{   0x13fe, 0x1600, 0x1602, 0x0002,
647 	    "Advantech PCI-1602",
648 	    DEFAULT_RCLK * 8,
649 	    PUC_PORT_2S, 0x10, 0, 8,
650 	},
651 
652 	{   0x1407, 0x0100, 0xffff, 0,
653 	    "Lava Computers Dual Serial",
654 	    DEFAULT_RCLK,
655 	    PUC_PORT_2S, 0x10, 4, 0,
656 	},
657 
658 	{   0x1407, 0x0101, 0xffff, 0,
659 	    "Lava Computers Quatro A",
660 	    DEFAULT_RCLK,
661 	    PUC_PORT_2S, 0x10, 4, 0,
662 	},
663 
664 	{   0x1407, 0x0102, 0xffff, 0,
665 	    "Lava Computers Quatro B",
666 	    DEFAULT_RCLK,
667 	    PUC_PORT_2S, 0x10, 4, 0,
668 	},
669 
670 	{   0x1407, 0x0120, 0xffff, 0,
671 	    "Lava Computers Quattro-PCI A",
672 	    DEFAULT_RCLK,
673 	    PUC_PORT_2S, 0x10, 4, 0,
674 	},
675 
676 	{   0x1407, 0x0121, 0xffff, 0,
677 	    "Lava Computers Quattro-PCI B",
678 	    DEFAULT_RCLK,
679 	    PUC_PORT_2S, 0x10, 4, 0,
680 	},
681 
682 	{   0x1407, 0x0180, 0xffff, 0,
683 	    "Lava Computers Octo A",
684 	    DEFAULT_RCLK,
685 	    PUC_PORT_4S, 0x10, 4, 0,
686 	},
687 
688 	{   0x1407, 0x0181, 0xffff, 0,
689 	    "Lava Computers Octo B",
690 	    DEFAULT_RCLK,
691 	    PUC_PORT_4S, 0x10, 4, 0,
692 	},
693 
694 	{   0x1409, 0x7268, 0xffff, 0,
695 	    "Sunix SUN1888",
696 	    0,
697 	    PUC_PORT_2P, 0x10, 0, 8,
698 	},
699 
700 	{   0x1409, 0x7168, 0xffff, 0,
701 	    NULL,
702 	    DEFAULT_RCLK * 8,
703 	    PUC_PORT_NONSTANDARD, 0x10, -1, -1,
704 	    .config_function = puc_config_timedia
705 	},
706 
707 	/*
708 	 * Boards with an Oxford Semiconductor chip.
709 	 *
710 	 * Oxford Semiconductor provides documentation for their chip at:
711 	 * <URL:http://www.plxtech.com/products/uart/>
712 	 *
713 	 * As sold by Kouwell <URL:http://www.kouwell.com/>.
714 	 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
715 	 */
716 	{
717 	    0x1415, 0x9501, 0x10fc, 0xc070,
718 	    "I-O DATA RSA-PCI2/R",
719 	    DEFAULT_RCLK * 8,
720 	    PUC_PORT_2S, 0x10, 0, 8,
721 	},
722 
723 	{   0x1415, 0x9501, 0x131f, 0x2050,
724 	    "SIIG Cyber 4 PCI 16550",
725 	    DEFAULT_RCLK * 10,
726 	    PUC_PORT_4S, 0x10, 0, 8,
727 	},
728 
729 	{   0x1415, 0x9501, 0x131f, 0x2051,
730 	    "SIIG Cyber 4S PCI 16C650 (20x family)",
731 	    DEFAULT_RCLK * 10,
732 	    PUC_PORT_4S, 0x10, 0, 8,
733 	},
734 
735 	{   0x1415, 0x9501, 0x131f, 0x2052,
736 	    "SIIG Quartet Serial 850",
737 	    DEFAULT_RCLK * 10,
738 	    PUC_PORT_4S, 0x10, 0, 8,
739 	},
740 
741 	{   0x1415, 0x9501, 0x14db, 0x2150,
742 	    "Kuroutoshikou SERIAL4P-LPPCI2",
743 	    DEFAULT_RCLK * 10,
744 	    PUC_PORT_4S, 0x10, 0, 8,
745 	},
746 
747 	{   0x1415, 0x9501, 0xffff, 0,
748 	    "Oxford Semiconductor OX16PCI954 UARTs",
749 	    0,
750 	    PUC_PORT_4S, 0x10, 0, 8,
751 	    .config_function = puc_config_oxford_pci954
752 	},
753 
754 	{   0x1415, 0x950a, 0x131f, 0x2030,
755 	    "SIIG Cyber 2S PCIe",
756 	    DEFAULT_RCLK * 10,
757 	    PUC_PORT_2S, 0x10, 0, 8,
758 	},
759 
760 	{   0x1415, 0x950a, 0x131f, 0x2032,
761 	    "SIIG Cyber Serial Dual PCI 16C850",
762 	    DEFAULT_RCLK * 10,
763 	    PUC_PORT_4S, 0x10, 0, 8,
764 	},
765 
766 	{   0x1415, 0x950a, 0x131f, 0x2061,
767 	    "SIIG Cyber 2SP1 PCIe",
768 	    DEFAULT_RCLK * 10,
769 	    PUC_PORT_2S, 0x10, 0, 8,
770 	},
771 
772 	{   0x1415, 0x950a, 0xffff, 0,
773 	    "Oxford Semiconductor OX16PCI954 UARTs",
774 	    DEFAULT_RCLK,
775 	    PUC_PORT_4S, 0x10, 0, 8,
776 	},
777 
778 	{   0x1415, 0x9511, 0xffff, 0,
779 	    "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
780 	    DEFAULT_RCLK,
781 	    PUC_PORT_4S, 0x10, 0, 8,
782 	},
783 
784 	{   0x1415, 0x9521, 0xffff, 0,
785 	    "Oxford Semiconductor OX16PCI952 UARTs",
786 	    DEFAULT_RCLK,
787 	    PUC_PORT_2S, 0x10, 4, 0,
788 	},
789 
790 	{   0x1415, 0x9538, 0xffff, 0,
791 	    "Oxford Semiconductor OX16PCI958 UARTs",
792 	    DEFAULT_RCLK,
793 	    PUC_PORT_8S, 0x18, 0, 8,
794 	},
795 
796 	/*
797 	 * Perle boards use Oxford Semiconductor chips, but they store the
798 	 * Oxford Semiconductor device ID as a subvendor device ID and use
799 	 * their own device IDs.
800 	 */
801 
802 	{   0x155f, 0x0331, 0xffff, 0,
803 	    "Perle Ultraport4 Express",
804 	    DEFAULT_RCLK * 8,
805 	    PUC_PORT_4S, 0x10, 0, 8,
806 	},
807 
808 	{   0x155f, 0xB012, 0xffff, 0,
809 	    "Perle Speed2 LE",
810 	    DEFAULT_RCLK * 8,
811 	    PUC_PORT_2S, 0x10, 0, 8,
812 	},
813 
814 	{   0x155f, 0xB022, 0xffff, 0,
815 	    "Perle Speed2 LE",
816 	    DEFAULT_RCLK * 8,
817 	    PUC_PORT_2S, 0x10, 0, 8,
818 	},
819 
820 	{   0x155f, 0xB004, 0xffff, 0,
821 	    "Perle Speed4 LE",
822 	    DEFAULT_RCLK * 8,
823 	    PUC_PORT_4S, 0x10, 0, 8,
824 	},
825 
826 	{   0x155f, 0xB008, 0xffff, 0,
827 	    "Perle Speed8 LE",
828 	    DEFAULT_RCLK * 8,
829 	    PUC_PORT_8S, 0x10, 0, 8,
830 	},
831 
832 
833 	/*
834 	 * Oxford Semiconductor PCI Express Expresso family
835 	 *
836 	 * Found in many 'native' PCI Express serial boards such as:
837 	 *
838 	 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
839 	 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
840 	 *
841 	 * Lindy 51189 (4 port)
842 	 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
843 	 *
844 	 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
845 	 * <URL:http://www.startech.com>
846 	 */
847 
848 	{   0x1415, 0xc11b, 0xffff, 0,
849 	    "Oxford Semiconductor OXPCIe952 1S1P",
850 	    DEFAULT_RCLK * 0x22,
851 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
852 	    .config_function = puc_config_oxford_pcie
853 	},
854 
855 	{   0x1415, 0xc138, 0xffff, 0,
856 	    "Oxford Semiconductor OXPCIe952 UARTs",
857 	    DEFAULT_RCLK * 0x22,
858 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
859 	    .config_function = puc_config_oxford_pcie
860 	},
861 
862 	{   0x1415, 0xc158, 0xffff, 0,
863 	    "Oxford Semiconductor OXPCIe952 UARTs",
864 	    DEFAULT_RCLK * 0x22,
865 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
866 	    .config_function = puc_config_oxford_pcie
867 	},
868 
869 	{   0x1415, 0xc15d, 0xffff, 0,
870 	    "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
871 	    DEFAULT_RCLK * 0x22,
872 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
873 	    .config_function = puc_config_oxford_pcie
874 	},
875 
876 	{   0x1415, 0xc208, 0xffff, 0,
877 	    "Oxford Semiconductor OXPCIe954 UARTs",
878 	    DEFAULT_RCLK * 0x22,
879 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
880 	    .config_function = puc_config_oxford_pcie
881 	},
882 
883 	{   0x1415, 0xc20d, 0xffff, 0,
884 	    "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
885 	    DEFAULT_RCLK * 0x22,
886 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
887 	    .config_function = puc_config_oxford_pcie
888 	},
889 
890 	{   0x1415, 0xc308, 0xffff, 0,
891 	    "Oxford Semiconductor OXPCIe958 UARTs",
892 	    DEFAULT_RCLK * 0x22,
893 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
894 	    .config_function = puc_config_oxford_pcie
895 	},
896 
897 	{   0x1415, 0xc30d, 0xffff, 0,
898 	    "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
899 	    DEFAULT_RCLK * 0x22,
900 	    PUC_PORT_NONSTANDARD, 0x10, 0, -1,
901 	    .config_function = puc_config_oxford_pcie
902 	},
903 
904 	{   0x14d2, 0x8010, 0xffff, 0,
905 	    "VScom PCI-100L",
906 	    DEFAULT_RCLK * 8,
907 	    PUC_PORT_1S, 0x14, 0, 0,
908 	},
909 
910 	{   0x14d2, 0x8020, 0xffff, 0,
911 	    "VScom PCI-200L",
912 	    DEFAULT_RCLK * 8,
913 	    PUC_PORT_2S, 0x14, 4, 0,
914 	},
915 
916 	{   0x14d2, 0x8028, 0xffff, 0,
917 	    "VScom 200Li",
918 	    DEFAULT_RCLK,
919 	    PUC_PORT_2S, 0x20, 0, 8,
920 	},
921 
922 	/*
923 	 * VScom (Titan?) PCI-800L.  More modern variant of the
924 	 * PCI-800.  Uses 6 discrete 16550 UARTs, plus another
925 	 * two of them obviously implemented as macro cells in
926 	 * the ASIC.  This causes the weird port access pattern
927 	 * below, where two of the IO port ranges each access
928 	 * one of the ASIC UARTs, and a block of IO addresses
929 	 * access the external UARTs.
930 	 */
931 	{   0x14d2, 0x8080, 0xffff, 0,
932 	    "Titan VScom PCI-800L",
933 	    DEFAULT_RCLK * 8,
934 	    PUC_PORT_8S, 0x14, -1, -1,
935 	    .config_function = puc_config_titan
936 	},
937 
938 	/*
939 	 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
940 	 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
941 	 * device ID 3 and PCI device 1 device ID 4.
942 	 */
943 	{   0x14d2, 0xa003, 0xffff, 0,
944 	    "Titan PCI-800H",
945 	    DEFAULT_RCLK * 8,
946 	    PUC_PORT_4S, 0x10, 0, 8,
947 	},
948 
949 	{   0x14d2, 0xa004, 0xffff, 0,
950 	    "Titan PCI-800H",
951 	    DEFAULT_RCLK * 8,
952 	    PUC_PORT_4S, 0x10, 0, 8,
953 	},
954 
955 	{   0x14d2, 0xa005, 0xffff, 0,
956 	    "Titan PCI-200H",
957 	    DEFAULT_RCLK * 8,
958 	    PUC_PORT_2S, 0x10, 0, 8,
959 	},
960 
961 	{   0x14d2, 0xe020, 0xffff, 0,
962 	    "Titan VScom PCI-200HV2",
963 	    DEFAULT_RCLK * 8,
964 	    PUC_PORT_2S, 0x10, 4, 0,
965 	},
966 
967 	{   0x14d2, 0xa007, 0xffff, 0,
968 	    "Titan VScom PCIex-800H",
969 	    DEFAULT_RCLK * 8,
970 	    PUC_PORT_4S, 0x10, 0, 8,
971 	},
972 
973 	{   0x14d2, 0xa008, 0xffff, 0,
974 	    "Titan VScom PCIex-800H",
975 	    DEFAULT_RCLK * 8,
976 	    PUC_PORT_4S, 0x10, 0, 8,
977 	},
978 
979 	{   0x14db, 0x2130, 0xffff, 0,
980 	    "Avlab Technology, PCI IO 2S",
981 	    DEFAULT_RCLK,
982 	    PUC_PORT_2S, 0x10, 4, 0,
983 	},
984 
985 	{   0x14db, 0x2150, 0xffff, 0,
986 	    "Avlab Low Profile PCI 4 Serial",
987 	    DEFAULT_RCLK,
988 	    PUC_PORT_4S, 0x10, 4, 0,
989 	},
990 
991 	{   0x14db, 0x2152, 0xffff, 0,
992 	    "Avlab Low Profile PCI 4 Serial",
993 	    DEFAULT_RCLK,
994 	    PUC_PORT_4S, 0x10, 4, 0,
995 	},
996 
997 	{   0x1592, 0x0781, 0xffff, 0,
998 	    "Syba Tech Ltd. PCI-4S2P-550-ECP",
999 	    DEFAULT_RCLK,
1000 	    PUC_PORT_4S1P, 0x10, 0, -1,
1001 	    .config_function = puc_config_syba
1002 	},
1003 
1004 	{   0x1fd4, 0x1999, 0x1fd4, 0x0002,
1005 	    "Sunix SER5xxxx 2-port serial",
1006 	    DEFAULT_RCLK * 8,
1007 	    PUC_PORT_2S, 0x10, 0, 8,
1008 	},
1009 
1010 	{   0x1fd4, 0x1999, 0x1fd4, 0x0004,
1011 	    "Sunix SER5xxxx 4-port serial",
1012 	    DEFAULT_RCLK * 8,
1013 	    PUC_PORT_4S, 0x10, 0, 8,
1014 	},
1015 
1016 	{   0x1fd4, 0x1999, 0x1fd4, 0x0008,
1017 	    "Sunix SER5xxxx 8-port serial",
1018 	    DEFAULT_RCLK * 8,
1019 	    PUC_PORT_8S, -1, -1, -1,
1020 	    .config_function = puc_config_sunix
1021 	},
1022 
1023 	{   0x1fd4, 0x1999, 0x1fd4, 0x0101,
1024 	    "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1025 	    DEFAULT_RCLK * 8,
1026 	    PUC_PORT_1S1P, -1, -1, -1,
1027 	    .config_function = puc_config_sunix
1028 	},
1029 
1030 	{   0x1fd4, 0x1999, 0x1fd4, 0x0102,
1031 	    "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1032 	    DEFAULT_RCLK * 8,
1033 	    PUC_PORT_2S1P, -1, -1, -1,
1034 	    .config_function = puc_config_sunix
1035 	},
1036 
1037 	{   0x1fd4, 0x1999, 0x1fd4, 0x0104,
1038 	    "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1039 	    DEFAULT_RCLK * 8,
1040 	    PUC_PORT_4S1P, -1, -1, -1,
1041 	    .config_function = puc_config_sunix
1042 	},
1043 
1044 	{   0x5372, 0x6872, 0xffff, 0,
1045 	    "Feasso PCI FPP-02 2S1P",
1046 	    DEFAULT_RCLK,
1047 	    PUC_PORT_2S1P, 0x10, 4, 0,
1048 	},
1049 
1050 	{   0x5372, 0x6873, 0xffff, 0,
1051 	    "Sun 1040 PCI Quad Serial",
1052 	    DEFAULT_RCLK,
1053 	    PUC_PORT_4S, 0x10, 4, 0,
1054 	},
1055 
1056 	{   0x6666, 0x0001, 0xffff, 0,
1057 	    "Decision Computer Inc, PCCOM 4-port serial",
1058 	    DEFAULT_RCLK,
1059 	    PUC_PORT_4S, 0x1c, 0, 8,
1060 	},
1061 
1062 	{   0x6666, 0x0002, 0xffff, 0,
1063 	    "Decision Computer Inc, PCCOM 8-port serial",
1064 	    DEFAULT_RCLK,
1065 	    PUC_PORT_8S, 0x1c, 0, 8,
1066 	},
1067 
1068 	{   0x6666, 0x0004, 0xffff, 0,
1069 	    "PCCOM dual port RS232/422/485",
1070 	    DEFAULT_RCLK,
1071 	    PUC_PORT_2S, 0x1c, 0, 8,
1072 	},
1073 
1074 	{   0x9710, 0x9815, 0xffff, 0,
1075 	    "NetMos NM9815 Dual 1284 Printer port",
1076 	    0,
1077 	    PUC_PORT_2P, 0x10, 8, 0,
1078 	},
1079 
1080 	/*
1081 	 * This is more specific than the generic NM9835 entry, and is placed
1082 	 * here to _prevent_ puc(4) from claiming this single port card.
1083 	 *
1084 	 * uart(4) will claim this device.
1085 	 */
1086 	{   0x9710, 0x9835, 0x1000, 1,
1087 	    "NetMos NM9835 based 1-port serial",
1088 	    DEFAULT_RCLK,
1089 	    PUC_PORT_1S, 0x10, 4, 0,
1090 	},
1091 
1092 	{   0x9710, 0x9835, 0x1000, 2,
1093 	    "NetMos NM9835 based 2-port serial",
1094 	    DEFAULT_RCLK,
1095 	    PUC_PORT_2S, 0x10, 4, 0,
1096 	},
1097 
1098 	{   0x9710, 0x9835, 0xffff, 0,
1099 	    "NetMos NM9835 Dual UART and 1284 Printer port",
1100 	    DEFAULT_RCLK,
1101 	    PUC_PORT_2S1P, 0x10, 4, 0,
1102 	},
1103 
1104 	{   0x9710, 0x9845, 0x1000, 0x0006,
1105 	    "NetMos NM9845 6 Port UART",
1106 	    DEFAULT_RCLK,
1107 	    PUC_PORT_6S, 0x10, 4, 0,
1108 	},
1109 
1110 	{   0x9710, 0x9845, 0xffff, 0,
1111 	    "NetMos NM9845 Quad UART and 1284 Printer port",
1112 	    DEFAULT_RCLK,
1113 	    PUC_PORT_4S1P, 0x10, 4, 0,
1114 	},
1115 
1116 	{   0x9710, 0x9865, 0xa000, 0x3002,
1117 	    "NetMos NM9865 Dual UART",
1118 	    DEFAULT_RCLK,
1119 	    PUC_PORT_2S, 0x10, 4, 0,
1120 	},
1121 
1122 	{   0x9710, 0x9865, 0xa000, 0x3003,
1123 	    "NetMos NM9865 Triple UART",
1124 	    DEFAULT_RCLK,
1125 	    PUC_PORT_3S, 0x10, 4, 0,
1126 	},
1127 
1128 	{   0x9710, 0x9865, 0xa000, 0x3004,
1129 	    "NetMos NM9865 Quad UART",
1130 	    DEFAULT_RCLK,
1131 	    PUC_PORT_4S, 0x10, 4, 0,
1132 	},
1133 
1134 	{   0x9710, 0x9865, 0xa000, 0x3011,
1135 	    "NetMos NM9865 Single UART and 1284 Printer port",
1136 	    DEFAULT_RCLK,
1137 	    PUC_PORT_1S1P, 0x10, 4, 0,
1138 	},
1139 
1140 	{   0x9710, 0x9865, 0xa000, 0x3012,
1141 	    "NetMos NM9865 Dual UART and 1284 Printer port",
1142 	    DEFAULT_RCLK,
1143 	    PUC_PORT_2S1P, 0x10, 4, 0,
1144 	},
1145 
1146 	{   0x9710, 0x9865, 0xa000, 0x3020,
1147 	    "NetMos NM9865 Dual 1284 Printer port",
1148 	    DEFAULT_RCLK,
1149 	    PUC_PORT_2P, 0x10, 4, 0,
1150 	},
1151 
1152 	{   0xb00c, 0x021c, 0xffff, 0,
1153 	    "IC Book Labs Gunboat x4 Lite",
1154 	    DEFAULT_RCLK,
1155 	    PUC_PORT_4S, 0x10, 0, 8,
1156 	    .config_function = puc_config_icbook
1157 	},
1158 
1159 	{   0xb00c, 0x031c, 0xffff, 0,
1160 	    "IC Book Labs Gunboat x4 Pro",
1161 	    DEFAULT_RCLK,
1162 	    PUC_PORT_4S, 0x10, 0, 8,
1163 	    .config_function = puc_config_icbook
1164 	},
1165 
1166 	{   0xb00c, 0x041c, 0xffff, 0,
1167 	    "IC Book Labs Ironclad x8 Lite",
1168 	    DEFAULT_RCLK,
1169 	    PUC_PORT_8S, 0x10, 0, 8,
1170 	    .config_function = puc_config_icbook
1171 	},
1172 
1173 	{   0xb00c, 0x051c, 0xffff, 0,
1174 	    "IC Book Labs Ironclad x8 Pro",
1175 	    DEFAULT_RCLK,
1176 	    PUC_PORT_8S, 0x10, 0, 8,
1177 	    .config_function = puc_config_icbook
1178 	},
1179 
1180 	{   0xb00c, 0x081c, 0xffff, 0,
1181 	    "IC Book Labs Dreadnought x16 Pro",
1182 	    DEFAULT_RCLK * 8,
1183 	    PUC_PORT_16S, 0x10, 0, 8,
1184 	    .config_function = puc_config_icbook
1185 	},
1186 
1187 	{   0xb00c, 0x091c, 0xffff, 0,
1188 	    "IC Book Labs Dreadnought x16 Lite",
1189 	    DEFAULT_RCLK,
1190 	    PUC_PORT_16S, 0x10, 0, 8,
1191 	    .config_function = puc_config_icbook
1192 	},
1193 
1194 	{   0xb00c, 0x0a1c, 0xffff, 0,
1195 	    "IC Book Labs Gunboat x2 Low Profile",
1196 	    DEFAULT_RCLK,
1197 	    PUC_PORT_2S, 0x10, 0, 8,
1198 	},
1199 
1200 	{   0xb00c, 0x0b1c, 0xffff, 0,
1201 	    "IC Book Labs Gunboat x4 Low Profile",
1202 	    DEFAULT_RCLK,
1203 	    PUC_PORT_4S, 0x10, 0, 8,
1204 	    .config_function = puc_config_icbook
1205 	},
1206 
1207 	{ 0xffff, 0, 0xffff, 0, NULL, 0 }
1208 };
1209 
1210 static int
1211 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1212     intptr_t *res)
1213 {
1214 	switch (cmd) {
1215 	case PUC_CFG_GET_OFS:
1216 		*res = 8 * (port & 1);
1217 		return (0);
1218 	case PUC_CFG_GET_RID:
1219 		*res = 0x14 + (port >> 1) * 4;
1220 		return (0);
1221 	default:
1222 		break;
1223 	}
1224 	return (ENXIO);
1225 }
1226 
1227 static int
1228 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1229     intptr_t *res)
1230 {
1231 	const struct puc_cfg *cfg = sc->sc_cfg;
1232 
1233 	if (cmd == PUC_CFG_GET_OFS) {
1234 		if (cfg->subdevice == 0x1282)		/* Everest SP */
1235 			port <<= 1;
1236 		else if (cfg->subdevice == 0x104b)	/* Maestro SP2 */
1237 			port = (port == 3) ? 4 : port;
1238 		*res = port * 8 + ((port > 2) ? 0x18 : 0);
1239 		return (0);
1240 	}
1241 	return (ENXIO);
1242 }
1243 
1244 static int
1245 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1246     intptr_t *res)
1247 {
1248 	if (cmd == PUC_CFG_GET_OFS) {
1249 		*res = port * 0x200;
1250 		return (0);
1251 	}
1252 	return (ENXIO);
1253 }
1254 
1255 static int
1256 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1257     intptr_t *res)
1258 {
1259 	if (cmd == PUC_CFG_GET_OFS) {
1260 		*res = port * 0x400;
1261 		return (0);
1262 	}
1263 	return (ENXIO);
1264 }
1265 
1266 static int
1267 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1268     intptr_t *res)
1269 {
1270 	if (cmd == PUC_CFG_GET_ILR) {
1271 		*res = PUC_ILR_DIGI;
1272 		return (0);
1273 	}
1274 	return (ENXIO);
1275 }
1276 
1277 static int
1278 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1279     intptr_t *res)
1280 {
1281 	if (cmd == PUC_CFG_GET_OFS) {
1282 		const struct puc_cfg *cfg = sc->sc_cfg;
1283 
1284 		if (port == 3 && (cfg->device == 0x1045 ||
1285 		    cfg->device == 0x1144))
1286 			port = 7;
1287 		*res = port * 0x200;
1288 
1289 		return 0;
1290 	}
1291 	return (ENXIO);
1292 }
1293 
1294 static int
1295 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1296     intptr_t *res)
1297 {
1298 	const struct puc_cfg *cfg = sc->sc_cfg;
1299 	struct puc_bar *bar;
1300 	uint8_t v0, v1;
1301 
1302 	switch (cmd) {
1303 	case PUC_CFG_SETUP:
1304 		/*
1305 		 * Check if the scratchpad register is enabled or if the
1306 		 * interrupt status and options registers are active.
1307 		 */
1308 		bar = puc_get_bar(sc, cfg->rid);
1309 		if (bar == NULL)
1310 			return (ENXIO);
1311 		/* Set DLAB in the LCR register of UART 0. */
1312 		bus_write_1(bar->b_res, 3, 0x80);
1313 		/* Write 0 to the SPR register of UART 0. */
1314 		bus_write_1(bar->b_res, 7, 0);
1315 		/* Read back the contents of the SPR register of UART 0. */
1316 		v0 = bus_read_1(bar->b_res, 7);
1317 		/* Write a specific value to the SPR register of UART 0. */
1318 		bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1319 		/* Read back the contents of the SPR register of UART 0. */
1320 		v1 = bus_read_1(bar->b_res, 7);
1321 		/* Clear DLAB in the LCR register of UART 0. */
1322 		bus_write_1(bar->b_res, 3, 0);
1323 		/* Save the two values read-back from the SPR register. */
1324 		sc->sc_cfg_data = (v0 << 8) | v1;
1325 		if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1326 			/*
1327 			 * The SPR register echoed the two values written
1328 			 * by us. This means that the SPAD jumper is set.
1329 			 */
1330 			device_printf(sc->sc_dev, "warning: extra features "
1331 			    "not usable -- SPAD compatibility enabled\n");
1332 			return (0);
1333 		}
1334 		if (v0 != 0) {
1335 			/*
1336 			 * The first value doesn't match. This can only mean
1337 			 * that the SPAD jumper is not set and that a non-
1338 			 * standard fixed clock multiplier jumper is set.
1339 			 */
1340 			if (bootverbose)
1341 				device_printf(sc->sc_dev, "fixed clock rate "
1342 				    "multiplier of %d\n", 1 << v0);
1343 			if (v0 < -cfg->clock)
1344 				device_printf(sc->sc_dev, "warning: "
1345 				    "suboptimal fixed clock rate multiplier "
1346 				    "setting\n");
1347 			return (0);
1348 		}
1349 		/*
1350 		 * The first value matched, but the second didn't. We know
1351 		 * that the SPAD jumper is not set. We also know that the
1352 		 * clock rate multiplier is software controlled *and* that
1353 		 * we just programmed it to the maximum allowed.
1354 		 */
1355 		if (bootverbose)
1356 			device_printf(sc->sc_dev, "clock rate multiplier of "
1357 			    "%d selected\n", 1 << -cfg->clock);
1358 		return (0);
1359 	case PUC_CFG_GET_CLOCK:
1360 		v0 = (sc->sc_cfg_data >> 8) & 0xff;
1361 		v1 = sc->sc_cfg_data & 0xff;
1362 		if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1363 			/*
1364 			 * XXX With the SPAD jumper applied, there's no
1365 			 * easy way of knowing if there's also a clock
1366 			 * rate multiplier jumper installed. Let's hope
1367 			 * not...
1368 			 */
1369 			*res = DEFAULT_RCLK;
1370 		} else if (v0 == 0) {
1371 			/*
1372 			 * No clock rate multiplier jumper installed,
1373 			 * so we programmed the board with the maximum
1374 			 * multiplier allowed as given to us in the
1375 			 * clock field of the config record (negated).
1376 			 */
1377 			*res = DEFAULT_RCLK << -cfg->clock;
1378 		} else
1379 			*res = DEFAULT_RCLK << v0;
1380 		return (0);
1381 	case PUC_CFG_GET_ILR:
1382 		v0 = (sc->sc_cfg_data >> 8) & 0xff;
1383 		v1 = sc->sc_cfg_data & 0xff;
1384 		*res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1385 		    ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1386 		return (0);
1387 	default:
1388 		break;
1389 	}
1390 	return (ENXIO);
1391 }
1392 
1393 static int
1394 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1395     intptr_t *res)
1396 {
1397 	static int base[] = { 0x251, 0x3f0, 0 };
1398 	const struct puc_cfg *cfg = sc->sc_cfg;
1399 	struct puc_bar *bar;
1400 	int efir, idx, ofs;
1401 	uint8_t v;
1402 
1403 	switch (cmd) {
1404 	case PUC_CFG_SETUP:
1405 		bar = puc_get_bar(sc, cfg->rid);
1406 		if (bar == NULL)
1407 			return (ENXIO);
1408 
1409 		/* configure both W83877TFs */
1410 		bus_write_1(bar->b_res, 0x250, 0x89);
1411 		bus_write_1(bar->b_res, 0x3f0, 0x87);
1412 		bus_write_1(bar->b_res, 0x3f0, 0x87);
1413 		idx = 0;
1414 		while (base[idx] != 0) {
1415 			efir = base[idx];
1416 			bus_write_1(bar->b_res, efir, 0x09);
1417 			v = bus_read_1(bar->b_res, efir + 1);
1418 			if ((v & 0x0f) != 0x0c)
1419 				return (ENXIO);
1420 			bus_write_1(bar->b_res, efir, 0x16);
1421 			v = bus_read_1(bar->b_res, efir + 1);
1422 			bus_write_1(bar->b_res, efir, 0x16);
1423 			bus_write_1(bar->b_res, efir + 1, v | 0x04);
1424 			bus_write_1(bar->b_res, efir, 0x16);
1425 			bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1426 			ofs = base[idx] & 0x300;
1427 			bus_write_1(bar->b_res, efir, 0x23);
1428 			bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1429 			bus_write_1(bar->b_res, efir, 0x24);
1430 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1431 			bus_write_1(bar->b_res, efir, 0x25);
1432 			bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1433 			bus_write_1(bar->b_res, efir, 0x17);
1434 			bus_write_1(bar->b_res, efir + 1, 0x03);
1435 			bus_write_1(bar->b_res, efir, 0x28);
1436 			bus_write_1(bar->b_res, efir + 1, 0x43);
1437 			idx++;
1438 		}
1439 		bus_write_1(bar->b_res, 0x250, 0xaa);
1440 		bus_write_1(bar->b_res, 0x3f0, 0xaa);
1441 		return (0);
1442 	case PUC_CFG_GET_OFS:
1443 		switch (port) {
1444 		case 0:
1445 			*res = 0x2f8;
1446 			return (0);
1447 		case 1:
1448 			*res = 0x2e8;
1449 			return (0);
1450 		case 2:
1451 			*res = 0x3f8;
1452 			return (0);
1453 		case 3:
1454 			*res = 0x3e8;
1455 			return (0);
1456 		case 4:
1457 			*res = 0x278;
1458 			return (0);
1459 		}
1460 		break;
1461 	default:
1462 		break;
1463 	}
1464 	return (ENXIO);
1465 }
1466 
1467 static int
1468 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1469     intptr_t *res)
1470 {
1471 	const struct puc_cfg *cfg = sc->sc_cfg;
1472 
1473 	switch (cmd) {
1474 	case PUC_CFG_GET_OFS:
1475 		if (cfg->ports == PUC_PORT_8S) {
1476 			*res = (port > 4) ? 8 * (port - 4) : 0;
1477 			return (0);
1478 		}
1479 		break;
1480 	case PUC_CFG_GET_RID:
1481 		if (cfg->ports == PUC_PORT_8S) {
1482 			*res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1483 			return (0);
1484 		}
1485 		if (cfg->ports == PUC_PORT_2S1P) {
1486 			switch (port) {
1487 			case 0: *res = 0x10; return (0);
1488 			case 1: *res = 0x14; return (0);
1489 			case 2: *res = 0x1c; return (0);
1490 			}
1491 		}
1492 		break;
1493 	default:
1494 		break;
1495 	}
1496 	return (ENXIO);
1497 }
1498 
1499 static int
1500 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1501     intptr_t *res)
1502 {
1503 	static const uint16_t dual[] = {
1504 	    0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1505 	    0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1506 	    0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1507 	    0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1508 	    0xD079, 0
1509 	};
1510 	static const uint16_t quad[] = {
1511 	    0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1512 	    0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1513 	    0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1514 	    0xB157, 0
1515 	};
1516 	static const uint16_t octa[] = {
1517 	    0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1518 	    0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1519 	};
1520 	static const struct {
1521 		int ports;
1522 		const uint16_t *ids;
1523 	} subdevs[] = {
1524 	    { 2, dual },
1525 	    { 4, quad },
1526 	    { 8, octa },
1527 	    { 0, NULL }
1528 	};
1529 	static char desc[64];
1530 	int dev, id;
1531 	uint16_t subdev;
1532 
1533 	switch (cmd) {
1534 	case PUC_CFG_GET_CLOCK:
1535 		if (port < 2)
1536 			*res = DEFAULT_RCLK * 8;
1537 		else
1538 			*res = DEFAULT_RCLK;
1539 		return (0);
1540 	case PUC_CFG_GET_DESC:
1541 		snprintf(desc, sizeof(desc),
1542 		    "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1543 		*res = (intptr_t)desc;
1544 		return (0);
1545 	case PUC_CFG_GET_NPORTS:
1546 		subdev = pci_get_subdevice(sc->sc_dev);
1547 		dev = 0;
1548 		while (subdevs[dev].ports != 0) {
1549 			id = 0;
1550 			while (subdevs[dev].ids[id] != 0) {
1551 				if (subdev == subdevs[dev].ids[id]) {
1552 					sc->sc_cfg_data = subdevs[dev].ports;
1553 					*res = sc->sc_cfg_data;
1554 					return (0);
1555 				}
1556 				id++;
1557 			}
1558 			dev++;
1559 		}
1560 		return (ENXIO);
1561 	case PUC_CFG_GET_OFS:
1562 		*res = (port == 1 || port == 3) ? 8 : 0;
1563 		return (0);
1564 	case PUC_CFG_GET_RID:
1565 		*res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1566 		return (0);
1567 	case PUC_CFG_GET_TYPE:
1568 		*res = PUC_TYPE_SERIAL;
1569 		return (0);
1570 	default:
1571 		break;
1572 	}
1573 	return (ENXIO);
1574 }
1575 
1576 static int
1577 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1578     int port __unused, intptr_t *res)
1579 {
1580 
1581 	switch (cmd) {
1582 	case PUC_CFG_GET_CLOCK:
1583 		/*
1584 		 * OXu16PCI954 use a 14.7456 MHz clock by default while
1585 		 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1586 		 */
1587 		if (pci_get_revid(sc->sc_dev) == 1)
1588 			*res = DEFAULT_RCLK * 8;
1589 		else
1590 			*res = DEFAULT_RCLK;
1591 		return (0);
1592 	default:
1593 		break;
1594 	}
1595 	return (ENXIO);
1596 }
1597 
1598 static int
1599 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1600     intptr_t *res)
1601 {
1602 	const struct puc_cfg *cfg = sc->sc_cfg;
1603 	int idx;
1604 	struct puc_bar *bar;
1605 	uint8_t value;
1606 
1607 	switch (cmd) {
1608 	case PUC_CFG_SETUP:
1609 		device_printf(sc->sc_dev, "%d UARTs detected\n",
1610 			sc->sc_nports);
1611 
1612 		/* Set UARTs to enhanced mode */
1613 		bar = puc_get_bar(sc, cfg->rid);
1614 		if (bar == NULL)
1615 			return (ENXIO);
1616 		for (idx = 0; idx < sc->sc_nports; idx++) {
1617 			value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1618 			    0x92);
1619 			bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1620 			    value | 0x10);
1621 		}
1622 		return (0);
1623 	case PUC_CFG_GET_LEN:
1624 		*res = 0x200;
1625 		return (0);
1626 	case PUC_CFG_GET_NPORTS:
1627 		/*
1628 		 * Check if we are being called from puc_bfe_attach()
1629 		 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1630 		 * puc_get_bar(), so we return a value of 16. This has cosmetic
1631 		 * side-effects at worst; in PUC_CFG_GET_DESC,
1632 		 * (int)sc->sc_cfg_data will not contain the true number of
1633 		 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1634 		 * call for this device family anyway.
1635 		 *
1636 		 * The check is for initialisation of sc->sc_bar[idx], which is
1637 		 * only done in puc_bfe_attach().
1638 		 */
1639 		idx = 0;
1640 		do {
1641 			if (sc->sc_bar[idx++].b_rid != -1) {
1642 				sc->sc_cfg_data = 16;
1643 				*res = sc->sc_cfg_data;
1644 				return (0);
1645 			}
1646 		} while (idx < PUC_PCI_BARS);
1647 
1648 		bar = puc_get_bar(sc, cfg->rid);
1649 		if (bar == NULL)
1650 			return (ENXIO);
1651 
1652 		value = bus_read_1(bar->b_res, 0x04);
1653 		if (value == 0)
1654 			return (ENXIO);
1655 
1656 		sc->sc_cfg_data = value;
1657 		*res = sc->sc_cfg_data;
1658 		return (0);
1659 	case PUC_CFG_GET_OFS:
1660 		*res = 0x1000 + (port << 9);
1661 		return (0);
1662 	case PUC_CFG_GET_TYPE:
1663 		*res = PUC_TYPE_SERIAL;
1664 		return (0);
1665 	default:
1666 		break;
1667 	}
1668 	return (ENXIO);
1669 }
1670 
1671 static int
1672 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1673     intptr_t *res)
1674 {
1675 	int error;
1676 
1677 	switch (cmd) {
1678 	case PUC_CFG_GET_OFS:
1679 		error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1680 		if (error != 0)
1681 			return (error);
1682 		*res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1683 		return (0);
1684 	case PUC_CFG_GET_RID:
1685 		error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1686 		if (error != 0)
1687 			return (error);
1688 		*res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1689 		return (0);
1690 	default:
1691 		break;
1692 	}
1693 	return (ENXIO);
1694 }
1695 
1696 static int
1697 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1698     intptr_t *res)
1699 {
1700 	switch (cmd) {
1701 	case PUC_CFG_GET_OFS:
1702 		*res = (port < 3) ? 0 : (port - 2) << 3;
1703 		return (0);
1704 	case PUC_CFG_GET_RID:
1705 		*res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1706 		return (0);
1707 	default:
1708 		break;
1709 	}
1710 	return (ENXIO);
1711 }
1712