1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * PCI "universal" communications card driver configuration data (used to 32 * match/attach the cards). 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 45 #include <dev/ic/ns16550.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <dev/puc/puc_bus.h> 51 #include <dev/puc/puc_cfg.h> 52 #include <dev/puc/puc_bfe.h> 53 54 static puc_config_f puc_config_advantech; 55 static puc_config_f puc_config_amc; 56 static puc_config_f puc_config_diva; 57 static puc_config_f puc_config_exar; 58 static puc_config_f puc_config_exar_pcie; 59 static puc_config_f puc_config_icbook; 60 static puc_config_f puc_config_moxa; 61 static puc_config_f puc_config_oxford_pci954; 62 static puc_config_f puc_config_oxford_pcie; 63 static puc_config_f puc_config_quatech; 64 static puc_config_f puc_config_syba; 65 static puc_config_f puc_config_siig; 66 static puc_config_f puc_config_sunix; 67 static puc_config_f puc_config_systembase; 68 static puc_config_f puc_config_timedia; 69 static puc_config_f puc_config_titan; 70 static puc_config_f puc_config_wch_ch38x; 71 72 const struct puc_cfg puc_pci_devices[] = { 73 { 0x0009, 0x7168, 0xffff, 0, 74 "Sunix SUN1889", 75 DEFAULT_RCLK * 8, 76 PUC_PORT_2S, 0x10, 0, 8, 77 }, 78 79 { 0x103c, 0x1048, 0x103c, 0x1049, 80 "HP Diva Serial [GSP] Multiport UART - Tosca Console", 81 DEFAULT_RCLK, 82 PUC_PORT_3S, 0x10, 0, -1, 83 .config_function = puc_config_diva 84 }, 85 86 { 0x103c, 0x1048, 0x103c, 0x104a, 87 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 88 DEFAULT_RCLK, 89 PUC_PORT_2S, 0x10, 0, -1, 90 .config_function = puc_config_diva 91 }, 92 93 { 0x103c, 0x1048, 0x103c, 0x104b, 94 "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 95 DEFAULT_RCLK, 96 PUC_PORT_4S, 0x10, 0, -1, 97 .config_function = puc_config_diva 98 }, 99 100 { 0x103c, 0x1048, 0x103c, 0x1223, 101 "HP Diva Serial [GSP] Multiport UART - Superdome Console", 102 DEFAULT_RCLK, 103 PUC_PORT_3S, 0x10, 0, -1, 104 .config_function = puc_config_diva 105 }, 106 107 { 0x103c, 0x1048, 0x103c, 0x1226, 108 "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 109 DEFAULT_RCLK, 110 PUC_PORT_3S, 0x10, 0, -1, 111 .config_function = puc_config_diva 112 }, 113 114 { 0x103c, 0x1048, 0x103c, 0x1282, 115 "HP Diva Serial [GSP] Multiport UART - Everest SP2", 116 DEFAULT_RCLK, 117 PUC_PORT_3S, 0x10, 0, -1, 118 .config_function = puc_config_diva 119 }, 120 121 { 0x10b5, 0x1076, 0x10b5, 0x1076, 122 "VScom PCI-800", 123 DEFAULT_RCLK * 8, 124 PUC_PORT_8S, 0x18, 0, 8, 125 }, 126 127 { 0x10b5, 0x1077, 0x10b5, 0x1077, 128 "VScom PCI-400", 129 DEFAULT_RCLK * 8, 130 PUC_PORT_4S, 0x18, 0, 8, 131 }, 132 133 { 0x10b5, 0x1103, 0x10b5, 0x1103, 134 "VScom PCI-200", 135 DEFAULT_RCLK * 8, 136 PUC_PORT_2S, 0x18, 4, 0, 137 }, 138 139 /* 140 * Boca Research Turbo Serial 658 (8 serial port) card. 141 * Appears to be the same as Chase Research PLC PCI-FAST8 142 * and Perle PCI-FAST8 Multi-Port serial cards. 143 */ 144 { 0x10b5, 0x9050, 0x12e0, 0x0021, 145 "Boca Research Turbo Serial 658", 146 DEFAULT_RCLK * 4, 147 PUC_PORT_8S, 0x18, 0, 8, 148 }, 149 150 { 0x10b5, 0x9050, 0x12e0, 0x0031, 151 "Boca Research Turbo Serial 654", 152 DEFAULT_RCLK * 4, 153 PUC_PORT_4S, 0x18, 0, 8, 154 }, 155 156 /* 157 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 158 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 159 * into the subsystem fields, and claims that it's a 160 * network/misc (0x02/0x80) device. 161 */ 162 { 0x10b5, 0x9050, 0xd84d, 0x6808, 163 "Dolphin Peripherals 4035", 164 DEFAULT_RCLK, 165 PUC_PORT_2S, 0x18, 4, 0, 166 }, 167 168 /* 169 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 170 * a seemingly-lame EEPROM setup that puts the Dolphin IDs 171 * into the subsystem fields, and claims that it's a 172 * network/misc (0x02/0x80) device. 173 */ 174 { 0x10b5, 0x9050, 0xd84d, 0x6810, 175 "Dolphin Peripherals 4014", 176 0, 177 PUC_PORT_2P, 0x20, 4, 0, 178 }, 179 180 { 0x10e8, 0x818e, 0xffff, 0, 181 "Applied Micro Circuits 8 Port UART", 182 DEFAULT_RCLK, 183 PUC_PORT_8S, 0x14, -1, -1, 184 .config_function = puc_config_amc 185 }, 186 187 /* 188 * The following members of the Digi International Neo series are 189 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV. 190 * Accordingly, the PCIe versions of these cards incorporate a PLX 191 * PCIe-PCI-bridge. 192 */ 193 194 { 0x114f, 0x00b0, 0xffff, 0, 195 "Digi Neo PCI 4 Port", 196 DEFAULT_RCLK * 8, 197 PUC_PORT_4S, 0x10, 0, -1, 198 .config_function = puc_config_exar 199 }, 200 201 { 0x114f, 0x00b1, 0xffff, 0, 202 "Digi Neo PCI 8 Port", 203 DEFAULT_RCLK * 8, 204 PUC_PORT_8S, 0x10, 0, -1, 205 .config_function = puc_config_exar 206 }, 207 208 { 0x114f, 0x00f0, 0xffff, 0, 209 "Digi Neo PCIe 8 Port", 210 DEFAULT_RCLK * 8, 211 PUC_PORT_8S, 0x10, 0, -1, 212 .config_function = puc_config_exar 213 }, 214 215 { 0x114f, 0x00f1, 0xffff, 0, 216 "Digi Neo PCIe 4 Port", 217 DEFAULT_RCLK * 8, 218 PUC_PORT_4S, 0x10, 0, -1, 219 .config_function = puc_config_exar 220 }, 221 222 { 0x114f, 0x00f2, 0xffff, 0, 223 "Digi Neo PCIe 4 Port RJ45", 224 DEFAULT_RCLK * 8, 225 PUC_PORT_4S, 0x10, 0, -1, 226 .config_function = puc_config_exar 227 }, 228 229 { 0x114f, 0x00f3, 0xffff, 0, 230 "Digi Neo PCIe 8 Port RJ45", 231 DEFAULT_RCLK * 8, 232 PUC_PORT_8S, 0x10, 0, -1, 233 .config_function = puc_config_exar 234 }, 235 236 { 0x11fe, 0x8010, 0xffff, 0, 237 "Comtrol RocketPort 550/8 RJ11 part A", 238 DEFAULT_RCLK * 4, 239 PUC_PORT_4S, 0x10, 0, 8, 240 }, 241 242 { 0x11fe, 0x8011, 0xffff, 0, 243 "Comtrol RocketPort 550/8 RJ11 part B", 244 DEFAULT_RCLK * 4, 245 PUC_PORT_4S, 0x10, 0, 8, 246 }, 247 248 { 0x11fe, 0x8012, 0xffff, 0, 249 "Comtrol RocketPort 550/8 Octa part A", 250 DEFAULT_RCLK * 4, 251 PUC_PORT_4S, 0x10, 0, 8, 252 }, 253 254 { 0x11fe, 0x8013, 0xffff, 0, 255 "Comtrol RocketPort 550/8 Octa part B", 256 DEFAULT_RCLK * 4, 257 PUC_PORT_4S, 0x10, 0, 8, 258 }, 259 260 { 0x11fe, 0x8014, 0xffff, 0, 261 "Comtrol RocketPort 550/4 RJ45", 262 DEFAULT_RCLK * 4, 263 PUC_PORT_4S, 0x10, 0, 8, 264 }, 265 266 { 0x11fe, 0x8015, 0xffff, 0, 267 "Comtrol RocketPort 550/Quad", 268 DEFAULT_RCLK * 4, 269 PUC_PORT_4S, 0x10, 0, 8, 270 }, 271 272 { 0x11fe, 0x8016, 0xffff, 0, 273 "Comtrol RocketPort 550/16 part A", 274 DEFAULT_RCLK * 4, 275 PUC_PORT_4S, 0x10, 0, 8, 276 }, 277 278 { 0x11fe, 0x8017, 0xffff, 0, 279 "Comtrol RocketPort 550/16 part B", 280 DEFAULT_RCLK * 4, 281 PUC_PORT_12S, 0x10, 0, 8, 282 }, 283 284 { 0x11fe, 0x8018, 0xffff, 0, 285 "Comtrol RocketPort 550/8 part A", 286 DEFAULT_RCLK * 4, 287 PUC_PORT_4S, 0x10, 0, 8, 288 }, 289 290 { 0x11fe, 0x8019, 0xffff, 0, 291 "Comtrol RocketPort 550/8 part B", 292 DEFAULT_RCLK * 4, 293 PUC_PORT_4S, 0x10, 0, 8, 294 }, 295 296 /* 297 * IBM SurePOS 300 Series (481033H) serial ports 298 * Details can be found on the IBM RSS websites 299 */ 300 301 { 0x1014, 0x0297, 0xffff, 0, 302 "IBM SurePOS 300 Series (481033H) serial ports", 303 DEFAULT_RCLK, 304 PUC_PORT_4S, 0x10, 4, 0 305 }, 306 307 /* 308 * SIIG Boards. 309 * 310 * SIIG provides documentation for their boards at: 311 * <URL:http://www.siig.com/downloads.asp> 312 */ 313 314 { 0x131f, 0x1010, 0xffff, 0, 315 "SIIG Cyber I/O PCI 16C550 (10x family)", 316 DEFAULT_RCLK, 317 PUC_PORT_1S1P, 0x18, 4, 0, 318 }, 319 320 { 0x131f, 0x1011, 0xffff, 0, 321 "SIIG Cyber I/O PCI 16C650 (10x family)", 322 DEFAULT_RCLK, 323 PUC_PORT_1S1P, 0x18, 4, 0, 324 }, 325 326 { 0x131f, 0x1012, 0xffff, 0, 327 "SIIG Cyber I/O PCI 16C850 (10x family)", 328 DEFAULT_RCLK, 329 PUC_PORT_1S1P, 0x18, 4, 0, 330 }, 331 332 { 0x131f, 0x1021, 0xffff, 0, 333 "SIIG Cyber Parallel Dual PCI (10x family)", 334 0, 335 PUC_PORT_2P, 0x18, 8, 0, 336 }, 337 338 { 0x131f, 0x1030, 0xffff, 0, 339 "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 340 DEFAULT_RCLK, 341 PUC_PORT_2S, 0x18, 4, 0, 342 }, 343 344 { 0x131f, 0x1031, 0xffff, 0, 345 "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 346 DEFAULT_RCLK, 347 PUC_PORT_2S, 0x18, 4, 0, 348 }, 349 350 { 0x131f, 0x1032, 0xffff, 0, 351 "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 352 DEFAULT_RCLK, 353 PUC_PORT_2S, 0x18, 4, 0, 354 }, 355 356 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 357 "SIIG Cyber 2S1P PCI 16C550 (10x family)", 358 DEFAULT_RCLK, 359 PUC_PORT_2S1P, 0x18, 4, 0, 360 }, 361 362 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 363 "SIIG Cyber 2S1P PCI 16C650 (10x family)", 364 DEFAULT_RCLK, 365 PUC_PORT_2S1P, 0x18, 4, 0, 366 }, 367 368 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 369 "SIIG Cyber 2S1P PCI 16C850 (10x family)", 370 DEFAULT_RCLK, 371 PUC_PORT_2S1P, 0x18, 4, 0, 372 }, 373 374 { 0x131f, 0x1050, 0xffff, 0, 375 "SIIG Cyber 4S PCI 16C550 (10x family)", 376 DEFAULT_RCLK, 377 PUC_PORT_4S, 0x18, 4, 0, 378 }, 379 380 { 0x131f, 0x1051, 0xffff, 0, 381 "SIIG Cyber 4S PCI 16C650 (10x family)", 382 DEFAULT_RCLK, 383 PUC_PORT_4S, 0x18, 4, 0, 384 }, 385 386 { 0x131f, 0x1052, 0xffff, 0, 387 "SIIG Cyber 4S PCI 16C850 (10x family)", 388 DEFAULT_RCLK, 389 PUC_PORT_4S, 0x18, 4, 0, 390 }, 391 392 { 0x131f, 0x2010, 0xffff, 0, 393 "SIIG Cyber I/O PCI 16C550 (20x family)", 394 DEFAULT_RCLK, 395 PUC_PORT_1S1P, 0x10, 4, 0, 396 }, 397 398 { 0x131f, 0x2011, 0xffff, 0, 399 "SIIG Cyber I/O PCI 16C650 (20x family)", 400 DEFAULT_RCLK, 401 PUC_PORT_1S1P, 0x10, 4, 0, 402 }, 403 404 { 0x131f, 0x2012, 0xffff, 0, 405 "SIIG Cyber I/O PCI 16C850 (20x family)", 406 DEFAULT_RCLK, 407 PUC_PORT_1S1P, 0x10, 4, 0, 408 }, 409 410 { 0x131f, 0x2021, 0xffff, 0, 411 "SIIG Cyber Parallel Dual PCI (20x family)", 412 0, 413 PUC_PORT_2P, 0x10, 8, 0, 414 }, 415 416 { 0x131f, 0x2030, 0xffff, 0, 417 "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 418 DEFAULT_RCLK, 419 PUC_PORT_2S, 0x10, 4, 0, 420 }, 421 422 { 0x131f, 0x2031, 0xffff, 0, 423 "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 424 DEFAULT_RCLK, 425 PUC_PORT_2S, 0x10, 4, 0, 426 }, 427 428 { 0x131f, 0x2032, 0xffff, 0, 429 "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 430 DEFAULT_RCLK, 431 PUC_PORT_2S, 0x10, 4, 0, 432 }, 433 434 { 0x131f, 0x2040, 0xffff, 0, 435 "SIIG Cyber 2P1S PCI 16C550 (20x family)", 436 DEFAULT_RCLK, 437 PUC_PORT_1S2P, 0x10, -1, 0, 438 .config_function = puc_config_siig 439 }, 440 441 { 0x131f, 0x2041, 0xffff, 0, 442 "SIIG Cyber 2P1S PCI 16C650 (20x family)", 443 DEFAULT_RCLK, 444 PUC_PORT_1S2P, 0x10, -1, 0, 445 .config_function = puc_config_siig 446 }, 447 448 { 0x131f, 0x2042, 0xffff, 0, 449 "SIIG Cyber 2P1S PCI 16C850 (20x family)", 450 DEFAULT_RCLK, 451 PUC_PORT_1S2P, 0x10, -1, 0, 452 .config_function = puc_config_siig 453 }, 454 455 { 0x131f, 0x2050, 0xffff, 0, 456 "SIIG Cyber 4S PCI 16C550 (20x family)", 457 DEFAULT_RCLK, 458 PUC_PORT_4S, 0x10, 4, 0, 459 }, 460 461 { 0x131f, 0x2051, 0xffff, 0, 462 "SIIG Cyber 4S PCI 16C650 (20x family)", 463 DEFAULT_RCLK, 464 PUC_PORT_4S, 0x10, 4, 0, 465 }, 466 467 { 0x131f, 0x2052, 0xffff, 0, 468 "SIIG Cyber 4S PCI 16C850 (20x family)", 469 DEFAULT_RCLK, 470 PUC_PORT_4S, 0x10, 4, 0, 471 }, 472 473 { 0x131f, 0x2060, 0xffff, 0, 474 "SIIG Cyber 2S1P PCI 16C550 (20x family)", 475 DEFAULT_RCLK, 476 PUC_PORT_2S1P, 0x10, 4, 0, 477 }, 478 479 { 0x131f, 0x2061, 0xffff, 0, 480 "SIIG Cyber 2S1P PCI 16C650 (20x family)", 481 DEFAULT_RCLK, 482 PUC_PORT_2S1P, 0x10, 4, 0, 483 }, 484 485 { 0x131f, 0x2062, 0xffff, 0, 486 "SIIG Cyber 2S1P PCI 16C850 (20x family)", 487 DEFAULT_RCLK, 488 PUC_PORT_2S1P, 0x10, 4, 0, 489 }, 490 491 { 0x131f, 0x2081, 0xffff, 0, 492 "SIIG PS8000 8S PCI 16C650 (20x family)", 493 DEFAULT_RCLK, 494 PUC_PORT_8S, 0x10, -1, -1, 495 .config_function = puc_config_siig 496 }, 497 498 { 0x135a, 0x0841, 0xffff, 0, 499 "Brainboxes UC-268", 500 DEFAULT_RCLK, 501 PUC_PORT_4S, 0x18, 0, 8, 502 }, 503 504 { 0x135a, 0x0861, 0xffff, 0, 505 "Brainboxes UC-257", 506 DEFAULT_RCLK, 507 PUC_PORT_2S, 0x18, 0, 8, 508 }, 509 510 { 0x135a, 0x0862, 0xffff, 0, 511 "Brainboxes UC-257", 512 DEFAULT_RCLK, 513 PUC_PORT_2S, 0x18, 0, 8, 514 }, 515 516 { 0x135a, 0x0863, 0xffff, 0, 517 "Brainboxes UC-257", 518 DEFAULT_RCLK, 519 PUC_PORT_2S, 0x18, 0, 8, 520 }, 521 522 { 0x135a, 0x0881, 0xffff, 0, 523 "Brainboxes UC-279", 524 DEFAULT_RCLK, 525 PUC_PORT_8S, 0x18, 0, 8, 526 }, 527 528 { 0x135a, 0x08a1, 0xffff, 0, 529 "Brainboxes UC-313", 530 DEFAULT_RCLK, 531 PUC_PORT_2S, 0x18, 0, 8, 532 }, 533 534 { 0x135a, 0x08a2, 0xffff, 0, 535 "Brainboxes UC-313", 536 DEFAULT_RCLK, 537 PUC_PORT_2S, 0x18, 0, 8, 538 }, 539 540 { 0x135a, 0x08a3, 0xffff, 0, 541 "Brainboxes UC-313", 542 DEFAULT_RCLK, 543 PUC_PORT_2S, 0x18, 0, 8, 544 }, 545 546 { 0x135a, 0x08c1, 0xffff, 0, 547 "Brainboxes UC-310", 548 DEFAULT_RCLK, 549 PUC_PORT_2S, 0x18, 0, 8, 550 }, 551 552 { 0x135a, 0x08e1, 0xffff, 0, 553 "Brainboxes UC-302", 554 DEFAULT_RCLK, 555 PUC_PORT_2S, 0x18, 0, 8, 556 }, 557 558 { 0x135a, 0x08e2, 0xffff, 0, 559 "Brainboxes UC-302", 560 DEFAULT_RCLK, 561 PUC_PORT_2S, 0x18, 0, 8, 562 }, 563 564 { 0x135a, 0x08e3, 0xffff, 0, 565 "Brainboxes UC-302", 566 DEFAULT_RCLK, 567 PUC_PORT_2S, 0x18, 0, 8, 568 }, 569 570 { 0x135a, 0x0901, 0xffff, 0, 571 "Brainboxes UC-431", 572 DEFAULT_RCLK, 573 PUC_PORT_3S, 0x18, 0, 8, 574 }, 575 576 { 0x135a, 0x0921, 0xffff, 0, 577 "Brainboxes UC-420", 578 DEFAULT_RCLK, 579 PUC_PORT_4S, 0x18, 0, 8, 580 }, 581 582 { 0x135a, 0x0981, 0xffff, 0, 583 "Brainboxes UC-475", 584 DEFAULT_RCLK, 585 PUC_PORT_2S, 0x18, 0, 8, 586 }, 587 588 { 0x135a, 0x0982, 0xffff, 0, 589 "Brainboxes UC-475", 590 DEFAULT_RCLK, 591 PUC_PORT_2S, 0x18, 0, 8, 592 }, 593 594 { 0x135a, 0x09a1, 0xffff, 0, 595 "Brainboxes UC-607", 596 DEFAULT_RCLK, 597 PUC_PORT_2S, 0x18, 0, 8, 598 }, 599 600 { 0x135a, 0x09a2, 0xffff, 0, 601 "Brainboxes UC-607", 602 DEFAULT_RCLK, 603 PUC_PORT_2S, 0x18, 0, 8, 604 }, 605 606 { 0x135a, 0x09a3, 0xffff, 0, 607 "Brainboxes UC-607", 608 DEFAULT_RCLK, 609 PUC_PORT_2S, 0x18, 0, 8, 610 }, 611 612 { 0x135a, 0x0a81, 0xffff, 0, 613 "Brainboxes UC-357", 614 DEFAULT_RCLK, 615 PUC_PORT_2S, 0x18, 0, 8, 616 }, 617 618 { 0x135a, 0x0a82, 0xffff, 0, 619 "Brainboxes UC-357", 620 DEFAULT_RCLK, 621 PUC_PORT_2S, 0x18, 0, 8, 622 }, 623 624 { 0x135a, 0x0a83, 0xffff, 0, 625 "Brainboxes UC-357", 626 DEFAULT_RCLK, 627 PUC_PORT_2S, 0x18, 0, 8, 628 }, 629 630 { 0x135a, 0x0ac1, 0xffff, 0, 631 "Brainboxes UP-189", 632 DEFAULT_RCLK, 633 PUC_PORT_2S, 0x18, 0, 8, 634 }, 635 636 { 0x135a, 0x0ac2, 0xffff, 0, 637 "Brainboxes UP-189", 638 DEFAULT_RCLK, 639 PUC_PORT_2S, 0x18, 0, 8, 640 }, 641 642 { 0x135a, 0x0ac3, 0xffff, 0, 643 "Brainboxes UP-189", 644 DEFAULT_RCLK, 645 PUC_PORT_2S, 0x18, 0, 8, 646 }, 647 648 { 0x135a, 0x0b01, 0xffff, 0, 649 "Brainboxes UC-346", 650 DEFAULT_RCLK, 651 PUC_PORT_4S, 0x18, 0, 8, 652 }, 653 654 { 0x135a, 0x0b02, 0xffff, 0, 655 "Brainboxes UC-346", 656 DEFAULT_RCLK, 657 PUC_PORT_4S, 0x18, 0, 8, 658 }, 659 660 { 0x135a, 0x0b21, 0xffff, 0, 661 "Brainboxes UP-200", 662 DEFAULT_RCLK, 663 PUC_PORT_2S, 0x18, 0, 8, 664 }, 665 666 { 0x135a, 0x0b22, 0xffff, 0, 667 "Brainboxes UP-200", 668 DEFAULT_RCLK, 669 PUC_PORT_2S, 0x18, 0, 8, 670 }, 671 672 { 0x135a, 0x0b23, 0xffff, 0, 673 "Brainboxes UP-200", 674 DEFAULT_RCLK, 675 PUC_PORT_2S, 0x18, 0, 8, 676 }, 677 678 { 0x135a, 0x0ba1, 0xffff, 0, 679 "Brainboxes UC-101", 680 DEFAULT_RCLK, 681 PUC_PORT_2S, 0x18, 0, 8, 682 }, 683 684 { 0x135a, 0x0bc1, 0xffff, 0, 685 "Brainboxes UC-203", 686 DEFAULT_RCLK, 687 PUC_PORT_2S, 0x18, 0, 8, 688 }, 689 690 { 0x135a, 0x0bc2, 0xffff, 0, 691 "Brainboxes UC-203", 692 DEFAULT_RCLK, 693 PUC_PORT_2S, 0x18, 0, 8, 694 }, 695 696 { 0x135a, 0x0c01, 0xffff, 0, 697 "Brainboxes UP-869", 698 DEFAULT_RCLK, 699 PUC_PORT_2S, 0x18, 0, 8, 700 }, 701 702 { 0x135a, 0x0c02, 0xffff, 0, 703 "Brainboxes UP-869", 704 DEFAULT_RCLK, 705 PUC_PORT_2S, 0x18, 0, 8, 706 }, 707 708 { 0x135a, 0x0c03, 0xffff, 0, 709 "Brainboxes UP-869", 710 DEFAULT_RCLK, 711 PUC_PORT_2S, 0x18, 0, 8, 712 }, 713 714 { 0x135a, 0x0c21, 0xffff, 0, 715 "Brainboxes UP-880", 716 DEFAULT_RCLK, 717 PUC_PORT_2S, 0x18, 0, 8, 718 }, 719 720 { 0x135a, 0x0c22, 0xffff, 0, 721 "Brainboxes UP-880", 722 DEFAULT_RCLK, 723 PUC_PORT_2S, 0x18, 0, 8, 724 }, 725 726 { 0x135a, 0x0c23, 0xffff, 0, 727 "Brainboxes UP-880", 728 DEFAULT_RCLK, 729 PUC_PORT_2S, 0x18, 0, 8, 730 }, 731 732 { 0x135a, 0x0c41, 0xffff, 0, 733 "Brainboxes UC-368", 734 DEFAULT_RCLK, 735 PUC_PORT_4S, 0x18, 0, 8, 736 }, 737 738 { 0x135a, 0x0ca1, 0xffff, 0, 739 "Brainboxes UC-253", 740 DEFAULT_RCLK, 741 PUC_PORT_2S, 0x18, 0, 8, 742 }, 743 744 { 0x135a, 0x0d21, 0xffff, 0, 745 "Brainboxes UC-260", 746 DEFAULT_RCLK, 747 PUC_PORT_4S, 0x18, 0, 8, 748 }, 749 750 { 0x135a, 0x0d41, 0xffff, 0, 751 "Brainboxes UC-836", 752 DEFAULT_RCLK, 753 PUC_PORT_4S, 0x18, 0, 8, 754 }, 755 756 { 0x135a, 0x0d80, 0xffff, 0, 757 "Intashield IS-200", 758 DEFAULT_RCLK, 759 PUC_PORT_2S, 0x18, 0, 8, 760 }, 761 762 { 0x135a, 0x0dc0, 0xffff, 0, 763 "Intashield IS-400", 764 DEFAULT_RCLK, 765 PUC_PORT_4S, 0x18, 0, 8, 766 }, 767 768 { 0x135a, 0x0e41, 0xffff, 0, 769 "Brainboxes PX-279", 770 DEFAULT_RCLK, 771 PUC_PORT_8S, 0x18, 0, 8, 772 }, 773 774 { 0x135a, 0x0e61, 0xffff, 0, 775 "Brainboxes UC-414", 776 DEFAULT_RCLK, 777 PUC_PORT_4S, 0x18, 0, 8, 778 }, 779 780 { 0x135a, 0x400a, 0xffff, 0, 781 "Brainboxes PX-260", 782 DEFAULT_RCLK * 0x22, 783 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 784 .config_function = puc_config_oxford_pcie 785 }, 786 787 { 0x135a, 0x400b, 0xffff, 0, 788 "Brainboxes PX-320", 789 DEFAULT_RCLK * 0x22, 790 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 791 .config_function = puc_config_oxford_pcie 792 }, 793 794 { 0x135a, 0x400c, 0xffff, 0, 795 "Brainboxes PX-313", 796 DEFAULT_RCLK * 0x22, 797 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 798 .config_function = puc_config_oxford_pcie 799 }, 800 801 { 0x135a, 0x400e, 0xffff, 0, 802 "Brainboxes PX-310", 803 DEFAULT_RCLK * 0x22, 804 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 805 .config_function = puc_config_oxford_pcie 806 }, 807 808 { 0x135a, 0x400f, 0xffff, 0, 809 "Brainboxes PX-346", 810 DEFAULT_RCLK * 0x22, 811 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 812 .config_function = puc_config_oxford_pcie 813 }, 814 815 { 0x135a, 0x4010, 0xffff, 0, 816 "Brainboxes PX-368", 817 DEFAULT_RCLK * 0x22, 818 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 819 .config_function = puc_config_oxford_pcie 820 }, 821 822 { 0x135a, 0x4011, 0xffff, 0, 823 "Brainboxes PX-420", 824 DEFAULT_RCLK * 0x22, 825 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 826 .config_function = puc_config_oxford_pcie 827 }, 828 829 { 0x135a, 0x4012, 0xffff, 0, 830 "Brainboxes PX-431", 831 DEFAULT_RCLK * 0x22, 832 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 833 .config_function = puc_config_oxford_pcie 834 }, 835 836 { 0x135a, 0x4013, 0xffff, 0, 837 "Brainboxes PX-820", 838 DEFAULT_RCLK * 0x22, 839 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 840 .config_function = puc_config_oxford_pcie 841 }, 842 843 { 0x135a, 0x4014, 0xffff, 0, 844 "Brainboxes PX-831", 845 DEFAULT_RCLK * 0x22, 846 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 847 .config_function = puc_config_oxford_pcie 848 }, 849 850 { 0x135a, 0x4015, 0xffff, 0, 851 "Brainboxes PX-257", 852 DEFAULT_RCLK * 0x22, 853 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 854 .config_function = puc_config_oxford_pcie 855 }, 856 857 { 0x135a, 0x4016, 0xffff, 0, 858 "Brainboxes PX-246", 859 DEFAULT_RCLK * 0x22, 860 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 861 .config_function = puc_config_oxford_pcie 862 }, 863 864 { 0x135a, 0x4017, 0xffff, 0, 865 "Brainboxes PX-846", 866 DEFAULT_RCLK * 0x22, 867 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 868 .config_function = puc_config_oxford_pcie 869 }, 870 871 { 0x135a, 0x4018, 0xffff, 0, 872 "Brainboxes PX-857", 873 DEFAULT_RCLK * 0x22, 874 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 875 .config_function = puc_config_oxford_pcie 876 }, 877 878 { 0x135a, 0x4019, 0xffff, 0, 879 "Brainboxes PX-101", 880 DEFAULT_RCLK * 0x22, 881 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 882 .config_function = puc_config_oxford_pcie 883 }, 884 885 { 0x135a, 0x401d, 0xffff, 0, 886 "Brainboxes PX-475", 887 DEFAULT_RCLK * 0x22, 888 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 889 .config_function = puc_config_oxford_pcie 890 }, 891 892 { 0x135a, 0x401e, 0xffff, 0, 893 "Brainboxes PX-803", 894 DEFAULT_RCLK * 0x22, 895 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 896 .config_function = puc_config_oxford_pcie 897 }, 898 899 { 0x135a, 0x4027, 0xffff, 0, 900 "Intashield IX-100", 901 DEFAULT_RCLK * 0x22, 902 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 903 .config_function = puc_config_oxford_pcie 904 }, 905 906 { 0x135a, 0x4028, 0xffff, 0, 907 "Intashield IX-200", 908 DEFAULT_RCLK * 0x22, 909 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 910 .config_function = puc_config_oxford_pcie 911 }, 912 913 { 0x135a, 0x4029, 0xffff, 0, 914 "Intashield IX-400", 915 DEFAULT_RCLK * 0x22, 916 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 917 .config_function = puc_config_oxford_pcie 918 }, 919 920 { 0x135c, 0x0010, 0xffff, 0, 921 "Quatech QSC-100", 922 -3, /* max 8x clock rate */ 923 PUC_PORT_4S, 0x14, 0, 8, 924 .config_function = puc_config_quatech 925 }, 926 927 { 0x135c, 0x0020, 0xffff, 0, 928 "Quatech DSC-100", 929 -1, /* max 2x clock rate */ 930 PUC_PORT_2S, 0x14, 0, 8, 931 .config_function = puc_config_quatech 932 }, 933 934 { 0x135c, 0x0030, 0xffff, 0, 935 "Quatech DSC-200/300", 936 -1, /* max 2x clock rate */ 937 PUC_PORT_2S, 0x14, 0, 8, 938 .config_function = puc_config_quatech 939 }, 940 941 { 0x135c, 0x0040, 0xffff, 0, 942 "Quatech QSC-200/300", 943 -3, /* max 8x clock rate */ 944 PUC_PORT_4S, 0x14, 0, 8, 945 .config_function = puc_config_quatech 946 }, 947 948 { 0x135c, 0x0050, 0xffff, 0, 949 "Quatech ESC-100D", 950 -3, /* max 8x clock rate */ 951 PUC_PORT_8S, 0x14, 0, 8, 952 .config_function = puc_config_quatech 953 }, 954 955 { 0x135c, 0x0060, 0xffff, 0, 956 "Quatech ESC-100M", 957 -3, /* max 8x clock rate */ 958 PUC_PORT_8S, 0x14, 0, 8, 959 .config_function = puc_config_quatech 960 }, 961 962 { 0x135c, 0x0170, 0xffff, 0, 963 "Quatech QSCLP-100", 964 -1, /* max 2x clock rate */ 965 PUC_PORT_4S, 0x18, 0, 8, 966 .config_function = puc_config_quatech 967 }, 968 969 { 0x135c, 0x0180, 0xffff, 0, 970 "Quatech DSCLP-100", 971 -1, /* max 3x clock rate */ 972 PUC_PORT_2S, 0x18, 0, 8, 973 .config_function = puc_config_quatech 974 }, 975 976 { 0x135c, 0x01b0, 0xffff, 0, 977 "Quatech DSCLP-200/300", 978 -1, /* max 2x clock rate */ 979 PUC_PORT_2S, 0x18, 0, 8, 980 .config_function = puc_config_quatech 981 }, 982 983 { 0x135c, 0x01e0, 0xffff, 0, 984 "Quatech ESCLP-100", 985 -3, /* max 8x clock rate */ 986 PUC_PORT_8S, 0x10, 0, 8, 987 .config_function = puc_config_quatech 988 }, 989 990 { 0x1393, 0x1024, 0xffff, 0, 991 "Moxa Technologies, Smartio CP-102E/PCIe", 992 DEFAULT_RCLK * 8, 993 PUC_PORT_2S, 0x14, 0, -1, 994 .config_function = puc_config_moxa 995 }, 996 997 { 0x1393, 0x1025, 0xffff, 0, 998 "Moxa Technologies, Smartio CP-102EL/PCIe", 999 DEFAULT_RCLK * 8, 1000 PUC_PORT_2S, 0x14, 0, -1, 1001 .config_function = puc_config_moxa 1002 }, 1003 1004 { 0x1393, 0x1040, 0xffff, 0, 1005 "Moxa Technologies, Smartio C104H/PCI", 1006 DEFAULT_RCLK * 8, 1007 PUC_PORT_4S, 0x18, 0, 8, 1008 }, 1009 1010 { 0x1393, 0x1041, 0xffff, 0, 1011 "Moxa Technologies, Smartio CP-104UL/PCI", 1012 DEFAULT_RCLK * 8, 1013 PUC_PORT_4S, 0x18, 0, 8, 1014 }, 1015 1016 { 0x1393, 0x1042, 0xffff, 0, 1017 "Moxa Technologies, Smartio CP-104JU/PCI", 1018 DEFAULT_RCLK * 8, 1019 PUC_PORT_4S, 0x18, 0, 8, 1020 }, 1021 1022 { 0x1393, 0x1043, 0xffff, 0, 1023 "Moxa Technologies, Smartio CP-104EL/PCIe", 1024 DEFAULT_RCLK * 8, 1025 PUC_PORT_4S, 0x18, 0, 8, 1026 }, 1027 1028 { 0x1393, 0x1045, 0xffff, 0, 1029 "Moxa Technologies, Smartio CP-104EL-A/PCIe", 1030 DEFAULT_RCLK * 8, 1031 PUC_PORT_4S, 0x14, 0, -1, 1032 .config_function = puc_config_moxa 1033 }, 1034 1035 { 0x1393, 0x1120, 0xffff, 0, 1036 "Moxa Technologies, CP-112UL", 1037 DEFAULT_RCLK * 8, 1038 PUC_PORT_2S, 0x18, 0, 8, 1039 }, 1040 1041 { 0x1393, 0x1141, 0xffff, 0, 1042 "Moxa Technologies, Industio CP-114", 1043 DEFAULT_RCLK * 8, 1044 PUC_PORT_4S, 0x18, 0, 8, 1045 }, 1046 1047 { 0x1393, 0x1144, 0xffff, 0, 1048 "Moxa Technologies, Smartio CP-114EL/PCIe", 1049 DEFAULT_RCLK * 8, 1050 PUC_PORT_4S, 0x14, 0, -1, 1051 .config_function = puc_config_moxa 1052 }, 1053 1054 { 0x1393, 0x1182, 0xffff, 0, 1055 "Moxa Technologies, Smartio CP-118EL-A/PCIe", 1056 DEFAULT_RCLK * 8, 1057 PUC_PORT_8S, 0x14, 0, -1, 1058 .config_function = puc_config_moxa 1059 }, 1060 1061 { 0x1393, 0x1680, 0xffff, 0, 1062 "Moxa Technologies, C168H/PCI", 1063 DEFAULT_RCLK * 8, 1064 PUC_PORT_8S, 0x18, 0, 8, 1065 }, 1066 1067 { 0x1393, 0x1681, 0xffff, 0, 1068 "Moxa Technologies, C168U/PCI", 1069 DEFAULT_RCLK * 8, 1070 PUC_PORT_8S, 0x18, 0, 8, 1071 }, 1072 1073 { 0x1393, 0x1682, 0xffff, 0, 1074 "Moxa Technologies, CP-168EL/PCIe", 1075 DEFAULT_RCLK * 8, 1076 PUC_PORT_8S, 0x18, 0, 8, 1077 }, 1078 1079 { 0x1393, 0x1683, 0xffff, 0, 1080 "Moxa Technologies, Smartio CP-168EL-A/PCIe", 1081 DEFAULT_RCLK * 8, 1082 PUC_PORT_8S, 0x14, 0, -1, 1083 .config_function = puc_config_moxa 1084 }, 1085 1086 { 0x13a8, 0x0152, 0xffff, 0, 1087 "Exar XR17C/D152", 1088 DEFAULT_RCLK * 8, 1089 PUC_PORT_2S, 0x10, 0, -1, 1090 .config_function = puc_config_exar 1091 }, 1092 1093 { 0x13a8, 0x0154, 0xffff, 0, 1094 "Exar XR17C154", 1095 DEFAULT_RCLK * 8, 1096 PUC_PORT_4S, 0x10, 0, -1, 1097 .config_function = puc_config_exar 1098 }, 1099 1100 { 0x13a8, 0x0158, 0xffff, 0, 1101 "Exar XR17C158", 1102 DEFAULT_RCLK * 8, 1103 PUC_PORT_8S, 0x10, 0, -1, 1104 .config_function = puc_config_exar 1105 }, 1106 1107 { 0x13a8, 0x0258, 0xffff, 0, 1108 "Exar XR17V258IV", 1109 DEFAULT_RCLK * 8, 1110 PUC_PORT_8S, 0x10, 0, -1, 1111 .config_function = puc_config_exar 1112 }, 1113 1114 { 0x13a8, 0x0352, 0xffff, 0, 1115 "Exar XR17V352", 1116 125000000, 1117 PUC_PORT_2S, 0x10, 0, -1, 1118 .config_function = puc_config_exar_pcie 1119 }, 1120 1121 { 0x13a8, 0x0354, 0xffff, 0, 1122 "Exar XR17V354", 1123 125000000, 1124 PUC_PORT_4S, 0x10, 0, -1, 1125 .config_function = puc_config_exar_pcie 1126 }, 1127 1128 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 1129 { 0x13a8, 0x0358, 0xffff, 0, 1130 "Exar XR17V358", 1131 125000000, 1132 PUC_PORT_8S, 0x10, 0, -1, 1133 .config_function = puc_config_exar_pcie 1134 }, 1135 1136 /* 1137 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford 1138 * Semiconductor OXuPCI954. Note these boards have a hardware bug in 1139 * that they drive the RS-422/485 transmitters after power-on until a 1140 * driver initializes the UARTs. 1141 */ 1142 { 0x13fe, 0x1600, 0x1602, 0x0002, 1143 "Advantech PCI-1602 Rev. A", 1144 DEFAULT_RCLK * 8, 1145 PUC_PORT_2S, 0x10, 0, 8, 1146 .config_function = puc_config_advantech 1147 }, 1148 1149 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */ 1150 { 0x13fe, 0xa102, 0x13fe, 0xa102, 1151 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)", 1152 DEFAULT_RCLK * 8, 1153 PUC_PORT_2S, 0x10, 4, 0, 1154 .config_function = puc_config_advantech 1155 }, 1156 1157 { 0x1407, 0x0100, 0xffff, 0, 1158 "Lava Computers Dual Serial", 1159 DEFAULT_RCLK, 1160 PUC_PORT_2S, 0x10, 4, 0, 1161 }, 1162 1163 { 0x1407, 0x0101, 0xffff, 0, 1164 "Lava Computers Quatro A", 1165 DEFAULT_RCLK, 1166 PUC_PORT_2S, 0x10, 4, 0, 1167 }, 1168 1169 { 0x1407, 0x0102, 0xffff, 0, 1170 "Lava Computers Quatro B", 1171 DEFAULT_RCLK, 1172 PUC_PORT_2S, 0x10, 4, 0, 1173 }, 1174 1175 { 0x1407, 0x0120, 0xffff, 0, 1176 "Lava Computers Quattro-PCI A", 1177 DEFAULT_RCLK, 1178 PUC_PORT_2S, 0x10, 4, 0, 1179 }, 1180 1181 { 0x1407, 0x0121, 0xffff, 0, 1182 "Lava Computers Quattro-PCI B", 1183 DEFAULT_RCLK, 1184 PUC_PORT_2S, 0x10, 4, 0, 1185 }, 1186 1187 { 0x1407, 0x0180, 0xffff, 0, 1188 "Lava Computers Octo A", 1189 DEFAULT_RCLK, 1190 PUC_PORT_4S, 0x10, 4, 0, 1191 }, 1192 1193 { 0x1407, 0x0181, 0xffff, 0, 1194 "Lava Computers Octo B", 1195 DEFAULT_RCLK, 1196 PUC_PORT_4S, 0x10, 4, 0, 1197 }, 1198 1199 { 0x1409, 0x7268, 0xffff, 0, 1200 "Sunix SUN1888", 1201 0, 1202 PUC_PORT_2P, 0x10, 0, 8, 1203 }, 1204 1205 { 0x1409, 0x7168, 0xffff, 0, 1206 NULL, 1207 DEFAULT_RCLK * 8, 1208 PUC_PORT_NONSTANDARD, 0x10, -1, -1, 1209 .config_function = puc_config_timedia 1210 }, 1211 1212 /* 1213 * Boards with an Oxford Semiconductor chip. 1214 * 1215 * Oxford Semiconductor provides documentation for their chip at: 1216 * <URL:http://www.plxtech.com/products/uart/> 1217 * 1218 * As sold by Kouwell <URL:http://www.kouwell.com/>. 1219 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 1220 */ 1221 { 1222 0x1415, 0x9501, 0x10fc, 0xc070, 1223 "I-O DATA RSA-PCI2/R", 1224 DEFAULT_RCLK * 8, 1225 PUC_PORT_2S, 0x10, 0, 8, 1226 }, 1227 1228 { 0x1415, 0x9501, 0x131f, 0x2050, 1229 "SIIG Cyber 4 PCI 16550", 1230 DEFAULT_RCLK * 10, 1231 PUC_PORT_4S, 0x10, 0, 8, 1232 }, 1233 1234 { 0x1415, 0x9501, 0x131f, 0x2051, 1235 "SIIG Cyber 4S PCI 16C650 (20x family)", 1236 DEFAULT_RCLK * 10, 1237 PUC_PORT_4S, 0x10, 0, 8, 1238 }, 1239 1240 { 0x1415, 0x9501, 0x131f, 0x2052, 1241 "SIIG Quartet Serial 850", 1242 DEFAULT_RCLK * 10, 1243 PUC_PORT_4S, 0x10, 0, 8, 1244 }, 1245 1246 { 0x1415, 0x9501, 0x14db, 0x2150, 1247 "Kuroutoshikou SERIAL4P-LPPCI2", 1248 DEFAULT_RCLK * 10, 1249 PUC_PORT_4S, 0x10, 0, 8, 1250 }, 1251 1252 { 0x1415, 0x9501, 0xffff, 0, 1253 "Oxford Semiconductor OX16PCI954 UARTs", 1254 0, 1255 PUC_PORT_4S, 0x10, 0, 8, 1256 .config_function = puc_config_oxford_pci954 1257 }, 1258 1259 { 0x1415, 0x950a, 0x131f, 0x2030, 1260 "SIIG Cyber 2S PCIe", 1261 DEFAULT_RCLK * 10, 1262 PUC_PORT_2S, 0x10, 0, 8, 1263 }, 1264 1265 { 0x1415, 0x950a, 0x131f, 0x2032, 1266 "SIIG Cyber Serial Dual PCI 16C850", 1267 DEFAULT_RCLK * 10, 1268 PUC_PORT_4S, 0x10, 0, 8, 1269 }, 1270 1271 { 0x1415, 0x950a, 0x131f, 0x2061, 1272 "SIIG Cyber 2SP1 PCIe", 1273 DEFAULT_RCLK * 10, 1274 PUC_PORT_2S, 0x10, 0, 8, 1275 }, 1276 1277 { 0x1415, 0x950a, 0xffff, 0, 1278 "Oxford Semiconductor OX16PCI954 UARTs", 1279 DEFAULT_RCLK, 1280 PUC_PORT_4S, 0x10, 0, 8, 1281 }, 1282 1283 { 0x1415, 0x9511, 0xffff, 0, 1284 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 1285 DEFAULT_RCLK, 1286 PUC_PORT_4S, 0x10, 0, 8, 1287 }, 1288 1289 { 0x1415, 0x9521, 0xffff, 0, 1290 "Oxford Semiconductor OX16PCI952 UARTs", 1291 DEFAULT_RCLK, 1292 PUC_PORT_2S, 0x10, 4, 0, 1293 }, 1294 1295 { 0x1415, 0x9538, 0xffff, 0, 1296 "Oxford Semiconductor OX16PCI958 UARTs", 1297 DEFAULT_RCLK, 1298 PUC_PORT_8S, 0x18, 0, 8, 1299 }, 1300 1301 /* 1302 * Perle boards use Oxford Semiconductor chips, but they store the 1303 * Oxford Semiconductor device ID as a subvendor device ID and use 1304 * their own device IDs. 1305 */ 1306 1307 { 0x155f, 0x0331, 0xffff, 0, 1308 "Perle Ultraport4 Express", 1309 DEFAULT_RCLK * 8, 1310 PUC_PORT_4S, 0x10, 0, 8, 1311 }, 1312 1313 { 0x155f, 0xB012, 0xffff, 0, 1314 "Perle Speed2 LE", 1315 DEFAULT_RCLK * 8, 1316 PUC_PORT_2S, 0x10, 0, 8, 1317 }, 1318 1319 { 0x155f, 0xB022, 0xffff, 0, 1320 "Perle Speed2 LE", 1321 DEFAULT_RCLK * 8, 1322 PUC_PORT_2S, 0x10, 0, 8, 1323 }, 1324 1325 { 0x155f, 0xB004, 0xffff, 0, 1326 "Perle Speed4 LE", 1327 DEFAULT_RCLK * 8, 1328 PUC_PORT_4S, 0x10, 0, 8, 1329 }, 1330 1331 { 0x155f, 0xB008, 0xffff, 0, 1332 "Perle Speed8 LE", 1333 DEFAULT_RCLK * 8, 1334 PUC_PORT_8S, 0x10, 0, 8, 1335 }, 1336 1337 /* 1338 * Oxford Semiconductor PCI Express Expresso family 1339 * 1340 * Found in many 'native' PCI Express serial boards such as: 1341 * 1342 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 1343 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 1344 * 1345 * Lindy 51189 (4 port) 1346 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 1347 * 1348 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 1349 * <URL:http://www.startech.com> 1350 */ 1351 1352 { 0x1415, 0xc11b, 0xffff, 0, 1353 "Oxford Semiconductor OXPCIe952 1S1P", 1354 DEFAULT_RCLK * 0x22, 1355 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1356 .config_function = puc_config_oxford_pcie 1357 }, 1358 1359 { 0x1415, 0xc138, 0xffff, 0, 1360 "Oxford Semiconductor OXPCIe952 UARTs", 1361 DEFAULT_RCLK * 0x22, 1362 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1363 .config_function = puc_config_oxford_pcie 1364 }, 1365 1366 { 0x1415, 0xc158, 0xffff, 0, 1367 "Oxford Semiconductor OXPCIe952 UARTs", 1368 DEFAULT_RCLK * 0x22, 1369 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1370 .config_function = puc_config_oxford_pcie 1371 }, 1372 1373 { 0x1415, 0xc15d, 0xffff, 0, 1374 "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 1375 DEFAULT_RCLK * 0x22, 1376 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1377 .config_function = puc_config_oxford_pcie 1378 }, 1379 1380 { 0x1415, 0xc208, 0xffff, 0, 1381 "Oxford Semiconductor OXPCIe954 UARTs", 1382 DEFAULT_RCLK * 0x22, 1383 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1384 .config_function = puc_config_oxford_pcie 1385 }, 1386 1387 { 0x1415, 0xc20d, 0xffff, 0, 1388 "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 1389 DEFAULT_RCLK * 0x22, 1390 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1391 .config_function = puc_config_oxford_pcie 1392 }, 1393 1394 { 0x1415, 0xc308, 0xffff, 0, 1395 "Oxford Semiconductor OXPCIe958 UARTs", 1396 DEFAULT_RCLK * 0x22, 1397 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1398 .config_function = puc_config_oxford_pcie 1399 }, 1400 1401 { 0x1415, 0xc30d, 0xffff, 0, 1402 "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 1403 DEFAULT_RCLK * 0x22, 1404 PUC_PORT_NONSTANDARD, 0x10, 0, -1, 1405 .config_function = puc_config_oxford_pcie 1406 }, 1407 1408 { 0x14d2, 0x8010, 0xffff, 0, 1409 "VScom PCI-100L", 1410 DEFAULT_RCLK * 8, 1411 PUC_PORT_1S, 0x14, 0, 0, 1412 }, 1413 1414 { 0x14d2, 0x8020, 0xffff, 0, 1415 "VScom PCI-200L", 1416 DEFAULT_RCLK * 8, 1417 PUC_PORT_2S, 0x14, 4, 0, 1418 }, 1419 1420 { 0x14d2, 0x8028, 0xffff, 0, 1421 "VScom 200Li", 1422 DEFAULT_RCLK, 1423 PUC_PORT_2S, 0x20, 0, 8, 1424 }, 1425 1426 /* 1427 * VScom (Titan?) PCI-800L. More modern variant of the 1428 * PCI-800. Uses 6 discrete 16550 UARTs, plus another 1429 * two of them obviously implemented as macro cells in 1430 * the ASIC. This causes the weird port access pattern 1431 * below, where two of the IO port ranges each access 1432 * one of the ASIC UARTs, and a block of IO addresses 1433 * access the external UARTs. 1434 */ 1435 { 0x14d2, 0x8080, 0xffff, 0, 1436 "Titan VScom PCI-800L", 1437 DEFAULT_RCLK * 8, 1438 PUC_PORT_8S, 0x14, -1, -1, 1439 .config_function = puc_config_titan 1440 }, 1441 1442 /* 1443 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 1444 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 1445 * device ID 3 and PCI device 1 device ID 4. 1446 */ 1447 { 0x14d2, 0xa003, 0xffff, 0, 1448 "Titan PCI-800H", 1449 DEFAULT_RCLK * 8, 1450 PUC_PORT_4S, 0x10, 0, 8, 1451 }, 1452 1453 { 0x14d2, 0xa004, 0xffff, 0, 1454 "Titan PCI-800H", 1455 DEFAULT_RCLK * 8, 1456 PUC_PORT_4S, 0x10, 0, 8, 1457 }, 1458 1459 { 0x14d2, 0xa005, 0xffff, 0, 1460 "Titan PCI-200H", 1461 DEFAULT_RCLK * 8, 1462 PUC_PORT_2S, 0x10, 0, 8, 1463 }, 1464 1465 { 0x14d2, 0xe020, 0xffff, 0, 1466 "Titan VScom PCI-200HV2", 1467 DEFAULT_RCLK * 8, 1468 PUC_PORT_2S, 0x10, 4, 0, 1469 }, 1470 1471 { 0x14d2, 0xa007, 0xffff, 0, 1472 "Titan VScom PCIex-800H", 1473 DEFAULT_RCLK * 8, 1474 PUC_PORT_4S, 0x10, 0, 8, 1475 }, 1476 1477 { 0x14d2, 0xa008, 0xffff, 0, 1478 "Titan VScom PCIex-800H", 1479 DEFAULT_RCLK * 8, 1480 PUC_PORT_4S, 0x10, 0, 8, 1481 }, 1482 1483 { 0x14db, 0x2130, 0xffff, 0, 1484 "Avlab Technology, PCI IO 2S", 1485 DEFAULT_RCLK, 1486 PUC_PORT_2S, 0x10, 4, 0, 1487 }, 1488 1489 { 0x14db, 0x2150, 0xffff, 0, 1490 "Avlab Low Profile PCI 4 Serial", 1491 DEFAULT_RCLK, 1492 PUC_PORT_4S, 0x10, 4, 0, 1493 }, 1494 1495 { 0x14db, 0x2152, 0xffff, 0, 1496 "Avlab Low Profile PCI 4 Serial", 1497 DEFAULT_RCLK, 1498 PUC_PORT_4S, 0x10, 4, 0, 1499 }, 1500 1501 { 0x1592, 0x0781, 0xffff, 0, 1502 "Syba Tech Ltd. PCI-4S2P-550-ECP", 1503 DEFAULT_RCLK, 1504 PUC_PORT_4S1P, 0x10, 0, -1, 1505 .config_function = puc_config_syba 1506 }, 1507 1508 { 0x1c00, 0x3253, 0xffff, 0, 1509 "WCH CH382 2S PCIe Dual Port Serial", 1510 DEFAULT_RCLK, 1511 PUC_PORT_2S, 0x10, 0, -1, 1512 .flags = PUC_FLAGS_NO_MSI, 1513 .config_function = puc_config_wch_ch38x 1514 }, 1515 1516 { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 1517 "Sunix SER5xxxx 2-port serial", 1518 DEFAULT_RCLK * 8, 1519 PUC_PORT_2S, 0x10, 0, 8, 1520 }, 1521 1522 { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1523 "Sunix SER5xxxx 4-port serial", 1524 DEFAULT_RCLK * 8, 1525 PUC_PORT_4S, 0x10, 0, 8, 1526 }, 1527 1528 { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1529 "Sunix SER5xxxx 8-port serial", 1530 DEFAULT_RCLK * 8, 1531 PUC_PORT_8S, -1, -1, -1, 1532 .config_function = puc_config_sunix 1533 }, 1534 1535 { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1536 "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1537 DEFAULT_RCLK * 8, 1538 PUC_PORT_1S1P, -1, -1, -1, 1539 .config_function = puc_config_sunix 1540 }, 1541 1542 { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1543 "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1544 DEFAULT_RCLK * 8, 1545 PUC_PORT_2S1P, -1, -1, -1, 1546 .config_function = puc_config_sunix 1547 }, 1548 1549 { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1550 "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1551 DEFAULT_RCLK * 8, 1552 PUC_PORT_4S1P, -1, -1, -1, 1553 .config_function = puc_config_sunix 1554 }, 1555 1556 { 0x5372, 0x6872, 0xffff, 0, 1557 "Feasso PCI FPP-02 2S1P", 1558 DEFAULT_RCLK, 1559 PUC_PORT_2S1P, 0x10, 4, 0, 1560 }, 1561 1562 { 0x5372, 0x6873, 0xffff, 0, 1563 "Sun 1040 PCI Quad Serial", 1564 DEFAULT_RCLK, 1565 PUC_PORT_4S, 0x10, 4, 0, 1566 }, 1567 1568 { 0x6666, 0x0001, 0xffff, 0, 1569 "Decision Computer Inc, PCCOM 4-port serial", 1570 DEFAULT_RCLK, 1571 PUC_PORT_4S, 0x1c, 0, 8, 1572 }, 1573 1574 { 0x6666, 0x0002, 0xffff, 0, 1575 "Decision Computer Inc, PCCOM 8-port serial", 1576 DEFAULT_RCLK, 1577 PUC_PORT_8S, 0x1c, 0, 8, 1578 }, 1579 1580 { 0x6666, 0x0004, 0xffff, 0, 1581 "PCCOM dual port RS232/422/485", 1582 DEFAULT_RCLK, 1583 PUC_PORT_2S, 0x1c, 0, 8, 1584 }, 1585 1586 { 0x9710, 0x9815, 0xffff, 0, 1587 "NetMos NM9815 Dual 1284 Printer port", 1588 0, 1589 PUC_PORT_2P, 0x10, 8, 0, 1590 }, 1591 1592 /* 1593 * This is more specific than the generic NM9835 entry, and is placed 1594 * here to _prevent_ puc(4) from claiming this single port card. 1595 * 1596 * uart(4) will claim this device. 1597 */ 1598 { 0x9710, 0x9835, 0x1000, 1, 1599 "NetMos NM9835 based 1-port serial", 1600 DEFAULT_RCLK, 1601 PUC_PORT_1S, 0x10, 4, 0, 1602 }, 1603 1604 { 0x9710, 0x9835, 0x1000, 2, 1605 "NetMos NM9835 based 2-port serial", 1606 DEFAULT_RCLK, 1607 PUC_PORT_2S, 0x10, 4, 0, 1608 }, 1609 1610 { 0x9710, 0x9835, 0xffff, 0, 1611 "NetMos NM9835 Dual UART and 1284 Printer port", 1612 DEFAULT_RCLK, 1613 PUC_PORT_2S1P, 0x10, 4, 0, 1614 }, 1615 1616 { 0x9710, 0x9845, 0x1000, 0x0006, 1617 "NetMos NM9845 6 Port UART", 1618 DEFAULT_RCLK, 1619 PUC_PORT_6S, 0x10, 4, 0, 1620 }, 1621 1622 { 0x9710, 0x9845, 0xffff, 0, 1623 "NetMos NM9845 Quad UART and 1284 Printer port", 1624 DEFAULT_RCLK, 1625 PUC_PORT_4S1P, 0x10, 4, 0, 1626 }, 1627 1628 { 0x9710, 0x9865, 0xa000, 0x3002, 1629 "NetMos NM9865 Dual UART", 1630 DEFAULT_RCLK, 1631 PUC_PORT_2S, 0x10, 4, 0, 1632 }, 1633 1634 { 0x9710, 0x9865, 0xa000, 0x3003, 1635 "NetMos NM9865 Triple UART", 1636 DEFAULT_RCLK, 1637 PUC_PORT_3S, 0x10, 4, 0, 1638 }, 1639 1640 { 0x9710, 0x9865, 0xa000, 0x3004, 1641 "NetMos NM9865 Quad UART", 1642 DEFAULT_RCLK, 1643 PUC_PORT_4S, 0x10, 4, 0, 1644 }, 1645 1646 { 0x9710, 0x9865, 0xa000, 0x3011, 1647 "NetMos NM9865 Single UART and 1284 Printer port", 1648 DEFAULT_RCLK, 1649 PUC_PORT_1S1P, 0x10, 4, 0, 1650 }, 1651 1652 { 0x9710, 0x9865, 0xa000, 0x3012, 1653 "NetMos NM9865 Dual UART and 1284 Printer port", 1654 DEFAULT_RCLK, 1655 PUC_PORT_2S1P, 0x10, 4, 0, 1656 }, 1657 1658 { 0x9710, 0x9865, 0xa000, 0x3020, 1659 "NetMos NM9865 Dual 1284 Printer port", 1660 DEFAULT_RCLK, 1661 PUC_PORT_2P, 0x10, 4, 0, 1662 }, 1663 1664 { 0xb00c, 0x021c, 0xffff, 0, 1665 "IC Book Labs Gunboat x4 Lite", 1666 DEFAULT_RCLK, 1667 PUC_PORT_4S, 0x10, 0, 8, 1668 .config_function = puc_config_icbook 1669 }, 1670 1671 { 0xb00c, 0x031c, 0xffff, 0, 1672 "IC Book Labs Gunboat x4 Pro", 1673 DEFAULT_RCLK, 1674 PUC_PORT_4S, 0x10, 0, 8, 1675 .config_function = puc_config_icbook 1676 }, 1677 1678 { 0xb00c, 0x041c, 0xffff, 0, 1679 "IC Book Labs Ironclad x8 Lite", 1680 DEFAULT_RCLK, 1681 PUC_PORT_8S, 0x10, 0, 8, 1682 .config_function = puc_config_icbook 1683 }, 1684 1685 { 0xb00c, 0x051c, 0xffff, 0, 1686 "IC Book Labs Ironclad x8 Pro", 1687 DEFAULT_RCLK, 1688 PUC_PORT_8S, 0x10, 0, 8, 1689 .config_function = puc_config_icbook 1690 }, 1691 1692 { 0xb00c, 0x081c, 0xffff, 0, 1693 "IC Book Labs Dreadnought x16 Pro", 1694 DEFAULT_RCLK * 8, 1695 PUC_PORT_16S, 0x10, 0, 8, 1696 .config_function = puc_config_icbook 1697 }, 1698 1699 { 0xb00c, 0x091c, 0xffff, 0, 1700 "IC Book Labs Dreadnought x16 Lite", 1701 DEFAULT_RCLK, 1702 PUC_PORT_16S, 0x10, 0, 8, 1703 .config_function = puc_config_icbook 1704 }, 1705 1706 { 0xb00c, 0x0a1c, 0xffff, 0, 1707 "IC Book Labs Gunboat x2 Low Profile", 1708 DEFAULT_RCLK, 1709 PUC_PORT_2S, 0x10, 0, 8, 1710 }, 1711 1712 { 0xb00c, 0x0b1c, 0xffff, 0, 1713 "IC Book Labs Gunboat x4 Low Profile", 1714 DEFAULT_RCLK, 1715 PUC_PORT_4S, 0x10, 0, 8, 1716 .config_function = puc_config_icbook 1717 }, 1718 1719 /* 1720 * Systembase cards using SB16C1050 UARTs: 1721 */ 1722 { 0x14a1, 0x0008, 0x14a1, 0x0008, 1723 "Systembase SB16C1058", 1724 DEFAULT_RCLK * 8, 1725 PUC_PORT_8S, 0x10, 0, 8, 1726 .config_function = puc_config_systembase, 1727 }, 1728 { 0x14a1, 0x0004, 0x14a1, 0x0004, 1729 "Systembase SB16C1054", 1730 DEFAULT_RCLK * 8, 1731 PUC_PORT_4S, 0x10, 0, 8, 1732 .config_function = puc_config_systembase, 1733 }, 1734 1735 { 0xffff, 0, 0xffff, 0, NULL, 0 } 1736 }; 1737 1738 static int 1739 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1740 intptr_t *res __unused) 1741 { 1742 const struct puc_cfg *cfg; 1743 struct resource *cres; 1744 struct puc_bar *bar; 1745 device_t cdev, dev; 1746 bus_size_t off; 1747 int base, crtype, fixed, high, i, oxpcie; 1748 uint8_t acr, func, mask; 1749 1750 if (cmd != PUC_CFG_SETUP) 1751 return (ENXIO); 1752 1753 base = fixed = oxpcie = 0; 1754 crtype = SYS_RES_IOPORT; 1755 acr = mask = 0x0; 1756 func = high = 1; 1757 off = 0x60; 1758 1759 cfg = sc->sc_cfg; 1760 switch (cfg->subvendor) { 1761 case 0x13fe: 1762 switch (cfg->device) { 1763 case 0xa102: 1764 high = 0; 1765 break; 1766 default: 1767 break; 1768 } 1769 default: 1770 break; 1771 } 1772 if (fixed == 1) 1773 goto setup; 1774 1775 dev = sc->sc_dev; 1776 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1777 pci_get_slot(dev), func); 1778 if (cdev == NULL) { 1779 device_printf(dev, "could not find config function\n"); 1780 return (ENXIO); 1781 } 1782 1783 i = PCIR_BAR(0); 1784 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE); 1785 if (cres == NULL) { 1786 device_printf(dev, "could not allocate config resource\n"); 1787 return (ENXIO); 1788 } 1789 1790 if (oxpcie == 0) { 1791 mask = bus_read_1(cres, off); 1792 if (pci_get_function(dev) == 1) 1793 base = 4; 1794 } 1795 1796 setup: 1797 for (i = 0; i < sc->sc_nports; ++i) { 1798 device_printf(dev, "port %d: ", i); 1799 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); 1800 if (bar == NULL) { 1801 printf("could not get BAR\n"); 1802 continue; 1803 } 1804 1805 if (fixed == 0) { 1806 if ((mask & (1 << (base + i))) == 0) { 1807 acr = 0; 1808 printf("RS-232\n"); 1809 } else { 1810 acr = (high == 1 ? 0x18 : 0x10); 1811 printf("RS-422/RS-485, active-%s auto-DTR\n", 1812 high == 1 ? "high" : "low"); 1813 } 1814 } 1815 1816 bus_write_1(bar->b_res, REG_SPR, REG_ACR); 1817 bus_write_1(bar->b_res, REG_ICR, acr); 1818 } 1819 1820 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres); 1821 return (0); 1822 } 1823 1824 static int 1825 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port, 1826 intptr_t *res) 1827 { 1828 1829 switch (cmd) { 1830 case PUC_CFG_GET_OFS: 1831 *res = 8 * (port & 1); 1832 return (0); 1833 case PUC_CFG_GET_RID: 1834 *res = 0x14 + (port >> 1) * 4; 1835 return (0); 1836 default: 1837 break; 1838 } 1839 return (ENXIO); 1840 } 1841 1842 static int 1843 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1844 intptr_t *res) 1845 { 1846 const struct puc_cfg *cfg = sc->sc_cfg; 1847 1848 if (cmd == PUC_CFG_GET_OFS) { 1849 if (cfg->subdevice == 0x1282) /* Everest SP */ 1850 port <<= 1; 1851 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1852 port = (port == 3) ? 4 : port; 1853 *res = port * 8 + ((port > 2) ? 0x18 : 0); 1854 return (0); 1855 } 1856 return (ENXIO); 1857 } 1858 1859 static int 1860 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1861 int port, intptr_t *res) 1862 { 1863 1864 if (cmd == PUC_CFG_GET_OFS) { 1865 *res = port * 0x200; 1866 return (0); 1867 } 1868 return (ENXIO); 1869 } 1870 1871 static int 1872 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1873 int port, intptr_t *res) 1874 { 1875 1876 if (cmd == PUC_CFG_GET_OFS) { 1877 *res = port * 0x400; 1878 return (0); 1879 } 1880 return (ENXIO); 1881 } 1882 1883 static int 1884 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1885 int port __unused, intptr_t *res) 1886 { 1887 1888 if (cmd == PUC_CFG_GET_ILR) { 1889 *res = PUC_ILR_DIGI; 1890 return (0); 1891 } 1892 return (ENXIO); 1893 } 1894 1895 static int 1896 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1897 intptr_t *res) 1898 { 1899 const struct puc_cfg *cfg = sc->sc_cfg; 1900 1901 if (cmd == PUC_CFG_GET_OFS) { 1902 if (port == 3 && (cfg->device == 0x1045 || 1903 cfg->device == 0x1144)) 1904 port = 7; 1905 *res = port * 0x200; 1906 1907 return 0; 1908 } 1909 return (ENXIO); 1910 } 1911 1912 static int 1913 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1914 int port __unused, intptr_t *res) 1915 { 1916 const struct puc_cfg *cfg = sc->sc_cfg; 1917 struct puc_bar *bar; 1918 uint8_t v0, v1; 1919 1920 switch (cmd) { 1921 case PUC_CFG_SETUP: 1922 /* 1923 * Check if the scratchpad register is enabled or if the 1924 * interrupt status and options registers are active. 1925 */ 1926 bar = puc_get_bar(sc, cfg->rid); 1927 if (bar == NULL) 1928 return (ENXIO); 1929 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); 1930 bus_write_1(bar->b_res, REG_SPR, 0); 1931 v0 = bus_read_1(bar->b_res, REG_SPR); 1932 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); 1933 v1 = bus_read_1(bar->b_res, REG_SPR); 1934 bus_write_1(bar->b_res, REG_LCR, 0); 1935 sc->sc_cfg_data = (v0 << 8) | v1; 1936 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1937 /* 1938 * The SPR register echoed the two values written 1939 * by us. This means that the SPAD jumper is set. 1940 */ 1941 device_printf(sc->sc_dev, "warning: extra features " 1942 "not usable -- SPAD compatibility enabled\n"); 1943 return (0); 1944 } 1945 if (v0 != 0) { 1946 /* 1947 * The first value doesn't match. This can only mean 1948 * that the SPAD jumper is not set and that a non- 1949 * standard fixed clock multiplier jumper is set. 1950 */ 1951 if (bootverbose) 1952 device_printf(sc->sc_dev, "fixed clock rate " 1953 "multiplier of %d\n", 1 << v0); 1954 if (v0 < -cfg->clock) 1955 device_printf(sc->sc_dev, "warning: " 1956 "suboptimal fixed clock rate multiplier " 1957 "setting\n"); 1958 return (0); 1959 } 1960 /* 1961 * The first value matched, but the second didn't. We know 1962 * that the SPAD jumper is not set. We also know that the 1963 * clock rate multiplier is software controlled *and* that 1964 * we just programmed it to the maximum allowed. 1965 */ 1966 if (bootverbose) 1967 device_printf(sc->sc_dev, "clock rate multiplier of " 1968 "%d selected\n", 1 << -cfg->clock); 1969 return (0); 1970 case PUC_CFG_GET_CLOCK: 1971 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1972 v1 = sc->sc_cfg_data & 0xff; 1973 if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1974 /* 1975 * XXX With the SPAD jumper applied, there's no 1976 * easy way of knowing if there's also a clock 1977 * rate multiplier jumper installed. Let's hope 1978 * not ... 1979 */ 1980 *res = DEFAULT_RCLK; 1981 } else if (v0 == 0) { 1982 /* 1983 * No clock rate multiplier jumper installed, 1984 * so we programmed the board with the maximum 1985 * multiplier allowed as given to us in the 1986 * clock field of the config record (negated). 1987 */ 1988 *res = DEFAULT_RCLK << -cfg->clock; 1989 } else 1990 *res = DEFAULT_RCLK << v0; 1991 return (0); 1992 case PUC_CFG_GET_ILR: 1993 v0 = (sc->sc_cfg_data >> 8) & 0xff; 1994 v1 = sc->sc_cfg_data & 0xff; 1995 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? 1996 PUC_ILR_NONE : PUC_ILR_QUATECH; 1997 return (0); 1998 default: 1999 break; 2000 } 2001 return (ENXIO); 2002 } 2003 2004 static int 2005 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 2006 intptr_t *res) 2007 { 2008 static int base[] = { 0x251, 0x3f0, 0 }; 2009 const struct puc_cfg *cfg = sc->sc_cfg; 2010 struct puc_bar *bar; 2011 int efir, idx, ofs; 2012 uint8_t v; 2013 2014 switch (cmd) { 2015 case PUC_CFG_SETUP: 2016 bar = puc_get_bar(sc, cfg->rid); 2017 if (bar == NULL) 2018 return (ENXIO); 2019 2020 /* configure both W83877TFs */ 2021 bus_write_1(bar->b_res, 0x250, 0x89); 2022 bus_write_1(bar->b_res, 0x3f0, 0x87); 2023 bus_write_1(bar->b_res, 0x3f0, 0x87); 2024 idx = 0; 2025 while (base[idx] != 0) { 2026 efir = base[idx]; 2027 bus_write_1(bar->b_res, efir, 0x09); 2028 v = bus_read_1(bar->b_res, efir + 1); 2029 if ((v & 0x0f) != 0x0c) 2030 return (ENXIO); 2031 bus_write_1(bar->b_res, efir, 0x16); 2032 v = bus_read_1(bar->b_res, efir + 1); 2033 bus_write_1(bar->b_res, efir, 0x16); 2034 bus_write_1(bar->b_res, efir + 1, v | 0x04); 2035 bus_write_1(bar->b_res, efir, 0x16); 2036 bus_write_1(bar->b_res, efir + 1, v & ~0x04); 2037 ofs = base[idx] & 0x300; 2038 bus_write_1(bar->b_res, efir, 0x23); 2039 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 2040 bus_write_1(bar->b_res, efir, 0x24); 2041 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 2042 bus_write_1(bar->b_res, efir, 0x25); 2043 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 2044 bus_write_1(bar->b_res, efir, 0x17); 2045 bus_write_1(bar->b_res, efir + 1, 0x03); 2046 bus_write_1(bar->b_res, efir, 0x28); 2047 bus_write_1(bar->b_res, efir + 1, 0x43); 2048 idx++; 2049 } 2050 bus_write_1(bar->b_res, 0x250, 0xaa); 2051 bus_write_1(bar->b_res, 0x3f0, 0xaa); 2052 return (0); 2053 case PUC_CFG_GET_OFS: 2054 switch (port) { 2055 case 0: 2056 *res = 0x2f8; 2057 return (0); 2058 case 1: 2059 *res = 0x2e8; 2060 return (0); 2061 case 2: 2062 *res = 0x3f8; 2063 return (0); 2064 case 3: 2065 *res = 0x3e8; 2066 return (0); 2067 case 4: 2068 *res = 0x278; 2069 return (0); 2070 } 2071 break; 2072 default: 2073 break; 2074 } 2075 return (ENXIO); 2076 } 2077 2078 static int 2079 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 2080 intptr_t *res) 2081 { 2082 const struct puc_cfg *cfg = sc->sc_cfg; 2083 2084 switch (cmd) { 2085 case PUC_CFG_GET_OFS: 2086 if (cfg->ports == PUC_PORT_8S) { 2087 *res = (port > 4) ? 8 * (port - 4) : 0; 2088 return (0); 2089 } 2090 break; 2091 case PUC_CFG_GET_RID: 2092 if (cfg->ports == PUC_PORT_8S) { 2093 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 2094 return (0); 2095 } 2096 if (cfg->ports == PUC_PORT_2S1P) { 2097 switch (port) { 2098 case 0: *res = 0x10; return (0); 2099 case 1: *res = 0x14; return (0); 2100 case 2: *res = 0x1c; return (0); 2101 } 2102 } 2103 break; 2104 default: 2105 break; 2106 } 2107 return (ENXIO); 2108 } 2109 2110 static int 2111 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 2112 intptr_t *res) 2113 { 2114 static const uint16_t dual[] = { 2115 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 2116 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 2117 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 2118 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 2119 0xD079, 0 2120 }; 2121 static const uint16_t quad[] = { 2122 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 2123 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 2124 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 2125 0xB157, 0 2126 }; 2127 static const uint16_t octa[] = { 2128 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 2129 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 2130 }; 2131 static const struct { 2132 int ports; 2133 const uint16_t *ids; 2134 } subdevs[] = { 2135 { 2, dual }, 2136 { 4, quad }, 2137 { 8, octa }, 2138 { 0, NULL } 2139 }; 2140 static char desc[64]; 2141 int dev, id; 2142 uint16_t subdev; 2143 2144 switch (cmd) { 2145 case PUC_CFG_GET_CLOCK: 2146 if (port < 2) 2147 *res = DEFAULT_RCLK * 8; 2148 else 2149 *res = DEFAULT_RCLK; 2150 return (0); 2151 case PUC_CFG_GET_DESC: 2152 snprintf(desc, sizeof(desc), 2153 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 2154 *res = (intptr_t)desc; 2155 return (0); 2156 case PUC_CFG_GET_NPORTS: 2157 subdev = pci_get_subdevice(sc->sc_dev); 2158 dev = 0; 2159 while (subdevs[dev].ports != 0) { 2160 id = 0; 2161 while (subdevs[dev].ids[id] != 0) { 2162 if (subdev == subdevs[dev].ids[id]) { 2163 sc->sc_cfg_data = subdevs[dev].ports; 2164 *res = sc->sc_cfg_data; 2165 return (0); 2166 } 2167 id++; 2168 } 2169 dev++; 2170 } 2171 return (ENXIO); 2172 case PUC_CFG_GET_OFS: 2173 *res = (port == 1 || port == 3) ? 8 : 0; 2174 return (0); 2175 case PUC_CFG_GET_RID: 2176 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 2177 return (0); 2178 case PUC_CFG_GET_TYPE: 2179 *res = PUC_TYPE_SERIAL; 2180 return (0); 2181 default: 2182 break; 2183 } 2184 return (ENXIO); 2185 } 2186 2187 static int 2188 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 2189 int port __unused, intptr_t *res) 2190 { 2191 2192 switch (cmd) { 2193 case PUC_CFG_GET_CLOCK: 2194 /* 2195 * OXu16PCI954 use a 14.7456 MHz clock by default while 2196 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 2197 */ 2198 if (pci_get_revid(sc->sc_dev) == 1) 2199 *res = DEFAULT_RCLK * 8; 2200 else 2201 *res = DEFAULT_RCLK; 2202 return (0); 2203 default: 2204 break; 2205 } 2206 return (ENXIO); 2207 } 2208 2209 static int 2210 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 2211 intptr_t *res) 2212 { 2213 const struct puc_cfg *cfg = sc->sc_cfg; 2214 int idx; 2215 struct puc_bar *bar; 2216 uint8_t value; 2217 2218 switch (cmd) { 2219 case PUC_CFG_SETUP: 2220 device_printf(sc->sc_dev, "%d UARTs detected\n", 2221 sc->sc_nports); 2222 2223 /* Set UARTs to enhanced mode */ 2224 bar = puc_get_bar(sc, cfg->rid); 2225 if (bar == NULL) 2226 return (ENXIO); 2227 for (idx = 0; idx < sc->sc_nports; idx++) { 2228 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 2229 0x92); 2230 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 2231 value | 0x10); 2232 } 2233 return (0); 2234 case PUC_CFG_GET_LEN: 2235 *res = 0x200; 2236 return (0); 2237 case PUC_CFG_GET_NPORTS: 2238 /* 2239 * Check if we are being called from puc_bfe_attach() 2240 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 2241 * puc_get_bar(), so we return a value of 16. This has 2242 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, 2243 * sc->sc_cfg_data will not contain the true number of 2244 * ports in PUC_CFG_GET_DESC, but we are not implementing 2245 * that call for this device family anyway. 2246 * 2247 * The check is for initialization of sc->sc_bar[idx], 2248 * which is only done in puc_bfe_attach(). 2249 */ 2250 idx = 0; 2251 do { 2252 if (sc->sc_bar[idx++].b_rid != -1) { 2253 sc->sc_cfg_data = 16; 2254 *res = sc->sc_cfg_data; 2255 return (0); 2256 } 2257 } while (idx < PUC_PCI_BARS); 2258 2259 bar = puc_get_bar(sc, cfg->rid); 2260 if (bar == NULL) 2261 return (ENXIO); 2262 2263 value = bus_read_1(bar->b_res, 0x04); 2264 if (value == 0) 2265 return (ENXIO); 2266 2267 sc->sc_cfg_data = value; 2268 *res = sc->sc_cfg_data; 2269 return (0); 2270 case PUC_CFG_GET_OFS: 2271 *res = 0x1000 + (port << 9); 2272 return (0); 2273 case PUC_CFG_GET_TYPE: 2274 *res = PUC_TYPE_SERIAL; 2275 return (0); 2276 default: 2277 break; 2278 } 2279 return (ENXIO); 2280 } 2281 2282 static int 2283 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 2284 intptr_t *res) 2285 { 2286 int error; 2287 2288 switch (cmd) { 2289 case PUC_CFG_GET_OFS: 2290 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 2291 if (error != 0) 2292 return (error); 2293 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 2294 return (0); 2295 case PUC_CFG_GET_RID: 2296 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 2297 if (error != 0) 2298 return (error); 2299 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 2300 return (0); 2301 default: 2302 break; 2303 } 2304 return (ENXIO); 2305 } 2306 2307 static int 2308 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 2309 int port, intptr_t *res) 2310 { 2311 2312 switch (cmd) { 2313 case PUC_CFG_GET_OFS: 2314 *res = (port < 3) ? 0 : (port - 2) << 3; 2315 return (0); 2316 case PUC_CFG_GET_RID: 2317 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 2318 return (0); 2319 default: 2320 break; 2321 } 2322 return (ENXIO); 2323 } 2324 2325 static int 2326 puc_config_systembase(struct puc_softc *sc __unused, 2327 enum puc_cfg_cmd cmd, int port, intptr_t *res) 2328 { 2329 struct puc_bar *bar; 2330 2331 switch (cmd) { 2332 case PUC_CFG_SETUP: 2333 bar = puc_get_bar(sc, 0x14); 2334 if (bar == NULL) 2335 return (ENXIO); 2336 2337 /* 2338 * The Systembase SB16C1058 (and probably other devices 2339 * based on the SB16C1050 UART core) require poking a 2340 * register in the *other* RID to turn on interrupts. 2341 */ 2342 bus_write_1(bar->b_res, /* OPT_IMRREG0 */ 0xc, 0xff); 2343 return (0); 2344 default: 2345 break; 2346 } 2347 return (ENXIO); 2348 } 2349 2350 static int 2351 puc_config_wch_ch38x(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 2352 int port, intptr_t *res) 2353 { 2354 if (cmd == PUC_CFG_GET_OFS) { 2355 *res = 0xc0 + (port * 8); 2356 return (0); 2357 } 2358 return (ENXIO); 2359 } 2360