1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2015 Andrew Turner 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory (Department of Computer Science and 9 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 10 * DARPA SSITH research programme. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34#include <machine/asm.h> 35__FBSDID("$FreeBSD$"); 36 37.arch_extension sec /* For smc */ 38.arch_extension virt /* For hvc */ 39 40.macro arm_smccc_1_0 insn 41ENTRY(arm_smccc_\insn) 42 mov r12, sp 43 push {r4-r7} 44 ldm r12, {r4-r7} 45 \insn #0 46 pop {r4-r7} 47 ldr r12, [sp, #(4 * 4)] 48 cmp r12, #0 49 beq 1f 50 stm r12, {r0-r3} 511: bx lr 52END(arm_smccc_\insn) 53.endm 54 55/* 56 * int arm_smccc_hvc(register_t, register_t, register_t, register_t, 57 * register_t, register_t, register_t, register_t, 58 * struct arm_smccc_res *res) 59 */ 60arm_smccc_1_0 hvc 61arm_smccc_1_0 smc 62