1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997-2000 Nicolas Souchu 5 * Copyright (c) 2001 Alcove - Nicolas Souchu 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ppc.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/interrupt.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/rman.h> 49 50 #ifdef __i386__ 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <machine/vmparam.h> 54 #endif 55 56 #include <dev/ppbus/ppbconf.h> 57 #include <dev/ppbus/ppb_msq.h> 58 59 #include <dev/ppc/ppcvar.h> 60 #include <dev/ppc/ppcreg.h> 61 62 #include "ppbus_if.h" 63 64 static void ppcintr(void *arg); 65 66 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 67 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 68 69 #define LOG_PPC(function, ppc, string) \ 70 if (bootverbose) printf("%s: %s\n", function, string) 71 72 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 73 74 /* 75 * We use critical enter/exit for the simple config locking needed to 76 * detect the devices. We just want to make sure that both of our writes 77 * happen without someone else also writing to those config registers. Since 78 * we just do this at startup, Giant keeps multiple threads from executing, 79 * and critical_enter() then is all that's needed to keep us from being preempted 80 * during the critical sequences with the hardware. 81 * 82 * Note: this doesn't prevent multiple threads from putting the chips into 83 * config mode, but since we only do that to detect the type at startup the 84 * extra overhead isn't needed since Giant protects us from multiple entry 85 * and no other code changes these registers. 86 */ 87 #define PPC_CONFIG_LOCK(ppc) critical_enter() 88 #define PPC_CONFIG_UNLOCK(ppc) critical_exit() 89 90 devclass_t ppc_devclass; 91 const char ppc_driver_name[] = "ppc"; 92 93 static char *ppc_models[] = { 94 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 95 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 96 "SMC FDC37C935", "PC87303", 0 97 }; 98 99 /* list of available modes */ 100 static char *ppc_avms[] = { 101 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 102 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 103 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 104 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 105 }; 106 107 /* list of current executing modes 108 * Note that few modes do not actually exist. 109 */ 110 static char *ppc_modes[] = { 111 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 112 "EPP", "EPP", "EPP", "ECP", 113 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 114 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 115 }; 116 117 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 118 119 #ifdef __i386__ 120 /* 121 * BIOS printer list - used by BIOS probe. 122 */ 123 #define BIOS_PPC_PORTS 0x408 124 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 125 #define BIOS_MAX_PPC 4 126 #endif 127 128 /* 129 * ppc_ecp_sync() XXX 130 */ 131 int 132 ppc_ecp_sync(device_t dev) 133 { 134 int i, r; 135 struct ppc_data *ppc = DEVTOSOFTC(dev); 136 137 PPC_ASSERT_LOCKED(ppc); 138 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 139 return 0; 140 141 r = r_ecr(ppc); 142 if ((r & 0xe0) != PPC_ECR_EPP) 143 return 0; 144 145 for (i = 0; i < 100; i++) { 146 r = r_ecr(ppc); 147 if (r & 0x1) 148 return 0; 149 DELAY(100); 150 } 151 152 device_printf(dev, "ECP sync failed as data still present in FIFO.\n"); 153 154 return 0; 155 } 156 157 /* 158 * ppc_detect_fifo() 159 * 160 * Detect parallel port FIFO 161 */ 162 static int 163 ppc_detect_fifo(struct ppc_data *ppc) 164 { 165 char ecr_sav; 166 char ctr_sav, ctr, cc; 167 short i; 168 169 /* save registers */ 170 ecr_sav = r_ecr(ppc); 171 ctr_sav = r_ctr(ppc); 172 173 /* enter ECP configuration mode, no interrupt, no DMA */ 174 w_ecr(ppc, 0xf4); 175 176 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 177 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 178 179 /* XXX 16 and 32 bits implementations not supported */ 180 if (ppc->ppc_pword != PPC_PWORD_8) { 181 LOG_PPC(__func__, ppc, "PWord not supported"); 182 goto error; 183 } 184 185 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 186 ctr = r_ctr(ppc); 187 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 188 189 /* enter ECP test mode, no interrupt, no DMA */ 190 w_ecr(ppc, 0xd4); 191 192 /* flush the FIFO */ 193 for (i=0; i<1024; i++) { 194 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 195 break; 196 cc = r_fifo(ppc); 197 } 198 199 if (i >= 1024) { 200 LOG_PPC(__func__, ppc, "can't flush FIFO"); 201 goto error; 202 } 203 204 /* enable interrupts, no DMA */ 205 w_ecr(ppc, 0xd0); 206 207 /* determine readIntrThreshold 208 * fill the FIFO until serviceIntr is set 209 */ 210 for (i=0; i<1024; i++) { 211 w_fifo(ppc, (char)i); 212 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 213 /* readThreshold reached */ 214 ppc->ppc_rthr = i+1; 215 } 216 if (r_ecr(ppc) & PPC_FIFO_FULL) { 217 ppc->ppc_fifo = i+1; 218 break; 219 } 220 } 221 222 if (i >= 1024) { 223 LOG_PPC(__func__, ppc, "can't fill FIFO"); 224 goto error; 225 } 226 227 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 228 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 229 w_ecr(ppc, 0xd0); /* enable interrupts */ 230 231 /* determine writeIntrThreshold 232 * empty the FIFO until serviceIntr is set 233 */ 234 for (i=ppc->ppc_fifo; i>0; i--) { 235 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 236 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 237 goto error; 238 } 239 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 240 /* writeIntrThreshold reached */ 241 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 242 } 243 /* if FIFO empty before the last byte, error */ 244 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 245 LOG_PPC(__func__, ppc, "data lost in FIFO"); 246 goto error; 247 } 248 } 249 250 /* FIFO must be empty after the last byte */ 251 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 252 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 253 goto error; 254 } 255 256 w_ctr(ppc, ctr_sav); 257 w_ecr(ppc, ecr_sav); 258 259 return (0); 260 261 error: 262 w_ctr(ppc, ctr_sav); 263 w_ecr(ppc, ecr_sav); 264 265 return (EINVAL); 266 } 267 268 static int 269 ppc_detect_port(struct ppc_data *ppc) 270 { 271 272 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 273 w_dtr(ppc, 0xaa); 274 if (r_dtr(ppc) != 0xaa) 275 return (0); 276 277 return (1); 278 } 279 280 /* 281 * EPP timeout, according to the PC87332 manual 282 * Semantics of clearing EPP timeout bit. 283 * PC87332 - reading SPP_STR does it... 284 * SMC - write 1 to EPP timeout bit XXX 285 * Others - (?) write 0 to EPP timeout bit 286 */ 287 static void 288 ppc_reset_epp_timeout(struct ppc_data *ppc) 289 { 290 char r; 291 292 r = r_str(ppc); 293 w_str(ppc, r | 0x1); 294 w_str(ppc, r & 0xfe); 295 296 return; 297 } 298 299 static int 300 ppc_check_epp_timeout(struct ppc_data *ppc) 301 { 302 ppc_reset_epp_timeout(ppc); 303 304 return (!(r_str(ppc) & TIMEOUT)); 305 } 306 307 /* 308 * Configure current operating mode 309 */ 310 static int 311 ppc_generic_setmode(struct ppc_data *ppc, int mode) 312 { 313 u_char ecr = 0; 314 315 /* check if mode is available */ 316 if (mode && !(ppc->ppc_avm & mode)) 317 return (EINVAL); 318 319 /* if ECP mode, configure ecr register */ 320 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 321 /* return to byte mode (keeping direction bit), 322 * no interrupt, no DMA to be able to change to 323 * ECP 324 */ 325 w_ecr(ppc, PPC_ECR_RESET); 326 ecr = PPC_DISABLE_INTR; 327 328 if (mode & PPB_EPP) 329 return (EINVAL); 330 else if (mode & PPB_ECP) 331 /* select ECP mode */ 332 ecr |= PPC_ECR_ECP; 333 else if (mode & PPB_PS2) 334 /* select PS2 mode with ECP */ 335 ecr |= PPC_ECR_PS2; 336 else 337 /* select COMPATIBLE/NIBBLE mode */ 338 ecr |= PPC_ECR_STD; 339 340 w_ecr(ppc, ecr); 341 } 342 343 ppc->ppc_mode = mode; 344 345 return (0); 346 } 347 348 /* 349 * The ppc driver is free to choose options like FIFO or DMA 350 * if ECP mode is available. 351 * 352 * The 'RAW' option allows the upper drivers to force the ppc mode 353 * even with FIFO, DMA available. 354 */ 355 static int 356 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 357 { 358 u_char ecr = 0; 359 360 /* check if mode is available */ 361 if (mode && !(ppc->ppc_avm & mode)) 362 return (EINVAL); 363 364 /* if ECP mode, configure ecr register */ 365 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 366 /* return to byte mode (keeping direction bit), 367 * no interrupt, no DMA to be able to change to 368 * ECP or EPP mode 369 */ 370 w_ecr(ppc, PPC_ECR_RESET); 371 ecr = PPC_DISABLE_INTR; 372 373 if (mode & PPB_EPP) 374 /* select EPP mode */ 375 ecr |= PPC_ECR_EPP; 376 else if (mode & PPB_ECP) 377 /* select ECP mode */ 378 ecr |= PPC_ECR_ECP; 379 else if (mode & PPB_PS2) 380 /* select PS2 mode with ECP */ 381 ecr |= PPC_ECR_PS2; 382 else 383 /* select COMPATIBLE/NIBBLE mode */ 384 ecr |= PPC_ECR_STD; 385 386 w_ecr(ppc, ecr); 387 } 388 389 ppc->ppc_mode = mode; 390 391 return (0); 392 } 393 394 #ifdef PPC_PROBE_CHIPSET 395 /* 396 * ppc_pc873xx_detect 397 * 398 * Probe for a Natsemi PC873xx-family part. 399 * 400 * References in this function are to the National Semiconductor 401 * PC87332 datasheet TL/C/11930, May 1995 revision. 402 */ 403 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 404 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 405 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 406 407 static int pc873xx_regstab[] = { 408 PC873_FER, PC873_FAR, PC873_PTR, 409 PC873_FCR, PC873_PCR, PC873_PMC, 410 PC873_TUP, PC873_SID, PC873_PNP0, 411 PC873_PNP1, PC873_LPTBA, -1 412 }; 413 414 static char *pc873xx_rnametab[] = { 415 "FER", "FAR", "PTR", "FCR", "PCR", 416 "PMC", "TUP", "SID", "PNP0", "PNP1", 417 "LPTBA", NULL 418 }; 419 420 static int 421 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 422 { 423 static int index = 0; 424 int idport, irq; 425 int ptr, pcr, val, i; 426 427 while ((idport = pc873xx_basetab[index++])) { 428 429 /* XXX should check first to see if this location is already claimed */ 430 431 /* 432 * Pull the 873xx through the power-on ID cycle (2.2,1.). 433 * We can't use this to locate the chip as it may already have 434 * been used by the BIOS. 435 */ 436 (void)inb(idport); (void)inb(idport); 437 (void)inb(idport); (void)inb(idport); 438 439 /* 440 * Read the SID byte. Possible values are : 441 * 442 * 01010xxx PC87334 443 * 0001xxxx PC87332 444 * 01110xxx PC87306 445 * 00110xxx PC87303 446 */ 447 outb(idport, PC873_SID); 448 val = inb(idport + 1); 449 if ((val & 0xf0) == 0x10) { 450 ppc->ppc_model = NS_PC87332; 451 } else if ((val & 0xf8) == 0x70) { 452 ppc->ppc_model = NS_PC87306; 453 } else if ((val & 0xf8) == 0x50) { 454 ppc->ppc_model = NS_PC87334; 455 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 456 documentation, but probing 457 yielded 0x40... */ 458 ppc->ppc_model = NS_PC87303; 459 } else { 460 if (bootverbose && (val != 0xff)) 461 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 462 continue ; /* not recognised */ 463 } 464 465 /* print registers */ 466 if (bootverbose) { 467 printf("PC873xx"); 468 for (i=0; pc873xx_regstab[i] != -1; i++) { 469 outb(idport, pc873xx_regstab[i]); 470 printf(" %s=0x%x", pc873xx_rnametab[i], 471 inb(idport + 1) & 0xff); 472 } 473 printf("\n"); 474 } 475 476 /* 477 * We think we have one. Is it enabled and where we want it to be? 478 */ 479 outb(idport, PC873_FER); 480 val = inb(idport + 1); 481 if (!(val & PC873_PPENABLE)) { 482 if (bootverbose) 483 printf("PC873xx parallel port disabled\n"); 484 continue; 485 } 486 outb(idport, PC873_FAR); 487 val = inb(idport + 1); 488 /* XXX we should create a driver instance for every port found */ 489 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 490 491 /* First try to change the port address to that requested... */ 492 493 switch (ppc->ppc_base) { 494 case 0x378: 495 val &= 0xfc; 496 break; 497 498 case 0x3bc: 499 val &= 0xfd; 500 break; 501 502 case 0x278: 503 val &= 0xfe; 504 break; 505 506 default: 507 val &= 0xfd; 508 break; 509 } 510 511 outb(idport, PC873_FAR); 512 outb(idport + 1, val); 513 outb(idport + 1, val); 514 515 /* Check for success by reading back the value we supposedly 516 wrote and comparing...*/ 517 518 outb(idport, PC873_FAR); 519 val = inb(idport + 1) & 0x3; 520 521 /* If we fail, report the failure... */ 522 523 if (pc873xx_porttab[val] != ppc->ppc_base) { 524 if (bootverbose) 525 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 526 pc873xx_porttab[val], ppc->ppc_base); 527 } 528 continue; 529 } 530 531 outb(idport, PC873_PTR); 532 ptr = inb(idport + 1); 533 534 /* get irq settings */ 535 if (ppc->ppc_base == 0x378) 536 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 537 else 538 irq = pc873xx_irqtab[val]; 539 540 if (bootverbose) 541 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 542 543 /* 544 * Check if irq settings are correct 545 */ 546 if (irq != ppc->ppc_irq) { 547 /* 548 * If the chipset is not locked and base address is 0x378, 549 * we have another chance 550 */ 551 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 552 if (ppc->ppc_irq == 7) { 553 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 554 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 555 } else { 556 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 557 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 558 } 559 if (bootverbose) 560 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 561 } else { 562 if (bootverbose) 563 printf("PC873xx sorry, can't change irq setting\n"); 564 } 565 } else { 566 if (bootverbose) 567 printf("PC873xx irq settings are correct\n"); 568 } 569 570 outb(idport, PC873_PCR); 571 pcr = inb(idport + 1); 572 573 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 574 if (bootverbose) 575 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 576 577 ppc->ppc_avm |= PPB_NIBBLE; 578 if (bootverbose) 579 printf(", NIBBLE"); 580 581 if (pcr & PC873_EPPEN) { 582 ppc->ppc_avm |= PPB_EPP; 583 584 if (bootverbose) 585 printf(", EPP"); 586 587 if (pcr & PC873_EPP19) 588 ppc->ppc_epp = EPP_1_9; 589 else 590 ppc->ppc_epp = EPP_1_7; 591 592 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 593 outb(idport, PC873_PTR); 594 ptr = inb(idport + 1); 595 if (ptr & PC873_EPPRDIR) 596 printf(", Regular mode"); 597 else 598 printf(", Automatic mode"); 599 } 600 } else if (pcr & PC873_ECPEN) { 601 ppc->ppc_avm |= PPB_ECP; 602 if (bootverbose) 603 printf(", ECP"); 604 605 if (pcr & PC873_ECPCLK) { /* XXX */ 606 ppc->ppc_avm |= PPB_PS2; 607 if (bootverbose) 608 printf(", PS/2"); 609 } 610 } else { 611 outb(idport, PC873_PTR); 612 ptr = inb(idport + 1); 613 if (ptr & PC873_EXTENDED) { 614 ppc->ppc_avm |= PPB_SPP; 615 if (bootverbose) 616 printf(", SPP"); 617 } 618 } 619 } else { 620 if (bootverbose) 621 printf("PC873xx unlocked"); 622 623 if (chipset_mode & PPB_ECP) { 624 if ((chipset_mode & PPB_EPP) && bootverbose) 625 printf(", ECP+EPP not supported"); 626 627 pcr &= ~PC873_EPPEN; 628 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 629 outb(idport + 1, pcr); 630 outb(idport + 1, pcr); 631 632 if (bootverbose) 633 printf(", ECP"); 634 635 } else if (chipset_mode & PPB_EPP) { 636 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 637 pcr |= (PC873_EPPEN | PC873_EPP19); 638 outb(idport + 1, pcr); 639 outb(idport + 1, pcr); 640 641 ppc->ppc_epp = EPP_1_9; /* XXX */ 642 643 if (bootverbose) 644 printf(", EPP1.9"); 645 646 /* enable automatic direction turnover */ 647 if (ppc->ppc_model == NS_PC87332) { 648 outb(idport, PC873_PTR); 649 ptr = inb(idport + 1); 650 ptr &= ~PC873_EPPRDIR; 651 outb(idport + 1, ptr); 652 outb(idport + 1, ptr); 653 654 if (bootverbose) 655 printf(", Automatic mode"); 656 } 657 } else { 658 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 659 outb(idport + 1, pcr); 660 outb(idport + 1, pcr); 661 662 /* configure extended bit in PTR */ 663 outb(idport, PC873_PTR); 664 ptr = inb(idport + 1); 665 666 if (chipset_mode & PPB_PS2) { 667 ptr |= PC873_EXTENDED; 668 669 if (bootverbose) 670 printf(", PS/2"); 671 672 } else { 673 /* default to NIBBLE mode */ 674 ptr &= ~PC873_EXTENDED; 675 676 if (bootverbose) 677 printf(", NIBBLE"); 678 } 679 outb(idport + 1, ptr); 680 outb(idport + 1, ptr); 681 } 682 683 ppc->ppc_avm = chipset_mode; 684 } 685 686 if (bootverbose) 687 printf("\n"); 688 689 ppc->ppc_type = PPC_TYPE_GENERIC; 690 ppc_generic_setmode(ppc, chipset_mode); 691 692 return(chipset_mode); 693 } 694 return(-1); 695 } 696 697 /* 698 * ppc_smc37c66xgt_detect 699 * 700 * SMC FDC37C66xGT configuration. 701 */ 702 static int 703 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 704 { 705 int i; 706 u_char r; 707 int type = -1; 708 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 709 710 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 711 712 713 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 714 715 /* 716 * Detection: enter configuration mode and read CRD register. 717 */ 718 PPC_CONFIG_LOCK(ppc); 719 outb(csr, SMC665_iCODE); 720 outb(csr, SMC665_iCODE); 721 PPC_CONFIG_UNLOCK(ppc); 722 723 outb(csr, 0xd); 724 if (inb(cio) == 0x65) { 725 type = SMC_37C665GT; 726 goto config; 727 } 728 729 for (i = 0; i < 2; i++) { 730 PPC_CONFIG_LOCK(ppc); 731 outb(csr, SMC666_iCODE); 732 outb(csr, SMC666_iCODE); 733 PPC_CONFIG_UNLOCK(ppc); 734 735 outb(csr, 0xd); 736 if (inb(cio) == 0x66) { 737 type = SMC_37C666GT; 738 break; 739 } 740 741 /* Another chance, CSR may be hard-configured to be at 0x370 */ 742 csr = SMC666_CSR; 743 } 744 745 config: 746 /* 747 * If chipset not found, do not continue. 748 */ 749 if (type == -1) { 750 outb(csr, 0xaa); /* end config mode */ 751 return (-1); 752 } 753 754 /* select CR1 */ 755 outb(csr, 0x1); 756 757 /* read the port's address: bits 0 and 1 of CR1 */ 758 r = inb(cio) & SMC_CR1_ADDR; 759 if (port_address[(int)r] != ppc->ppc_base) { 760 outb(csr, 0xaa); /* end config mode */ 761 return (-1); 762 } 763 764 ppc->ppc_model = type; 765 766 /* 767 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 768 * If SPP mode is detected, try to set ECP+EPP mode 769 */ 770 771 if (bootverbose) { 772 outb(csr, 0x1); 773 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x", 774 inb(cio) & 0xff); 775 776 outb(csr, 0x4); 777 printf(" CR4=0x%x", inb(cio) & 0xff); 778 } 779 780 /* select CR1 */ 781 outb(csr, 0x1); 782 783 if (!chipset_mode) { 784 /* autodetect mode */ 785 786 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 787 if (type == SMC_37C666GT) { 788 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 789 if (bootverbose) 790 printf(" configuration hardwired, supposing " \ 791 "ECP+EPP SPP"); 792 793 } else 794 if ((inb(cio) & SMC_CR1_MODE) == 0) { 795 /* already in extended parallel port mode, read CR4 */ 796 outb(csr, 0x4); 797 r = (inb(cio) & SMC_CR4_EMODE); 798 799 switch (r) { 800 case SMC_SPP: 801 ppc->ppc_avm |= PPB_SPP; 802 if (bootverbose) 803 printf(" SPP"); 804 break; 805 806 case SMC_EPPSPP: 807 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 808 if (bootverbose) 809 printf(" EPP SPP"); 810 break; 811 812 case SMC_ECP: 813 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 814 if (bootverbose) 815 printf(" ECP SPP"); 816 break; 817 818 case SMC_ECPEPP: 819 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 820 if (bootverbose) 821 printf(" ECP+EPP SPP"); 822 break; 823 } 824 } else { 825 /* not an extended port mode */ 826 ppc->ppc_avm |= PPB_SPP; 827 if (bootverbose) 828 printf(" SPP"); 829 } 830 831 } else { 832 /* mode forced */ 833 ppc->ppc_avm = chipset_mode; 834 835 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 836 if (type == SMC_37C666GT) 837 goto end_detect; 838 839 r = inb(cio); 840 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 841 /* do not use ECP when the mode is not forced to */ 842 outb(cio, r | SMC_CR1_MODE); 843 if (bootverbose) 844 printf(" SPP"); 845 } else { 846 /* an extended mode is selected */ 847 outb(cio, r & ~SMC_CR1_MODE); 848 849 /* read CR4 register and reset mode field */ 850 outb(csr, 0x4); 851 r = inb(cio) & ~SMC_CR4_EMODE; 852 853 if (chipset_mode & PPB_ECP) { 854 if (chipset_mode & PPB_EPP) { 855 outb(cio, r | SMC_ECPEPP); 856 if (bootverbose) 857 printf(" ECP+EPP"); 858 } else { 859 outb(cio, r | SMC_ECP); 860 if (bootverbose) 861 printf(" ECP"); 862 } 863 } else { 864 /* PPB_EPP is set */ 865 outb(cio, r | SMC_EPPSPP); 866 if (bootverbose) 867 printf(" EPP SPP"); 868 } 869 } 870 ppc->ppc_avm = chipset_mode; 871 } 872 873 /* set FIFO threshold to 16 */ 874 if (ppc->ppc_avm & PPB_ECP) { 875 /* select CRA */ 876 outb(csr, 0xa); 877 outb(cio, 16); 878 } 879 880 end_detect: 881 882 if (bootverbose) 883 printf ("\n"); 884 885 if (ppc->ppc_avm & PPB_EPP) { 886 /* select CR4 */ 887 outb(csr, 0x4); 888 r = inb(cio); 889 890 /* 891 * Set the EPP protocol... 892 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 893 */ 894 if (ppc->ppc_epp == EPP_1_9) 895 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 896 else 897 outb(cio, (r | SMC_CR4_EPPTYPE)); 898 } 899 900 outb(csr, 0xaa); /* end config mode */ 901 902 ppc->ppc_type = PPC_TYPE_SMCLIKE; 903 ppc_smclike_setmode(ppc, chipset_mode); 904 905 return (chipset_mode); 906 } 907 908 /* 909 * SMC FDC37C935 configuration 910 * Found on many Alpha machines 911 */ 912 static int 913 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 914 { 915 int type = -1; 916 917 PPC_CONFIG_LOCK(ppc); 918 outb(SMC935_CFG, 0x55); /* enter config mode */ 919 outb(SMC935_CFG, 0x55); 920 PPC_CONFIG_UNLOCK(ppc); 921 922 outb(SMC935_IND, SMC935_ID); /* check device id */ 923 if (inb(SMC935_DAT) == 0x2) 924 type = SMC_37C935; 925 926 if (type == -1) { 927 outb(SMC935_CFG, 0xaa); /* exit config mode */ 928 return (-1); 929 } 930 931 ppc->ppc_model = type; 932 933 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 934 outb(SMC935_DAT, 3); /* which is logical device 3 */ 935 936 /* set io port base */ 937 outb(SMC935_IND, SMC935_PORTHI); 938 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 939 outb(SMC935_IND, SMC935_PORTLO); 940 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 941 942 if (!chipset_mode) 943 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 944 else { 945 ppc->ppc_avm = chipset_mode; 946 outb(SMC935_IND, SMC935_PPMODE); 947 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 948 949 /* SPP + EPP or just plain SPP */ 950 if (chipset_mode & (PPB_SPP)) { 951 if (chipset_mode & PPB_EPP) { 952 if (ppc->ppc_epp == EPP_1_9) { 953 outb(SMC935_IND, SMC935_PPMODE); 954 outb(SMC935_DAT, SMC935_EPP19SPP); 955 } 956 if (ppc->ppc_epp == EPP_1_7) { 957 outb(SMC935_IND, SMC935_PPMODE); 958 outb(SMC935_DAT, SMC935_EPP17SPP); 959 } 960 } else { 961 outb(SMC935_IND, SMC935_PPMODE); 962 outb(SMC935_DAT, SMC935_SPP); 963 } 964 } 965 966 /* ECP + EPP or just plain ECP */ 967 if (chipset_mode & PPB_ECP) { 968 if (chipset_mode & PPB_EPP) { 969 if (ppc->ppc_epp == EPP_1_9) { 970 outb(SMC935_IND, SMC935_PPMODE); 971 outb(SMC935_DAT, SMC935_ECPEPP19); 972 } 973 if (ppc->ppc_epp == EPP_1_7) { 974 outb(SMC935_IND, SMC935_PPMODE); 975 outb(SMC935_DAT, SMC935_ECPEPP17); 976 } 977 } else { 978 outb(SMC935_IND, SMC935_PPMODE); 979 outb(SMC935_DAT, SMC935_ECP); 980 } 981 } 982 } 983 984 outb(SMC935_CFG, 0xaa); /* exit config mode */ 985 986 ppc->ppc_type = PPC_TYPE_SMCLIKE; 987 ppc_smclike_setmode(ppc, chipset_mode); 988 989 return (chipset_mode); 990 } 991 992 /* 993 * Winbond W83877F stuff 994 * 995 * EFER: extended function enable register 996 * EFIR: extended function index register 997 * EFDR: extended function data register 998 */ 999 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1000 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1001 1002 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1003 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1004 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1005 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1006 1007 static int 1008 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1009 { 1010 int i, j, efer; 1011 unsigned char r, hefere, hefras; 1012 1013 for (i = 0; i < 4; i ++) { 1014 /* first try to enable configuration registers */ 1015 efer = w83877f_efers[i]; 1016 1017 /* write the key to the EFER */ 1018 for (j = 0; j < w83877f_keyiter[i]; j ++) 1019 outb (efer, w83877f_keys[i]); 1020 1021 /* then check HEFERE and HEFRAS bits */ 1022 outb (efir, 0x0c); 1023 hefere = inb(efdr) & WINB_HEFERE; 1024 1025 outb (efir, 0x16); 1026 hefras = inb(efdr) & WINB_HEFRAS; 1027 1028 /* 1029 * HEFRAS HEFERE 1030 * 0 1 write 89h to 250h (power-on default) 1031 * 1 0 write 86h twice to 3f0h 1032 * 1 1 write 87h twice to 3f0h 1033 * 0 0 write 88h to 250h 1034 */ 1035 if ((hefere | hefras) == w83877f_hefs[i]) 1036 goto found; 1037 } 1038 1039 return (-1); /* failed */ 1040 1041 found: 1042 /* check base port address - read from CR23 */ 1043 outb(efir, 0x23); 1044 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1045 return (-1); 1046 1047 /* read CHIP ID from CR9/bits0-3 */ 1048 outb(efir, 0x9); 1049 1050 switch (inb(efdr) & WINB_CHIPID) { 1051 case WINB_W83877F_ID: 1052 ppc->ppc_model = WINB_W83877F; 1053 break; 1054 1055 case WINB_W83877AF_ID: 1056 ppc->ppc_model = WINB_W83877AF; 1057 break; 1058 1059 default: 1060 ppc->ppc_model = WINB_UNKNOWN; 1061 } 1062 1063 if (bootverbose) { 1064 /* dump of registers */ 1065 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]); 1066 for (i = 0; i <= 0xd; i ++) { 1067 outb(efir, i); 1068 printf("0x%x ", inb(efdr)); 1069 } 1070 for (i = 0x10; i <= 0x17; i ++) { 1071 outb(efir, i); 1072 printf("0x%x ", inb(efdr)); 1073 } 1074 outb(efir, 0x1e); 1075 printf("0x%x ", inb(efdr)); 1076 for (i = 0x20; i <= 0x29; i ++) { 1077 outb(efir, i); 1078 printf("0x%x ", inb(efdr)); 1079 } 1080 printf("\n"); 1081 } 1082 1083 ppc->ppc_type = PPC_TYPE_GENERIC; 1084 1085 if (!chipset_mode) { 1086 /* autodetect mode */ 1087 1088 /* select CR0 */ 1089 outb(efir, 0x0); 1090 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1091 1092 /* select CR9 */ 1093 outb(efir, 0x9); 1094 r |= (inb(efdr) & WINB_PRTMODS2); 1095 1096 switch (r) { 1097 case WINB_W83757: 1098 if (bootverbose) 1099 device_printf(ppc->ppc_dev, 1100 "W83757 compatible mode\n"); 1101 return (-1); /* generic or SMC-like */ 1102 1103 case WINB_EXTFDC: 1104 case WINB_EXTADP: 1105 case WINB_EXT2FDD: 1106 case WINB_JOYSTICK: 1107 if (bootverbose) 1108 device_printf(ppc->ppc_dev, 1109 "not in parallel port mode\n"); 1110 return (-1); 1111 1112 case (WINB_PARALLEL | WINB_EPP_SPP): 1113 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1114 if (bootverbose) 1115 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1116 break; 1117 1118 case (WINB_PARALLEL | WINB_ECP): 1119 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1120 if (bootverbose) 1121 device_printf(ppc->ppc_dev, "ECP SPP\n"); 1122 break; 1123 1124 case (WINB_PARALLEL | WINB_ECP_EPP): 1125 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1126 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1127 1128 if (bootverbose) 1129 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n"); 1130 break; 1131 default: 1132 printf("%s: unknown case (0x%x)!\n", __func__, r); 1133 } 1134 1135 } else { 1136 /* mode forced */ 1137 1138 /* select CR9 and set PRTMODS2 bit */ 1139 outb(efir, 0x9); 1140 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1141 1142 /* select CR0 and reset PRTMODSx bits */ 1143 outb(efir, 0x0); 1144 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1145 1146 if (chipset_mode & PPB_ECP) { 1147 if (chipset_mode & PPB_EPP) { 1148 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1149 if (bootverbose) 1150 device_printf(ppc->ppc_dev, 1151 "ECP+EPP\n"); 1152 1153 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1154 1155 } else { 1156 outb(efdr, inb(efdr) | WINB_ECP); 1157 if (bootverbose) 1158 device_printf(ppc->ppc_dev, "ECP\n"); 1159 } 1160 } else { 1161 /* select EPP_SPP otherwise */ 1162 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1163 if (bootverbose) 1164 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1165 } 1166 ppc->ppc_avm = chipset_mode; 1167 } 1168 1169 /* exit configuration mode */ 1170 outb(efer, 0xaa); 1171 1172 switch (ppc->ppc_type) { 1173 case PPC_TYPE_SMCLIKE: 1174 ppc_smclike_setmode(ppc, chipset_mode); 1175 break; 1176 default: 1177 ppc_generic_setmode(ppc, chipset_mode); 1178 break; 1179 } 1180 1181 return (chipset_mode); 1182 } 1183 #endif 1184 1185 /* 1186 * ppc_generic_detect 1187 */ 1188 static int 1189 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1190 { 1191 /* default to generic */ 1192 ppc->ppc_type = PPC_TYPE_GENERIC; 1193 1194 if (bootverbose) 1195 device_printf(ppc->ppc_dev, "SPP"); 1196 1197 /* first, check for ECP */ 1198 w_ecr(ppc, PPC_ECR_PS2); 1199 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1200 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1201 if (bootverbose) 1202 printf(" ECP "); 1203 1204 /* search for SMC style ECP+EPP mode */ 1205 w_ecr(ppc, PPC_ECR_EPP); 1206 } 1207 1208 /* try to reset EPP timeout bit */ 1209 if (ppc_check_epp_timeout(ppc)) { 1210 ppc->ppc_dtm |= PPB_EPP; 1211 1212 if (ppc->ppc_dtm & PPB_ECP) { 1213 /* SMC like chipset found */ 1214 ppc->ppc_model = SMC_LIKE; 1215 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1216 1217 if (bootverbose) 1218 printf(" ECP+EPP"); 1219 } else { 1220 if (bootverbose) 1221 printf(" EPP"); 1222 } 1223 } else { 1224 /* restore to standard mode */ 1225 w_ecr(ppc, PPC_ECR_STD); 1226 } 1227 1228 /* XXX try to detect NIBBLE and PS2 modes */ 1229 ppc->ppc_dtm |= PPB_NIBBLE; 1230 1231 if (chipset_mode) 1232 ppc->ppc_avm = chipset_mode; 1233 else 1234 ppc->ppc_avm = ppc->ppc_dtm; 1235 1236 if (bootverbose) 1237 printf("\n"); 1238 1239 switch (ppc->ppc_type) { 1240 case PPC_TYPE_SMCLIKE: 1241 ppc_smclike_setmode(ppc, chipset_mode); 1242 break; 1243 default: 1244 ppc_generic_setmode(ppc, chipset_mode); 1245 break; 1246 } 1247 1248 return (chipset_mode); 1249 } 1250 1251 /* 1252 * ppc_detect() 1253 * 1254 * mode is the mode suggested at boot 1255 */ 1256 static int 1257 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1258 1259 #ifdef PPC_PROBE_CHIPSET 1260 int i, mode; 1261 1262 /* list of supported chipsets */ 1263 int (*chipset_detect[])(struct ppc_data *, int) = { 1264 ppc_pc873xx_detect, 1265 ppc_smc37c66xgt_detect, 1266 ppc_w83877f_detect, 1267 ppc_smc37c935_detect, 1268 ppc_generic_detect, 1269 NULL 1270 }; 1271 #endif 1272 1273 /* if can't find the port and mode not forced return error */ 1274 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1275 return (EIO); /* failed, port not present */ 1276 1277 /* assume centronics compatible mode is supported */ 1278 ppc->ppc_avm = PPB_COMPATIBLE; 1279 1280 #ifdef PPC_PROBE_CHIPSET 1281 /* we have to differenciate available chipset modes, 1282 * chipset running modes and IEEE-1284 operating modes 1283 * 1284 * after detection, the port must support running in compatible mode 1285 */ 1286 if (ppc->ppc_flags & 0x40) { 1287 if (bootverbose) 1288 printf("ppc: chipset forced to generic\n"); 1289 #endif 1290 1291 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1292 1293 #ifdef PPC_PROBE_CHIPSET 1294 } else { 1295 for (i=0; chipset_detect[i] != NULL; i++) { 1296 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1297 ppc->ppc_mode = mode; 1298 break; 1299 } 1300 } 1301 } 1302 #endif 1303 1304 /* configure/detect ECP FIFO */ 1305 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1306 ppc_detect_fifo(ppc); 1307 1308 return (0); 1309 } 1310 1311 /* 1312 * ppc_exec_microseq() 1313 * 1314 * Execute a microsequence. 1315 * Microsequence mechanism is supposed to handle fast I/O operations. 1316 */ 1317 int 1318 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1319 { 1320 struct ppc_data *ppc = DEVTOSOFTC(dev); 1321 struct ppb_microseq *mi; 1322 char cc, *p; 1323 int i, iter, len; 1324 int error; 1325 1326 int reg; 1327 char mask; 1328 int accum = 0; 1329 char *ptr = NULL; 1330 1331 struct ppb_microseq *stack = NULL; 1332 1333 /* microsequence registers are equivalent to PC-like port registers */ 1334 1335 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1336 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1337 1338 #define INCR_PC (mi ++) /* increment program counter */ 1339 1340 PPC_ASSERT_LOCKED(ppc); 1341 mi = *p_msq; 1342 for (;;) { 1343 switch (mi->opcode) { 1344 case MS_OP_RSET: 1345 cc = r_reg(mi->arg[0].i, ppc); 1346 cc &= (char)mi->arg[2].i; /* clear mask */ 1347 cc |= (char)mi->arg[1].i; /* assert mask */ 1348 w_reg(mi->arg[0].i, ppc, cc); 1349 INCR_PC; 1350 break; 1351 1352 case MS_OP_RASSERT_P: 1353 reg = mi->arg[1].i; 1354 ptr = ppc->ppc_ptr; 1355 1356 if ((len = mi->arg[0].i) == MS_ACCUM) { 1357 accum = ppc->ppc_accum; 1358 for (; accum; accum--) 1359 w_reg(reg, ppc, *ptr++); 1360 ppc->ppc_accum = accum; 1361 } else 1362 for (i=0; i<len; i++) 1363 w_reg(reg, ppc, *ptr++); 1364 ppc->ppc_ptr = ptr; 1365 1366 INCR_PC; 1367 break; 1368 1369 case MS_OP_RFETCH_P: 1370 reg = mi->arg[1].i; 1371 mask = (char)mi->arg[2].i; 1372 ptr = ppc->ppc_ptr; 1373 1374 if ((len = mi->arg[0].i) == MS_ACCUM) { 1375 accum = ppc->ppc_accum; 1376 for (; accum; accum--) 1377 *ptr++ = r_reg(reg, ppc) & mask; 1378 ppc->ppc_accum = accum; 1379 } else 1380 for (i=0; i<len; i++) 1381 *ptr++ = r_reg(reg, ppc) & mask; 1382 ppc->ppc_ptr = ptr; 1383 1384 INCR_PC; 1385 break; 1386 1387 case MS_OP_RFETCH: 1388 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1389 (char)mi->arg[1].i; 1390 INCR_PC; 1391 break; 1392 1393 case MS_OP_RASSERT: 1394 case MS_OP_DELAY: 1395 1396 /* let's suppose the next instr. is the same */ 1397 prefetch: 1398 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1399 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1400 1401 if (mi->opcode == MS_OP_DELAY) { 1402 DELAY(mi->arg[0].i); 1403 INCR_PC; 1404 goto prefetch; 1405 } 1406 break; 1407 1408 case MS_OP_ADELAY: 1409 if (mi->arg[0].i) { 1410 PPC_UNLOCK(ppc); 1411 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1412 PPC_LOCK(ppc); 1413 } 1414 INCR_PC; 1415 break; 1416 1417 case MS_OP_TRIG: 1418 reg = mi->arg[0].i; 1419 iter = mi->arg[1].i; 1420 p = (char *)mi->arg[2].p; 1421 1422 /* XXX delay limited to 255 us */ 1423 for (i=0; i<iter; i++) { 1424 w_reg(reg, ppc, *p++); 1425 DELAY((unsigned char)*p++); 1426 } 1427 INCR_PC; 1428 break; 1429 1430 case MS_OP_SET: 1431 ppc->ppc_accum = mi->arg[0].i; 1432 INCR_PC; 1433 break; 1434 1435 case MS_OP_DBRA: 1436 if (--ppc->ppc_accum > 0) 1437 mi += mi->arg[0].i; 1438 INCR_PC; 1439 break; 1440 1441 case MS_OP_BRSET: 1442 cc = r_str(ppc); 1443 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1444 mi += mi->arg[1].i; 1445 INCR_PC; 1446 break; 1447 1448 case MS_OP_BRCLEAR: 1449 cc = r_str(ppc); 1450 if ((cc & (char)mi->arg[0].i) == 0) 1451 mi += mi->arg[1].i; 1452 INCR_PC; 1453 break; 1454 1455 case MS_OP_BRSTAT: 1456 cc = r_str(ppc); 1457 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1458 (char)mi->arg[0].i) 1459 mi += mi->arg[2].i; 1460 INCR_PC; 1461 break; 1462 1463 case MS_OP_C_CALL: 1464 /* 1465 * If the C call returns !0 then end the microseq. 1466 * The current state of ptr is passed to the C function 1467 */ 1468 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1469 return (error); 1470 1471 INCR_PC; 1472 break; 1473 1474 case MS_OP_PTR: 1475 ppc->ppc_ptr = (char *)mi->arg[0].p; 1476 INCR_PC; 1477 break; 1478 1479 case MS_OP_CALL: 1480 if (stack) 1481 panic("%s: too much calls", __func__); 1482 1483 if (mi->arg[0].p) { 1484 /* store the state of the actual 1485 * microsequence 1486 */ 1487 stack = mi; 1488 1489 /* jump to the new microsequence */ 1490 mi = (struct ppb_microseq *)mi->arg[0].p; 1491 } else 1492 INCR_PC; 1493 1494 break; 1495 1496 case MS_OP_SUBRET: 1497 /* retrieve microseq and pc state before the call */ 1498 mi = stack; 1499 1500 /* reset the stack */ 1501 stack = NULL; 1502 1503 /* XXX return code */ 1504 1505 INCR_PC; 1506 break; 1507 1508 case MS_OP_PUT: 1509 case MS_OP_GET: 1510 case MS_OP_RET: 1511 /* can't return to ppb level during the execution 1512 * of a submicrosequence */ 1513 if (stack) 1514 panic("%s: can't return to ppb level", 1515 __func__); 1516 1517 /* update pc for ppb level of execution */ 1518 *p_msq = mi; 1519 1520 /* return to ppb level of execution */ 1521 return (0); 1522 1523 default: 1524 panic("%s: unknown microsequence opcode 0x%x", 1525 __func__, mi->opcode); 1526 } 1527 } 1528 1529 /* unreached */ 1530 } 1531 1532 static void 1533 ppcintr(void *arg) 1534 { 1535 struct ppc_data *ppc = arg; 1536 u_char ctr, ecr, str; 1537 1538 /* 1539 * If we have any child interrupt handlers registered, let 1540 * them handle this interrupt. 1541 * 1542 * XXX: If DMA is in progress should we just complete that w/o 1543 * doing this? 1544 */ 1545 PPC_LOCK(ppc); 1546 if (ppc->ppc_intr_hook != NULL && 1547 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) { 1548 PPC_UNLOCK(ppc); 1549 return; 1550 } 1551 1552 str = r_str(ppc); 1553 ctr = r_ctr(ppc); 1554 ecr = r_ecr(ppc); 1555 1556 #if defined(PPC_DEBUG) && PPC_DEBUG > 1 1557 printf("![%x/%x/%x]", ctr, ecr, str); 1558 #endif 1559 1560 /* don't use ecp mode with IRQENABLE set */ 1561 if (ctr & IRQENABLE) { 1562 PPC_UNLOCK(ppc); 1563 return; 1564 } 1565 1566 /* interrupts are generated by nFault signal 1567 * only in ECP mode */ 1568 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1569 /* check if ppc driver has programmed the 1570 * nFault interrupt */ 1571 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1572 1573 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1574 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1575 } else { 1576 /* shall be handled by underlying layers XXX */ 1577 PPC_UNLOCK(ppc); 1578 return; 1579 } 1580 } 1581 1582 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1583 /* disable interrupts (should be done by hardware though) */ 1584 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1585 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1586 ecr = r_ecr(ppc); 1587 1588 /* check if DMA completed */ 1589 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1590 #ifdef PPC_DEBUG 1591 printf("a"); 1592 #endif 1593 /* stop DMA */ 1594 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1595 ecr = r_ecr(ppc); 1596 1597 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1598 #ifdef PPC_DEBUG 1599 printf("d"); 1600 #endif 1601 ppc->ppc_dmadone(ppc); 1602 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1603 1604 /* wakeup the waiting process */ 1605 wakeup(ppc); 1606 } 1607 } 1608 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1609 1610 /* classic interrupt I/O */ 1611 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1612 } 1613 PPC_UNLOCK(ppc); 1614 1615 return; 1616 } 1617 1618 int 1619 ppc_read(device_t dev, char *buf, int len, int mode) 1620 { 1621 return (EINVAL); 1622 } 1623 1624 int 1625 ppc_write(device_t dev, char *buf, int len, int how) 1626 { 1627 return (EINVAL); 1628 } 1629 1630 int 1631 ppc_reset_epp(device_t dev) 1632 { 1633 struct ppc_data *ppc = DEVTOSOFTC(dev); 1634 1635 PPC_ASSERT_LOCKED(ppc); 1636 ppc_reset_epp_timeout(ppc); 1637 1638 return 0; 1639 } 1640 1641 int 1642 ppc_setmode(device_t dev, int mode) 1643 { 1644 struct ppc_data *ppc = DEVTOSOFTC(dev); 1645 1646 PPC_ASSERT_LOCKED(ppc); 1647 switch (ppc->ppc_type) { 1648 case PPC_TYPE_SMCLIKE: 1649 return (ppc_smclike_setmode(ppc, mode)); 1650 break; 1651 1652 case PPC_TYPE_GENERIC: 1653 default: 1654 return (ppc_generic_setmode(ppc, mode)); 1655 break; 1656 } 1657 1658 /* not reached */ 1659 return (ENXIO); 1660 } 1661 1662 int 1663 ppc_probe(device_t dev, int rid) 1664 { 1665 #ifdef __i386__ 1666 static short next_bios_ppc = 0; 1667 #endif 1668 struct ppc_data *ppc; 1669 int error; 1670 rman_res_t port; 1671 1672 /* 1673 * Allocate the ppc_data structure. 1674 */ 1675 ppc = DEVTOSOFTC(dev); 1676 bzero(ppc, sizeof(struct ppc_data)); 1677 1678 ppc->rid_ioport = rid; 1679 1680 /* retrieve ISA parameters */ 1681 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1682 1683 #ifdef __i386__ 1684 /* 1685 * If port not specified, use bios list. 1686 */ 1687 if (error) { 1688 if ((next_bios_ppc < BIOS_MAX_PPC) && 1689 (*(BIOS_PORTS + next_bios_ppc) != 0)) { 1690 port = *(BIOS_PORTS + next_bios_ppc++); 1691 if (bootverbose) 1692 device_printf(dev, 1693 "parallel port found at 0x%jx\n", port); 1694 } else { 1695 device_printf(dev, "parallel port not found.\n"); 1696 return (ENXIO); 1697 } 1698 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1699 IO_LPTSIZE_EXTENDED); 1700 } 1701 #endif 1702 1703 /* IO port is mandatory */ 1704 1705 /* Try "extended" IO port range...*/ 1706 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 1707 &ppc->rid_ioport, 1708 IO_LPTSIZE_EXTENDED, 1709 RF_ACTIVE); 1710 1711 if (ppc->res_ioport != 0) { 1712 if (bootverbose) 1713 device_printf(dev, "using extended I/O port range\n"); 1714 } else { 1715 /* Failed? If so, then try the "normal" IO port range... */ 1716 ppc->res_ioport = bus_alloc_resource_anywhere(dev, 1717 SYS_RES_IOPORT, 1718 &ppc->rid_ioport, 1719 IO_LPTSIZE_NORMAL, 1720 RF_ACTIVE); 1721 if (ppc->res_ioport != 0) { 1722 if (bootverbose) 1723 device_printf(dev, "using normal I/O port range\n"); 1724 } else { 1725 if (bootverbose) 1726 device_printf(dev, "cannot reserve I/O port range\n"); 1727 goto error; 1728 } 1729 } 1730 1731 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1732 1733 ppc->ppc_flags = device_get_flags(dev); 1734 1735 if (!(ppc->ppc_flags & 0x20)) { 1736 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1737 &ppc->rid_irq, 1738 RF_SHAREABLE); 1739 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1740 &ppc->rid_drq, 1741 RF_ACTIVE); 1742 } 1743 1744 if (ppc->res_irq) 1745 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1746 if (ppc->res_drq) 1747 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1748 1749 ppc->ppc_dev = dev; 1750 ppc->ppc_model = GENERIC; 1751 1752 ppc->ppc_mode = PPB_COMPATIBLE; 1753 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1754 1755 ppc->ppc_type = PPC_TYPE_GENERIC; 1756 1757 /* 1758 * Try to detect the chipset and its mode. 1759 */ 1760 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1761 goto error; 1762 1763 return (0); 1764 1765 error: 1766 if (ppc->res_irq != 0) { 1767 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1768 ppc->res_irq); 1769 } 1770 if (ppc->res_ioport != 0) { 1771 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1772 ppc->res_ioport); 1773 } 1774 if (ppc->res_drq != 0) { 1775 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1776 ppc->res_drq); 1777 } 1778 return (ENXIO); 1779 } 1780 1781 int 1782 ppc_attach(device_t dev) 1783 { 1784 struct ppc_data *ppc = DEVTOSOFTC(dev); 1785 int error; 1786 1787 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF); 1788 1789 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1790 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1791 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1792 ppc_epp_protocol[ppc->ppc_epp] : ""); 1793 1794 if (ppc->ppc_fifo) 1795 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1796 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1797 1798 if (ppc->res_irq) { 1799 /* default to the tty mask for registration */ /* XXX */ 1800 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY | 1801 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie); 1802 if (error) { 1803 device_printf(dev, 1804 "failed to register interrupt handler: %d\n", 1805 error); 1806 mtx_destroy(&ppc->ppc_lock); 1807 return (error); 1808 } 1809 } 1810 1811 /* add ppbus as a child of this isa to parallel bridge */ 1812 ppc->ppbus = device_add_child(dev, "ppbus", -1); 1813 1814 /* 1815 * Probe the ppbus and attach devices found. 1816 */ 1817 device_probe_and_attach(ppc->ppbus); 1818 1819 return (0); 1820 } 1821 1822 int 1823 ppc_detach(device_t dev) 1824 { 1825 struct ppc_data *ppc = DEVTOSOFTC(dev); 1826 1827 if (ppc->res_irq == 0) { 1828 return (ENXIO); 1829 } 1830 1831 /* detach & delete all children */ 1832 device_delete_children(dev); 1833 1834 if (ppc->res_irq != 0) { 1835 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1836 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1837 ppc->res_irq); 1838 } 1839 if (ppc->res_ioport != 0) { 1840 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1841 ppc->res_ioport); 1842 } 1843 if (ppc->res_drq != 0) { 1844 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1845 ppc->res_drq); 1846 } 1847 1848 mtx_destroy(&ppc->ppc_lock); 1849 1850 return (0); 1851 } 1852 1853 u_char 1854 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1855 { 1856 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1857 1858 PPC_ASSERT_LOCKED(ppc); 1859 switch (iop) { 1860 case PPB_OUTSB_EPP: 1861 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1862 break; 1863 case PPB_OUTSW_EPP: 1864 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1865 break; 1866 case PPB_OUTSL_EPP: 1867 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1868 break; 1869 case PPB_INSB_EPP: 1870 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1871 break; 1872 case PPB_INSW_EPP: 1873 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1874 break; 1875 case PPB_INSL_EPP: 1876 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1877 break; 1878 case PPB_RDTR: 1879 return (r_dtr(ppc)); 1880 case PPB_RSTR: 1881 return (r_str(ppc)); 1882 case PPB_RCTR: 1883 return (r_ctr(ppc)); 1884 case PPB_REPP_A: 1885 return (r_epp_A(ppc)); 1886 case PPB_REPP_D: 1887 return (r_epp_D(ppc)); 1888 case PPB_RECR: 1889 return (r_ecr(ppc)); 1890 case PPB_RFIFO: 1891 return (r_fifo(ppc)); 1892 case PPB_WDTR: 1893 w_dtr(ppc, byte); 1894 break; 1895 case PPB_WSTR: 1896 w_str(ppc, byte); 1897 break; 1898 case PPB_WCTR: 1899 w_ctr(ppc, byte); 1900 break; 1901 case PPB_WEPP_A: 1902 w_epp_A(ppc, byte); 1903 break; 1904 case PPB_WEPP_D: 1905 w_epp_D(ppc, byte); 1906 break; 1907 case PPB_WECR: 1908 w_ecr(ppc, byte); 1909 break; 1910 case PPB_WFIFO: 1911 w_fifo(ppc, byte); 1912 break; 1913 default: 1914 panic("%s: unknown I/O operation", __func__); 1915 break; 1916 } 1917 1918 return (0); /* not significative */ 1919 } 1920 1921 int 1922 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1923 { 1924 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1925 1926 switch (index) { 1927 case PPC_IVAR_EPP_PROTO: 1928 PPC_ASSERT_LOCKED(ppc); 1929 *val = (u_long)ppc->ppc_epp; 1930 break; 1931 case PPC_IVAR_LOCK: 1932 *val = (uintptr_t)&ppc->ppc_lock; 1933 break; 1934 default: 1935 return (ENOENT); 1936 } 1937 1938 return (0); 1939 } 1940 1941 int 1942 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val) 1943 { 1944 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1945 1946 switch (index) { 1947 case PPC_IVAR_INTR_HANDLER: 1948 PPC_ASSERT_LOCKED(ppc); 1949 if (dev != ppc->ppbus) 1950 return (EINVAL); 1951 if (val == 0) { 1952 ppc->ppc_intr_hook = NULL; 1953 break; 1954 } 1955 if (ppc->ppc_intr_hook != NULL) 1956 return (EBUSY); 1957 ppc->ppc_intr_hook = (void *)val; 1958 ppc->ppc_intr_arg = device_get_softc(dev); 1959 break; 1960 default: 1961 return (ENOENT); 1962 } 1963 1964 return (0); 1965 } 1966 1967 /* 1968 * We allow child devices to allocate an IRQ resource at rid 0 for their 1969 * interrupt handlers. 1970 */ 1971 struct resource * 1972 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 1973 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1974 { 1975 struct ppc_data *ppc = DEVTOSOFTC(bus); 1976 1977 switch (type) { 1978 case SYS_RES_IRQ: 1979 if (*rid == 0) 1980 return (ppc->res_irq); 1981 break; 1982 } 1983 return (NULL); 1984 } 1985 1986 int 1987 ppc_release_resource(device_t bus, device_t child, int type, int rid, 1988 struct resource *r) 1989 { 1990 #ifdef INVARIANTS 1991 struct ppc_data *ppc = DEVTOSOFTC(bus); 1992 #endif 1993 1994 switch (type) { 1995 case SYS_RES_IRQ: 1996 if (rid == 0) { 1997 KASSERT(r == ppc->res_irq, 1998 ("ppc child IRQ resource mismatch")); 1999 return (0); 2000 } 2001 break; 2002 } 2003 return (EINVAL); 2004 } 2005 2006 MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2007