1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997-2000 Nicolas Souchu 5 * Copyright (c) 2001 Alcove - Nicolas Souchu 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ppc.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/interrupt.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/mutex.h> 44 #include <sys/proc.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/rman.h> 49 50 #ifdef __i386__ 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <machine/vmparam.h> 54 #include <machine/pc/bios.h> 55 #endif 56 57 #include <dev/ppbus/ppbconf.h> 58 #include <dev/ppbus/ppb_msq.h> 59 60 #include <dev/ppc/ppcvar.h> 61 #include <dev/ppc/ppcreg.h> 62 63 #include "ppbus_if.h" 64 65 static void ppcintr(void *arg); 66 67 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 68 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 69 70 #define LOG_PPC(function, ppc, string) \ 71 if (bootverbose) printf("%s: %s\n", function, string) 72 73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 74 75 /* 76 * We use critical enter/exit for the simple config locking needed to 77 * detect the devices. We just want to make sure that both of our writes 78 * happen without someone else also writing to those config registers. Since 79 * we just do this at startup, Giant keeps multiple threads from executing, 80 * and critical_enter() then is all that's needed to keep us from being preempted 81 * during the critical sequences with the hardware. 82 * 83 * Note: this doesn't prevent multiple threads from putting the chips into 84 * config mode, but since we only do that to detect the type at startup the 85 * extra overhead isn't needed since Giant protects us from multiple entry 86 * and no other code changes these registers. 87 */ 88 #define PPC_CONFIG_LOCK(ppc) critical_enter() 89 #define PPC_CONFIG_UNLOCK(ppc) critical_exit() 90 91 devclass_t ppc_devclass; 92 const char ppc_driver_name[] = "ppc"; 93 94 static char *ppc_models[] = { 95 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 96 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 97 "SMC FDC37C935", "PC87303", 0 98 }; 99 100 /* list of available modes */ 101 static char *ppc_avms[] = { 102 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 103 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 104 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 105 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 106 }; 107 108 /* list of current executing modes 109 * Note that few modes do not actually exist. 110 */ 111 static char *ppc_modes[] = { 112 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 113 "EPP", "EPP", "EPP", "ECP", 114 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 115 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 116 }; 117 118 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 119 120 #ifdef __i386__ 121 /* 122 * BIOS printer list - used by BIOS probe. 123 */ 124 #define BIOS_PPC_PORTS 0x408 125 #define BIOS_PORTS ((short *)BIOS_PADDRTOVADDR(BIOS_PPC_PORTS)) 126 #define BIOS_MAX_PPC 4 127 #endif 128 129 /* 130 * ppc_ecp_sync() XXX 131 */ 132 int 133 ppc_ecp_sync(device_t dev) 134 { 135 int i, r; 136 struct ppc_data *ppc = DEVTOSOFTC(dev); 137 138 PPC_ASSERT_LOCKED(ppc); 139 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 140 return 0; 141 142 r = r_ecr(ppc); 143 if ((r & 0xe0) != PPC_ECR_EPP) 144 return 0; 145 146 for (i = 0; i < 100; i++) { 147 r = r_ecr(ppc); 148 if (r & 0x1) 149 return 0; 150 DELAY(100); 151 } 152 153 device_printf(dev, "ECP sync failed as data still present in FIFO.\n"); 154 155 return 0; 156 } 157 158 /* 159 * ppc_detect_fifo() 160 * 161 * Detect parallel port FIFO 162 */ 163 static int 164 ppc_detect_fifo(struct ppc_data *ppc) 165 { 166 char ecr_sav; 167 char ctr_sav, ctr, cc; 168 short i; 169 170 /* save registers */ 171 ecr_sav = r_ecr(ppc); 172 ctr_sav = r_ctr(ppc); 173 174 /* enter ECP configuration mode, no interrupt, no DMA */ 175 w_ecr(ppc, 0xf4); 176 177 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 178 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 179 180 /* XXX 16 and 32 bits implementations not supported */ 181 if (ppc->ppc_pword != PPC_PWORD_8) { 182 LOG_PPC(__func__, ppc, "PWord not supported"); 183 goto error; 184 } 185 186 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 187 ctr = r_ctr(ppc); 188 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 189 190 /* enter ECP test mode, no interrupt, no DMA */ 191 w_ecr(ppc, 0xd4); 192 193 /* flush the FIFO */ 194 for (i=0; i<1024; i++) { 195 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 196 break; 197 cc = r_fifo(ppc); 198 } 199 200 if (i >= 1024) { 201 LOG_PPC(__func__, ppc, "can't flush FIFO"); 202 goto error; 203 } 204 205 /* enable interrupts, no DMA */ 206 w_ecr(ppc, 0xd0); 207 208 /* determine readIntrThreshold 209 * fill the FIFO until serviceIntr is set 210 */ 211 for (i=0; i<1024; i++) { 212 w_fifo(ppc, (char)i); 213 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 214 /* readThreshold reached */ 215 ppc->ppc_rthr = i+1; 216 } 217 if (r_ecr(ppc) & PPC_FIFO_FULL) { 218 ppc->ppc_fifo = i+1; 219 break; 220 } 221 } 222 223 if (i >= 1024) { 224 LOG_PPC(__func__, ppc, "can't fill FIFO"); 225 goto error; 226 } 227 228 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 229 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 230 w_ecr(ppc, 0xd0); /* enable interrupts */ 231 232 /* determine writeIntrThreshold 233 * empty the FIFO until serviceIntr is set 234 */ 235 for (i=ppc->ppc_fifo; i>0; i--) { 236 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 237 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 238 goto error; 239 } 240 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 241 /* writeIntrThreshold reached */ 242 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 243 } 244 /* if FIFO empty before the last byte, error */ 245 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 246 LOG_PPC(__func__, ppc, "data lost in FIFO"); 247 goto error; 248 } 249 } 250 251 /* FIFO must be empty after the last byte */ 252 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 253 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 254 goto error; 255 } 256 257 w_ctr(ppc, ctr_sav); 258 w_ecr(ppc, ecr_sav); 259 260 return (0); 261 262 error: 263 w_ctr(ppc, ctr_sav); 264 w_ecr(ppc, ecr_sav); 265 266 return (EINVAL); 267 } 268 269 static int 270 ppc_detect_port(struct ppc_data *ppc) 271 { 272 273 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 274 w_dtr(ppc, 0xaa); 275 if (r_dtr(ppc) != 0xaa) 276 return (0); 277 278 return (1); 279 } 280 281 /* 282 * EPP timeout, according to the PC87332 manual 283 * Semantics of clearing EPP timeout bit. 284 * PC87332 - reading SPP_STR does it... 285 * SMC - write 1 to EPP timeout bit XXX 286 * Others - (?) write 0 to EPP timeout bit 287 */ 288 static void 289 ppc_reset_epp_timeout(struct ppc_data *ppc) 290 { 291 char r; 292 293 r = r_str(ppc); 294 w_str(ppc, r | 0x1); 295 w_str(ppc, r & 0xfe); 296 297 return; 298 } 299 300 static int 301 ppc_check_epp_timeout(struct ppc_data *ppc) 302 { 303 ppc_reset_epp_timeout(ppc); 304 305 return (!(r_str(ppc) & TIMEOUT)); 306 } 307 308 /* 309 * Configure current operating mode 310 */ 311 static int 312 ppc_generic_setmode(struct ppc_data *ppc, int mode) 313 { 314 u_char ecr = 0; 315 316 /* check if mode is available */ 317 if (mode && !(ppc->ppc_avm & mode)) 318 return (EINVAL); 319 320 /* if ECP mode, configure ecr register */ 321 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 322 /* return to byte mode (keeping direction bit), 323 * no interrupt, no DMA to be able to change to 324 * ECP 325 */ 326 w_ecr(ppc, PPC_ECR_RESET); 327 ecr = PPC_DISABLE_INTR; 328 329 if (mode & PPB_EPP) 330 return (EINVAL); 331 else if (mode & PPB_ECP) 332 /* select ECP mode */ 333 ecr |= PPC_ECR_ECP; 334 else if (mode & PPB_PS2) 335 /* select PS2 mode with ECP */ 336 ecr |= PPC_ECR_PS2; 337 else 338 /* select COMPATIBLE/NIBBLE mode */ 339 ecr |= PPC_ECR_STD; 340 341 w_ecr(ppc, ecr); 342 } 343 344 ppc->ppc_mode = mode; 345 346 return (0); 347 } 348 349 /* 350 * The ppc driver is free to choose options like FIFO or DMA 351 * if ECP mode is available. 352 * 353 * The 'RAW' option allows the upper drivers to force the ppc mode 354 * even with FIFO, DMA available. 355 */ 356 static int 357 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 358 { 359 u_char ecr = 0; 360 361 /* check if mode is available */ 362 if (mode && !(ppc->ppc_avm & mode)) 363 return (EINVAL); 364 365 /* if ECP mode, configure ecr register */ 366 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 367 /* return to byte mode (keeping direction bit), 368 * no interrupt, no DMA to be able to change to 369 * ECP or EPP mode 370 */ 371 w_ecr(ppc, PPC_ECR_RESET); 372 ecr = PPC_DISABLE_INTR; 373 374 if (mode & PPB_EPP) 375 /* select EPP mode */ 376 ecr |= PPC_ECR_EPP; 377 else if (mode & PPB_ECP) 378 /* select ECP mode */ 379 ecr |= PPC_ECR_ECP; 380 else if (mode & PPB_PS2) 381 /* select PS2 mode with ECP */ 382 ecr |= PPC_ECR_PS2; 383 else 384 /* select COMPATIBLE/NIBBLE mode */ 385 ecr |= PPC_ECR_STD; 386 387 w_ecr(ppc, ecr); 388 } 389 390 ppc->ppc_mode = mode; 391 392 return (0); 393 } 394 395 #ifdef PPC_PROBE_CHIPSET 396 /* 397 * ppc_pc873xx_detect 398 * 399 * Probe for a Natsemi PC873xx-family part. 400 * 401 * References in this function are to the National Semiconductor 402 * PC87332 datasheet TL/C/11930, May 1995 revision. 403 */ 404 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 405 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 406 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 407 408 static int pc873xx_regstab[] = { 409 PC873_FER, PC873_FAR, PC873_PTR, 410 PC873_FCR, PC873_PCR, PC873_PMC, 411 PC873_TUP, PC873_SID, PC873_PNP0, 412 PC873_PNP1, PC873_LPTBA, -1 413 }; 414 415 static char *pc873xx_rnametab[] = { 416 "FER", "FAR", "PTR", "FCR", "PCR", 417 "PMC", "TUP", "SID", "PNP0", "PNP1", 418 "LPTBA", NULL 419 }; 420 421 static int 422 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 423 { 424 static int index = 0; 425 int idport, irq; 426 int ptr, pcr, val, i; 427 428 while ((idport = pc873xx_basetab[index++])) { 429 430 /* XXX should check first to see if this location is already claimed */ 431 432 /* 433 * Pull the 873xx through the power-on ID cycle (2.2,1.). 434 * We can't use this to locate the chip as it may already have 435 * been used by the BIOS. 436 */ 437 (void)inb(idport); (void)inb(idport); 438 (void)inb(idport); (void)inb(idport); 439 440 /* 441 * Read the SID byte. Possible values are : 442 * 443 * 01010xxx PC87334 444 * 0001xxxx PC87332 445 * 01110xxx PC87306 446 * 00110xxx PC87303 447 */ 448 outb(idport, PC873_SID); 449 val = inb(idport + 1); 450 if ((val & 0xf0) == 0x10) { 451 ppc->ppc_model = NS_PC87332; 452 } else if ((val & 0xf8) == 0x70) { 453 ppc->ppc_model = NS_PC87306; 454 } else if ((val & 0xf8) == 0x50) { 455 ppc->ppc_model = NS_PC87334; 456 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 457 documentation, but probing 458 yielded 0x40... */ 459 ppc->ppc_model = NS_PC87303; 460 } else { 461 if (bootverbose && (val != 0xff)) 462 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 463 continue ; /* not recognised */ 464 } 465 466 /* print registers */ 467 if (bootverbose) { 468 printf("PC873xx"); 469 for (i=0; pc873xx_regstab[i] != -1; i++) { 470 outb(idport, pc873xx_regstab[i]); 471 printf(" %s=0x%x", pc873xx_rnametab[i], 472 inb(idport + 1) & 0xff); 473 } 474 printf("\n"); 475 } 476 477 /* 478 * We think we have one. Is it enabled and where we want it to be? 479 */ 480 outb(idport, PC873_FER); 481 val = inb(idport + 1); 482 if (!(val & PC873_PPENABLE)) { 483 if (bootverbose) 484 printf("PC873xx parallel port disabled\n"); 485 continue; 486 } 487 outb(idport, PC873_FAR); 488 val = inb(idport + 1); 489 /* XXX we should create a driver instance for every port found */ 490 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 491 492 /* First try to change the port address to that requested... */ 493 494 switch (ppc->ppc_base) { 495 case 0x378: 496 val &= 0xfc; 497 break; 498 499 case 0x3bc: 500 val &= 0xfd; 501 break; 502 503 case 0x278: 504 val &= 0xfe; 505 break; 506 507 default: 508 val &= 0xfd; 509 break; 510 } 511 512 outb(idport, PC873_FAR); 513 outb(idport + 1, val); 514 outb(idport + 1, val); 515 516 /* Check for success by reading back the value we supposedly 517 wrote and comparing...*/ 518 519 outb(idport, PC873_FAR); 520 val = inb(idport + 1) & 0x3; 521 522 /* If we fail, report the failure... */ 523 524 if (pc873xx_porttab[val] != ppc->ppc_base) { 525 if (bootverbose) 526 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 527 pc873xx_porttab[val], ppc->ppc_base); 528 } 529 continue; 530 } 531 532 outb(idport, PC873_PTR); 533 ptr = inb(idport + 1); 534 535 /* get irq settings */ 536 if (ppc->ppc_base == 0x378) 537 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 538 else 539 irq = pc873xx_irqtab[val]; 540 541 if (bootverbose) 542 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 543 544 /* 545 * Check if irq settings are correct 546 */ 547 if (irq != ppc->ppc_irq) { 548 /* 549 * If the chipset is not locked and base address is 0x378, 550 * we have another chance 551 */ 552 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 553 if (ppc->ppc_irq == 7) { 554 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 555 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 556 } else { 557 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 558 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 559 } 560 if (bootverbose) 561 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 562 } else { 563 if (bootverbose) 564 printf("PC873xx sorry, can't change irq setting\n"); 565 } 566 } else { 567 if (bootverbose) 568 printf("PC873xx irq settings are correct\n"); 569 } 570 571 outb(idport, PC873_PCR); 572 pcr = inb(idport + 1); 573 574 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 575 if (bootverbose) 576 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 577 578 ppc->ppc_avm |= PPB_NIBBLE; 579 if (bootverbose) 580 printf(", NIBBLE"); 581 582 if (pcr & PC873_EPPEN) { 583 ppc->ppc_avm |= PPB_EPP; 584 585 if (bootverbose) 586 printf(", EPP"); 587 588 if (pcr & PC873_EPP19) 589 ppc->ppc_epp = EPP_1_9; 590 else 591 ppc->ppc_epp = EPP_1_7; 592 593 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 594 outb(idport, PC873_PTR); 595 ptr = inb(idport + 1); 596 if (ptr & PC873_EPPRDIR) 597 printf(", Regular mode"); 598 else 599 printf(", Automatic mode"); 600 } 601 } else if (pcr & PC873_ECPEN) { 602 ppc->ppc_avm |= PPB_ECP; 603 if (bootverbose) 604 printf(", ECP"); 605 606 if (pcr & PC873_ECPCLK) { /* XXX */ 607 ppc->ppc_avm |= PPB_PS2; 608 if (bootverbose) 609 printf(", PS/2"); 610 } 611 } else { 612 outb(idport, PC873_PTR); 613 ptr = inb(idport + 1); 614 if (ptr & PC873_EXTENDED) { 615 ppc->ppc_avm |= PPB_SPP; 616 if (bootverbose) 617 printf(", SPP"); 618 } 619 } 620 } else { 621 if (bootverbose) 622 printf("PC873xx unlocked"); 623 624 if (chipset_mode & PPB_ECP) { 625 if ((chipset_mode & PPB_EPP) && bootverbose) 626 printf(", ECP+EPP not supported"); 627 628 pcr &= ~PC873_EPPEN; 629 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 630 outb(idport + 1, pcr); 631 outb(idport + 1, pcr); 632 633 if (bootverbose) 634 printf(", ECP"); 635 636 } else if (chipset_mode & PPB_EPP) { 637 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 638 pcr |= (PC873_EPPEN | PC873_EPP19); 639 outb(idport + 1, pcr); 640 outb(idport + 1, pcr); 641 642 ppc->ppc_epp = EPP_1_9; /* XXX */ 643 644 if (bootverbose) 645 printf(", EPP1.9"); 646 647 /* enable automatic direction turnover */ 648 if (ppc->ppc_model == NS_PC87332) { 649 outb(idport, PC873_PTR); 650 ptr = inb(idport + 1); 651 ptr &= ~PC873_EPPRDIR; 652 outb(idport + 1, ptr); 653 outb(idport + 1, ptr); 654 655 if (bootverbose) 656 printf(", Automatic mode"); 657 } 658 } else { 659 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 660 outb(idport + 1, pcr); 661 outb(idport + 1, pcr); 662 663 /* configure extended bit in PTR */ 664 outb(idport, PC873_PTR); 665 ptr = inb(idport + 1); 666 667 if (chipset_mode & PPB_PS2) { 668 ptr |= PC873_EXTENDED; 669 670 if (bootverbose) 671 printf(", PS/2"); 672 673 } else { 674 /* default to NIBBLE mode */ 675 ptr &= ~PC873_EXTENDED; 676 677 if (bootverbose) 678 printf(", NIBBLE"); 679 } 680 outb(idport + 1, ptr); 681 outb(idport + 1, ptr); 682 } 683 684 ppc->ppc_avm = chipset_mode; 685 } 686 687 if (bootverbose) 688 printf("\n"); 689 690 ppc->ppc_type = PPC_TYPE_GENERIC; 691 ppc_generic_setmode(ppc, chipset_mode); 692 693 return(chipset_mode); 694 } 695 return(-1); 696 } 697 698 /* 699 * ppc_smc37c66xgt_detect 700 * 701 * SMC FDC37C66xGT configuration. 702 */ 703 static int 704 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 705 { 706 int i; 707 u_char r; 708 int type = -1; 709 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 710 711 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 712 713 714 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 715 716 /* 717 * Detection: enter configuration mode and read CRD register. 718 */ 719 PPC_CONFIG_LOCK(ppc); 720 outb(csr, SMC665_iCODE); 721 outb(csr, SMC665_iCODE); 722 PPC_CONFIG_UNLOCK(ppc); 723 724 outb(csr, 0xd); 725 if (inb(cio) == 0x65) { 726 type = SMC_37C665GT; 727 goto config; 728 } 729 730 for (i = 0; i < 2; i++) { 731 PPC_CONFIG_LOCK(ppc); 732 outb(csr, SMC666_iCODE); 733 outb(csr, SMC666_iCODE); 734 PPC_CONFIG_UNLOCK(ppc); 735 736 outb(csr, 0xd); 737 if (inb(cio) == 0x66) { 738 type = SMC_37C666GT; 739 break; 740 } 741 742 /* Another chance, CSR may be hard-configured to be at 0x370 */ 743 csr = SMC666_CSR; 744 } 745 746 config: 747 /* 748 * If chipset not found, do not continue. 749 */ 750 if (type == -1) { 751 outb(csr, 0xaa); /* end config mode */ 752 return (-1); 753 } 754 755 /* select CR1 */ 756 outb(csr, 0x1); 757 758 /* read the port's address: bits 0 and 1 of CR1 */ 759 r = inb(cio) & SMC_CR1_ADDR; 760 if (port_address[(int)r] != ppc->ppc_base) { 761 outb(csr, 0xaa); /* end config mode */ 762 return (-1); 763 } 764 765 ppc->ppc_model = type; 766 767 /* 768 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 769 * If SPP mode is detected, try to set ECP+EPP mode 770 */ 771 772 if (bootverbose) { 773 outb(csr, 0x1); 774 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x", 775 inb(cio) & 0xff); 776 777 outb(csr, 0x4); 778 printf(" CR4=0x%x", inb(cio) & 0xff); 779 } 780 781 /* select CR1 */ 782 outb(csr, 0x1); 783 784 if (!chipset_mode) { 785 /* autodetect mode */ 786 787 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 788 if (type == SMC_37C666GT) { 789 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 790 if (bootverbose) 791 printf(" configuration hardwired, supposing " \ 792 "ECP+EPP SPP"); 793 794 } else 795 if ((inb(cio) & SMC_CR1_MODE) == 0) { 796 /* already in extended parallel port mode, read CR4 */ 797 outb(csr, 0x4); 798 r = (inb(cio) & SMC_CR4_EMODE); 799 800 switch (r) { 801 case SMC_SPP: 802 ppc->ppc_avm |= PPB_SPP; 803 if (bootverbose) 804 printf(" SPP"); 805 break; 806 807 case SMC_EPPSPP: 808 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 809 if (bootverbose) 810 printf(" EPP SPP"); 811 break; 812 813 case SMC_ECP: 814 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 815 if (bootverbose) 816 printf(" ECP SPP"); 817 break; 818 819 case SMC_ECPEPP: 820 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 821 if (bootverbose) 822 printf(" ECP+EPP SPP"); 823 break; 824 } 825 } else { 826 /* not an extended port mode */ 827 ppc->ppc_avm |= PPB_SPP; 828 if (bootverbose) 829 printf(" SPP"); 830 } 831 832 } else { 833 /* mode forced */ 834 ppc->ppc_avm = chipset_mode; 835 836 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 837 if (type == SMC_37C666GT) 838 goto end_detect; 839 840 r = inb(cio); 841 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 842 /* do not use ECP when the mode is not forced to */ 843 outb(cio, r | SMC_CR1_MODE); 844 if (bootverbose) 845 printf(" SPP"); 846 } else { 847 /* an extended mode is selected */ 848 outb(cio, r & ~SMC_CR1_MODE); 849 850 /* read CR4 register and reset mode field */ 851 outb(csr, 0x4); 852 r = inb(cio) & ~SMC_CR4_EMODE; 853 854 if (chipset_mode & PPB_ECP) { 855 if (chipset_mode & PPB_EPP) { 856 outb(cio, r | SMC_ECPEPP); 857 if (bootverbose) 858 printf(" ECP+EPP"); 859 } else { 860 outb(cio, r | SMC_ECP); 861 if (bootverbose) 862 printf(" ECP"); 863 } 864 } else { 865 /* PPB_EPP is set */ 866 outb(cio, r | SMC_EPPSPP); 867 if (bootverbose) 868 printf(" EPP SPP"); 869 } 870 } 871 ppc->ppc_avm = chipset_mode; 872 } 873 874 /* set FIFO threshold to 16 */ 875 if (ppc->ppc_avm & PPB_ECP) { 876 /* select CRA */ 877 outb(csr, 0xa); 878 outb(cio, 16); 879 } 880 881 end_detect: 882 883 if (bootverbose) 884 printf ("\n"); 885 886 if (ppc->ppc_avm & PPB_EPP) { 887 /* select CR4 */ 888 outb(csr, 0x4); 889 r = inb(cio); 890 891 /* 892 * Set the EPP protocol... 893 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 894 */ 895 if (ppc->ppc_epp == EPP_1_9) 896 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 897 else 898 outb(cio, (r | SMC_CR4_EPPTYPE)); 899 } 900 901 outb(csr, 0xaa); /* end config mode */ 902 903 ppc->ppc_type = PPC_TYPE_SMCLIKE; 904 ppc_smclike_setmode(ppc, chipset_mode); 905 906 return (chipset_mode); 907 } 908 909 /* 910 * SMC FDC37C935 configuration 911 * Found on many Alpha machines 912 */ 913 static int 914 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 915 { 916 int type = -1; 917 918 PPC_CONFIG_LOCK(ppc); 919 outb(SMC935_CFG, 0x55); /* enter config mode */ 920 outb(SMC935_CFG, 0x55); 921 PPC_CONFIG_UNLOCK(ppc); 922 923 outb(SMC935_IND, SMC935_ID); /* check device id */ 924 if (inb(SMC935_DAT) == 0x2) 925 type = SMC_37C935; 926 927 if (type == -1) { 928 outb(SMC935_CFG, 0xaa); /* exit config mode */ 929 return (-1); 930 } 931 932 ppc->ppc_model = type; 933 934 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 935 outb(SMC935_DAT, 3); /* which is logical device 3 */ 936 937 /* set io port base */ 938 outb(SMC935_IND, SMC935_PORTHI); 939 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 940 outb(SMC935_IND, SMC935_PORTLO); 941 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 942 943 if (!chipset_mode) 944 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 945 else { 946 ppc->ppc_avm = chipset_mode; 947 outb(SMC935_IND, SMC935_PPMODE); 948 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 949 950 /* SPP + EPP or just plain SPP */ 951 if (chipset_mode & (PPB_SPP)) { 952 if (chipset_mode & PPB_EPP) { 953 if (ppc->ppc_epp == EPP_1_9) { 954 outb(SMC935_IND, SMC935_PPMODE); 955 outb(SMC935_DAT, SMC935_EPP19SPP); 956 } 957 if (ppc->ppc_epp == EPP_1_7) { 958 outb(SMC935_IND, SMC935_PPMODE); 959 outb(SMC935_DAT, SMC935_EPP17SPP); 960 } 961 } else { 962 outb(SMC935_IND, SMC935_PPMODE); 963 outb(SMC935_DAT, SMC935_SPP); 964 } 965 } 966 967 /* ECP + EPP or just plain ECP */ 968 if (chipset_mode & PPB_ECP) { 969 if (chipset_mode & PPB_EPP) { 970 if (ppc->ppc_epp == EPP_1_9) { 971 outb(SMC935_IND, SMC935_PPMODE); 972 outb(SMC935_DAT, SMC935_ECPEPP19); 973 } 974 if (ppc->ppc_epp == EPP_1_7) { 975 outb(SMC935_IND, SMC935_PPMODE); 976 outb(SMC935_DAT, SMC935_ECPEPP17); 977 } 978 } else { 979 outb(SMC935_IND, SMC935_PPMODE); 980 outb(SMC935_DAT, SMC935_ECP); 981 } 982 } 983 } 984 985 outb(SMC935_CFG, 0xaa); /* exit config mode */ 986 987 ppc->ppc_type = PPC_TYPE_SMCLIKE; 988 ppc_smclike_setmode(ppc, chipset_mode); 989 990 return (chipset_mode); 991 } 992 993 /* 994 * Winbond W83877F stuff 995 * 996 * EFER: extended function enable register 997 * EFIR: extended function index register 998 * EFDR: extended function data register 999 */ 1000 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1001 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1002 1003 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1004 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1005 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1006 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1007 1008 static int 1009 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1010 { 1011 int i, j, efer; 1012 unsigned char r, hefere, hefras; 1013 1014 for (i = 0; i < 4; i ++) { 1015 /* first try to enable configuration registers */ 1016 efer = w83877f_efers[i]; 1017 1018 /* write the key to the EFER */ 1019 for (j = 0; j < w83877f_keyiter[i]; j ++) 1020 outb (efer, w83877f_keys[i]); 1021 1022 /* then check HEFERE and HEFRAS bits */ 1023 outb (efir, 0x0c); 1024 hefere = inb(efdr) & WINB_HEFERE; 1025 1026 outb (efir, 0x16); 1027 hefras = inb(efdr) & WINB_HEFRAS; 1028 1029 /* 1030 * HEFRAS HEFERE 1031 * 0 1 write 89h to 250h (power-on default) 1032 * 1 0 write 86h twice to 3f0h 1033 * 1 1 write 87h twice to 3f0h 1034 * 0 0 write 88h to 250h 1035 */ 1036 if ((hefere | hefras) == w83877f_hefs[i]) 1037 goto found; 1038 } 1039 1040 return (-1); /* failed */ 1041 1042 found: 1043 /* check base port address - read from CR23 */ 1044 outb(efir, 0x23); 1045 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1046 return (-1); 1047 1048 /* read CHIP ID from CR9/bits0-3 */ 1049 outb(efir, 0x9); 1050 1051 switch (inb(efdr) & WINB_CHIPID) { 1052 case WINB_W83877F_ID: 1053 ppc->ppc_model = WINB_W83877F; 1054 break; 1055 1056 case WINB_W83877AF_ID: 1057 ppc->ppc_model = WINB_W83877AF; 1058 break; 1059 1060 default: 1061 ppc->ppc_model = WINB_UNKNOWN; 1062 } 1063 1064 if (bootverbose) { 1065 /* dump of registers */ 1066 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]); 1067 for (i = 0; i <= 0xd; i ++) { 1068 outb(efir, i); 1069 printf("0x%x ", inb(efdr)); 1070 } 1071 for (i = 0x10; i <= 0x17; i ++) { 1072 outb(efir, i); 1073 printf("0x%x ", inb(efdr)); 1074 } 1075 outb(efir, 0x1e); 1076 printf("0x%x ", inb(efdr)); 1077 for (i = 0x20; i <= 0x29; i ++) { 1078 outb(efir, i); 1079 printf("0x%x ", inb(efdr)); 1080 } 1081 printf("\n"); 1082 } 1083 1084 ppc->ppc_type = PPC_TYPE_GENERIC; 1085 1086 if (!chipset_mode) { 1087 /* autodetect mode */ 1088 1089 /* select CR0 */ 1090 outb(efir, 0x0); 1091 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1092 1093 /* select CR9 */ 1094 outb(efir, 0x9); 1095 r |= (inb(efdr) & WINB_PRTMODS2); 1096 1097 switch (r) { 1098 case WINB_W83757: 1099 if (bootverbose) 1100 device_printf(ppc->ppc_dev, 1101 "W83757 compatible mode\n"); 1102 return (-1); /* generic or SMC-like */ 1103 1104 case WINB_EXTFDC: 1105 case WINB_EXTADP: 1106 case WINB_EXT2FDD: 1107 case WINB_JOYSTICK: 1108 if (bootverbose) 1109 device_printf(ppc->ppc_dev, 1110 "not in parallel port mode\n"); 1111 return (-1); 1112 1113 case (WINB_PARALLEL | WINB_EPP_SPP): 1114 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1115 if (bootverbose) 1116 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1117 break; 1118 1119 case (WINB_PARALLEL | WINB_ECP): 1120 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1121 if (bootverbose) 1122 device_printf(ppc->ppc_dev, "ECP SPP\n"); 1123 break; 1124 1125 case (WINB_PARALLEL | WINB_ECP_EPP): 1126 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1127 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1128 1129 if (bootverbose) 1130 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n"); 1131 break; 1132 default: 1133 printf("%s: unknown case (0x%x)!\n", __func__, r); 1134 } 1135 1136 } else { 1137 /* mode forced */ 1138 1139 /* select CR9 and set PRTMODS2 bit */ 1140 outb(efir, 0x9); 1141 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1142 1143 /* select CR0 and reset PRTMODSx bits */ 1144 outb(efir, 0x0); 1145 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1146 1147 if (chipset_mode & PPB_ECP) { 1148 if (chipset_mode & PPB_EPP) { 1149 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1150 if (bootverbose) 1151 device_printf(ppc->ppc_dev, 1152 "ECP+EPP\n"); 1153 1154 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1155 1156 } else { 1157 outb(efdr, inb(efdr) | WINB_ECP); 1158 if (bootverbose) 1159 device_printf(ppc->ppc_dev, "ECP\n"); 1160 } 1161 } else { 1162 /* select EPP_SPP otherwise */ 1163 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1164 if (bootverbose) 1165 device_printf(ppc->ppc_dev, "EPP SPP\n"); 1166 } 1167 ppc->ppc_avm = chipset_mode; 1168 } 1169 1170 /* exit configuration mode */ 1171 outb(efer, 0xaa); 1172 1173 switch (ppc->ppc_type) { 1174 case PPC_TYPE_SMCLIKE: 1175 ppc_smclike_setmode(ppc, chipset_mode); 1176 break; 1177 default: 1178 ppc_generic_setmode(ppc, chipset_mode); 1179 break; 1180 } 1181 1182 return (chipset_mode); 1183 } 1184 #endif 1185 1186 /* 1187 * ppc_generic_detect 1188 */ 1189 static int 1190 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1191 { 1192 /* default to generic */ 1193 ppc->ppc_type = PPC_TYPE_GENERIC; 1194 1195 if (bootverbose) 1196 device_printf(ppc->ppc_dev, "SPP"); 1197 1198 /* first, check for ECP */ 1199 w_ecr(ppc, PPC_ECR_PS2); 1200 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1201 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1202 if (bootverbose) 1203 printf(" ECP "); 1204 1205 /* search for SMC style ECP+EPP mode */ 1206 w_ecr(ppc, PPC_ECR_EPP); 1207 } 1208 1209 /* try to reset EPP timeout bit */ 1210 if (ppc_check_epp_timeout(ppc)) { 1211 ppc->ppc_dtm |= PPB_EPP; 1212 1213 if (ppc->ppc_dtm & PPB_ECP) { 1214 /* SMC like chipset found */ 1215 ppc->ppc_model = SMC_LIKE; 1216 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1217 1218 if (bootverbose) 1219 printf(" ECP+EPP"); 1220 } else { 1221 if (bootverbose) 1222 printf(" EPP"); 1223 } 1224 } else { 1225 /* restore to standard mode */ 1226 w_ecr(ppc, PPC_ECR_STD); 1227 } 1228 1229 /* XXX try to detect NIBBLE and PS2 modes */ 1230 ppc->ppc_dtm |= PPB_NIBBLE; 1231 1232 if (chipset_mode) 1233 ppc->ppc_avm = chipset_mode; 1234 else 1235 ppc->ppc_avm = ppc->ppc_dtm; 1236 1237 if (bootverbose) 1238 printf("\n"); 1239 1240 switch (ppc->ppc_type) { 1241 case PPC_TYPE_SMCLIKE: 1242 ppc_smclike_setmode(ppc, chipset_mode); 1243 break; 1244 default: 1245 ppc_generic_setmode(ppc, chipset_mode); 1246 break; 1247 } 1248 1249 return (chipset_mode); 1250 } 1251 1252 /* 1253 * ppc_detect() 1254 * 1255 * mode is the mode suggested at boot 1256 */ 1257 static int 1258 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1259 1260 #ifdef PPC_PROBE_CHIPSET 1261 int i, mode; 1262 1263 /* list of supported chipsets */ 1264 int (*chipset_detect[])(struct ppc_data *, int) = { 1265 ppc_pc873xx_detect, 1266 ppc_smc37c66xgt_detect, 1267 ppc_w83877f_detect, 1268 ppc_smc37c935_detect, 1269 ppc_generic_detect, 1270 NULL 1271 }; 1272 #endif 1273 1274 /* if can't find the port and mode not forced return error */ 1275 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1276 return (EIO); /* failed, port not present */ 1277 1278 /* assume centronics compatible mode is supported */ 1279 ppc->ppc_avm = PPB_COMPATIBLE; 1280 1281 #ifdef PPC_PROBE_CHIPSET 1282 /* we have to differenciate available chipset modes, 1283 * chipset running modes and IEEE-1284 operating modes 1284 * 1285 * after detection, the port must support running in compatible mode 1286 */ 1287 if (ppc->ppc_flags & 0x40) { 1288 if (bootverbose) 1289 printf("ppc: chipset forced to generic\n"); 1290 #endif 1291 1292 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1293 1294 #ifdef PPC_PROBE_CHIPSET 1295 } else { 1296 for (i=0; chipset_detect[i] != NULL; i++) { 1297 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1298 ppc->ppc_mode = mode; 1299 break; 1300 } 1301 } 1302 } 1303 #endif 1304 1305 /* configure/detect ECP FIFO */ 1306 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1307 ppc_detect_fifo(ppc); 1308 1309 return (0); 1310 } 1311 1312 /* 1313 * ppc_exec_microseq() 1314 * 1315 * Execute a microsequence. 1316 * Microsequence mechanism is supposed to handle fast I/O operations. 1317 */ 1318 int 1319 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1320 { 1321 struct ppc_data *ppc = DEVTOSOFTC(dev); 1322 struct ppb_microseq *mi; 1323 char cc, *p; 1324 int i, iter, len; 1325 int error; 1326 1327 int reg; 1328 char mask; 1329 int accum = 0; 1330 char *ptr = NULL; 1331 1332 struct ppb_microseq *stack = NULL; 1333 1334 /* microsequence registers are equivalent to PC-like port registers */ 1335 1336 #define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1337 #define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1338 1339 #define INCR_PC (mi ++) /* increment program counter */ 1340 1341 PPC_ASSERT_LOCKED(ppc); 1342 mi = *p_msq; 1343 for (;;) { 1344 switch (mi->opcode) { 1345 case MS_OP_RSET: 1346 cc = r_reg(mi->arg[0].i, ppc); 1347 cc &= (char)mi->arg[2].i; /* clear mask */ 1348 cc |= (char)mi->arg[1].i; /* assert mask */ 1349 w_reg(mi->arg[0].i, ppc, cc); 1350 INCR_PC; 1351 break; 1352 1353 case MS_OP_RASSERT_P: 1354 reg = mi->arg[1].i; 1355 ptr = ppc->ppc_ptr; 1356 1357 if ((len = mi->arg[0].i) == MS_ACCUM) { 1358 accum = ppc->ppc_accum; 1359 for (; accum; accum--) 1360 w_reg(reg, ppc, *ptr++); 1361 ppc->ppc_accum = accum; 1362 } else 1363 for (i=0; i<len; i++) 1364 w_reg(reg, ppc, *ptr++); 1365 ppc->ppc_ptr = ptr; 1366 1367 INCR_PC; 1368 break; 1369 1370 case MS_OP_RFETCH_P: 1371 reg = mi->arg[1].i; 1372 mask = (char)mi->arg[2].i; 1373 ptr = ppc->ppc_ptr; 1374 1375 if ((len = mi->arg[0].i) == MS_ACCUM) { 1376 accum = ppc->ppc_accum; 1377 for (; accum; accum--) 1378 *ptr++ = r_reg(reg, ppc) & mask; 1379 ppc->ppc_accum = accum; 1380 } else 1381 for (i=0; i<len; i++) 1382 *ptr++ = r_reg(reg, ppc) & mask; 1383 ppc->ppc_ptr = ptr; 1384 1385 INCR_PC; 1386 break; 1387 1388 case MS_OP_RFETCH: 1389 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1390 (char)mi->arg[1].i; 1391 INCR_PC; 1392 break; 1393 1394 case MS_OP_RASSERT: 1395 case MS_OP_DELAY: 1396 1397 /* let's suppose the next instr. is the same */ 1398 prefetch: 1399 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1400 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1401 1402 if (mi->opcode == MS_OP_DELAY) { 1403 DELAY(mi->arg[0].i); 1404 INCR_PC; 1405 goto prefetch; 1406 } 1407 break; 1408 1409 case MS_OP_ADELAY: 1410 if (mi->arg[0].i) { 1411 PPC_UNLOCK(ppc); 1412 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1413 PPC_LOCK(ppc); 1414 } 1415 INCR_PC; 1416 break; 1417 1418 case MS_OP_TRIG: 1419 reg = mi->arg[0].i; 1420 iter = mi->arg[1].i; 1421 p = (char *)mi->arg[2].p; 1422 1423 /* XXX delay limited to 255 us */ 1424 for (i=0; i<iter; i++) { 1425 w_reg(reg, ppc, *p++); 1426 DELAY((unsigned char)*p++); 1427 } 1428 INCR_PC; 1429 break; 1430 1431 case MS_OP_SET: 1432 ppc->ppc_accum = mi->arg[0].i; 1433 INCR_PC; 1434 break; 1435 1436 case MS_OP_DBRA: 1437 if (--ppc->ppc_accum > 0) 1438 mi += mi->arg[0].i; 1439 INCR_PC; 1440 break; 1441 1442 case MS_OP_BRSET: 1443 cc = r_str(ppc); 1444 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1445 mi += mi->arg[1].i; 1446 INCR_PC; 1447 break; 1448 1449 case MS_OP_BRCLEAR: 1450 cc = r_str(ppc); 1451 if ((cc & (char)mi->arg[0].i) == 0) 1452 mi += mi->arg[1].i; 1453 INCR_PC; 1454 break; 1455 1456 case MS_OP_BRSTAT: 1457 cc = r_str(ppc); 1458 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1459 (char)mi->arg[0].i) 1460 mi += mi->arg[2].i; 1461 INCR_PC; 1462 break; 1463 1464 case MS_OP_C_CALL: 1465 /* 1466 * If the C call returns !0 then end the microseq. 1467 * The current state of ptr is passed to the C function 1468 */ 1469 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1470 return (error); 1471 1472 INCR_PC; 1473 break; 1474 1475 case MS_OP_PTR: 1476 ppc->ppc_ptr = (char *)mi->arg[0].p; 1477 INCR_PC; 1478 break; 1479 1480 case MS_OP_CALL: 1481 if (stack) 1482 panic("%s: too much calls", __func__); 1483 1484 if (mi->arg[0].p) { 1485 /* store the state of the actual 1486 * microsequence 1487 */ 1488 stack = mi; 1489 1490 /* jump to the new microsequence */ 1491 mi = (struct ppb_microseq *)mi->arg[0].p; 1492 } else 1493 INCR_PC; 1494 1495 break; 1496 1497 case MS_OP_SUBRET: 1498 /* retrieve microseq and pc state before the call */ 1499 mi = stack; 1500 1501 /* reset the stack */ 1502 stack = NULL; 1503 1504 /* XXX return code */ 1505 1506 INCR_PC; 1507 break; 1508 1509 case MS_OP_PUT: 1510 case MS_OP_GET: 1511 case MS_OP_RET: 1512 /* can't return to ppb level during the execution 1513 * of a submicrosequence */ 1514 if (stack) 1515 panic("%s: can't return to ppb level", 1516 __func__); 1517 1518 /* update pc for ppb level of execution */ 1519 *p_msq = mi; 1520 1521 /* return to ppb level of execution */ 1522 return (0); 1523 1524 default: 1525 panic("%s: unknown microsequence opcode 0x%x", 1526 __func__, mi->opcode); 1527 } 1528 } 1529 1530 /* unreached */ 1531 } 1532 1533 static void 1534 ppcintr(void *arg) 1535 { 1536 struct ppc_data *ppc = arg; 1537 u_char ctr, ecr, str; 1538 1539 /* 1540 * If we have any child interrupt handlers registered, let 1541 * them handle this interrupt. 1542 * 1543 * XXX: If DMA is in progress should we just complete that w/o 1544 * doing this? 1545 */ 1546 PPC_LOCK(ppc); 1547 if (ppc->ppc_intr_hook != NULL && 1548 ppc->ppc_intr_hook(ppc->ppc_intr_arg) == 0) { 1549 PPC_UNLOCK(ppc); 1550 return; 1551 } 1552 1553 str = r_str(ppc); 1554 ctr = r_ctr(ppc); 1555 ecr = r_ecr(ppc); 1556 1557 #if defined(PPC_DEBUG) && PPC_DEBUG > 1 1558 printf("![%x/%x/%x]", ctr, ecr, str); 1559 #endif 1560 1561 /* don't use ecp mode with IRQENABLE set */ 1562 if (ctr & IRQENABLE) { 1563 PPC_UNLOCK(ppc); 1564 return; 1565 } 1566 1567 /* interrupts are generated by nFault signal 1568 * only in ECP mode */ 1569 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1570 /* check if ppc driver has programmed the 1571 * nFault interrupt */ 1572 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1573 1574 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1575 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1576 } else { 1577 /* shall be handled by underlying layers XXX */ 1578 PPC_UNLOCK(ppc); 1579 return; 1580 } 1581 } 1582 1583 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1584 /* disable interrupts (should be done by hardware though) */ 1585 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1586 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1587 ecr = r_ecr(ppc); 1588 1589 /* check if DMA completed */ 1590 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1591 #ifdef PPC_DEBUG 1592 printf("a"); 1593 #endif 1594 /* stop DMA */ 1595 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1596 ecr = r_ecr(ppc); 1597 1598 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1599 #ifdef PPC_DEBUG 1600 printf("d"); 1601 #endif 1602 ppc->ppc_dmadone(ppc); 1603 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1604 1605 /* wakeup the waiting process */ 1606 wakeup(ppc); 1607 } 1608 } 1609 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1610 1611 /* classic interrupt I/O */ 1612 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1613 } 1614 PPC_UNLOCK(ppc); 1615 1616 return; 1617 } 1618 1619 int 1620 ppc_read(device_t dev, char *buf, int len, int mode) 1621 { 1622 return (EINVAL); 1623 } 1624 1625 int 1626 ppc_write(device_t dev, char *buf, int len, int how) 1627 { 1628 return (EINVAL); 1629 } 1630 1631 int 1632 ppc_reset_epp(device_t dev) 1633 { 1634 struct ppc_data *ppc = DEVTOSOFTC(dev); 1635 1636 PPC_ASSERT_LOCKED(ppc); 1637 ppc_reset_epp_timeout(ppc); 1638 1639 return 0; 1640 } 1641 1642 int 1643 ppc_setmode(device_t dev, int mode) 1644 { 1645 struct ppc_data *ppc = DEVTOSOFTC(dev); 1646 1647 PPC_ASSERT_LOCKED(ppc); 1648 switch (ppc->ppc_type) { 1649 case PPC_TYPE_SMCLIKE: 1650 return (ppc_smclike_setmode(ppc, mode)); 1651 break; 1652 1653 case PPC_TYPE_GENERIC: 1654 default: 1655 return (ppc_generic_setmode(ppc, mode)); 1656 break; 1657 } 1658 1659 /* not reached */ 1660 return (ENXIO); 1661 } 1662 1663 int 1664 ppc_probe(device_t dev, int rid) 1665 { 1666 #ifdef __i386__ 1667 static short next_bios_ppc = 0; 1668 #endif 1669 struct ppc_data *ppc; 1670 int error; 1671 rman_res_t port; 1672 1673 /* 1674 * Allocate the ppc_data structure. 1675 */ 1676 ppc = DEVTOSOFTC(dev); 1677 bzero(ppc, sizeof(struct ppc_data)); 1678 1679 ppc->rid_ioport = rid; 1680 1681 /* retrieve ISA parameters */ 1682 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1683 1684 #ifdef __i386__ 1685 /* 1686 * If port not specified, use bios list. 1687 */ 1688 if (error) { 1689 if ((next_bios_ppc < BIOS_MAX_PPC) && 1690 (*(BIOS_PORTS + next_bios_ppc) != 0)) { 1691 port = *(BIOS_PORTS + next_bios_ppc++); 1692 if (bootverbose) 1693 device_printf(dev, 1694 "parallel port found at 0x%jx\n", port); 1695 } else { 1696 device_printf(dev, "parallel port not found.\n"); 1697 return (ENXIO); 1698 } 1699 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1700 IO_LPTSIZE_EXTENDED); 1701 } 1702 #endif 1703 1704 /* IO port is mandatory */ 1705 1706 /* Try "extended" IO port range...*/ 1707 ppc->res_ioport = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 1708 &ppc->rid_ioport, 1709 IO_LPTSIZE_EXTENDED, 1710 RF_ACTIVE); 1711 1712 if (ppc->res_ioport != 0) { 1713 if (bootverbose) 1714 device_printf(dev, "using extended I/O port range\n"); 1715 } else { 1716 /* Failed? If so, then try the "normal" IO port range... */ 1717 ppc->res_ioport = bus_alloc_resource_anywhere(dev, 1718 SYS_RES_IOPORT, 1719 &ppc->rid_ioport, 1720 IO_LPTSIZE_NORMAL, 1721 RF_ACTIVE); 1722 if (ppc->res_ioport != 0) { 1723 if (bootverbose) 1724 device_printf(dev, "using normal I/O port range\n"); 1725 } else { 1726 if (bootverbose) 1727 device_printf(dev, "cannot reserve I/O port range\n"); 1728 goto error; 1729 } 1730 } 1731 1732 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1733 1734 ppc->ppc_flags = device_get_flags(dev); 1735 1736 if (!(ppc->ppc_flags & 0x20)) { 1737 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1738 &ppc->rid_irq, 1739 RF_SHAREABLE); 1740 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1741 &ppc->rid_drq, 1742 RF_ACTIVE); 1743 } 1744 1745 if (ppc->res_irq) 1746 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1747 if (ppc->res_drq) 1748 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1749 1750 ppc->ppc_dev = dev; 1751 ppc->ppc_model = GENERIC; 1752 1753 ppc->ppc_mode = PPB_COMPATIBLE; 1754 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1755 1756 ppc->ppc_type = PPC_TYPE_GENERIC; 1757 1758 /* 1759 * Try to detect the chipset and its mode. 1760 */ 1761 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1762 goto error; 1763 1764 return (0); 1765 1766 error: 1767 if (ppc->res_irq != 0) { 1768 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1769 ppc->res_irq); 1770 } 1771 if (ppc->res_ioport != 0) { 1772 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1773 ppc->res_ioport); 1774 } 1775 if (ppc->res_drq != 0) { 1776 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1777 ppc->res_drq); 1778 } 1779 return (ENXIO); 1780 } 1781 1782 int 1783 ppc_attach(device_t dev) 1784 { 1785 struct ppc_data *ppc = DEVTOSOFTC(dev); 1786 int error; 1787 1788 mtx_init(&ppc->ppc_lock, device_get_nameunit(dev), "ppc", MTX_DEF); 1789 1790 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1791 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1792 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1793 ppc_epp_protocol[ppc->ppc_epp] : ""); 1794 1795 if (ppc->ppc_fifo) 1796 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1797 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1798 1799 if (ppc->res_irq) { 1800 /* default to the tty mask for registration */ /* XXX */ 1801 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY | 1802 INTR_MPSAFE, NULL, ppcintr, ppc, &ppc->intr_cookie); 1803 if (error) { 1804 device_printf(dev, 1805 "failed to register interrupt handler: %d\n", 1806 error); 1807 mtx_destroy(&ppc->ppc_lock); 1808 return (error); 1809 } 1810 } 1811 1812 /* add ppbus as a child of this isa to parallel bridge */ 1813 ppc->ppbus = device_add_child(dev, "ppbus", -1); 1814 1815 /* 1816 * Probe the ppbus and attach devices found. 1817 */ 1818 device_probe_and_attach(ppc->ppbus); 1819 1820 return (0); 1821 } 1822 1823 int 1824 ppc_detach(device_t dev) 1825 { 1826 struct ppc_data *ppc = DEVTOSOFTC(dev); 1827 1828 if (ppc->res_irq == 0) { 1829 return (ENXIO); 1830 } 1831 1832 /* detach & delete all children */ 1833 device_delete_children(dev); 1834 1835 if (ppc->res_irq != 0) { 1836 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1837 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1838 ppc->res_irq); 1839 } 1840 if (ppc->res_ioport != 0) { 1841 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1842 ppc->res_ioport); 1843 } 1844 if (ppc->res_drq != 0) { 1845 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1846 ppc->res_drq); 1847 } 1848 1849 mtx_destroy(&ppc->ppc_lock); 1850 1851 return (0); 1852 } 1853 1854 u_char 1855 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1856 { 1857 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1858 1859 PPC_ASSERT_LOCKED(ppc); 1860 switch (iop) { 1861 case PPB_OUTSB_EPP: 1862 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1863 break; 1864 case PPB_OUTSW_EPP: 1865 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1866 break; 1867 case PPB_OUTSL_EPP: 1868 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1869 break; 1870 case PPB_INSB_EPP: 1871 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1872 break; 1873 case PPB_INSW_EPP: 1874 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1875 break; 1876 case PPB_INSL_EPP: 1877 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1878 break; 1879 case PPB_RDTR: 1880 return (r_dtr(ppc)); 1881 case PPB_RSTR: 1882 return (r_str(ppc)); 1883 case PPB_RCTR: 1884 return (r_ctr(ppc)); 1885 case PPB_REPP_A: 1886 return (r_epp_A(ppc)); 1887 case PPB_REPP_D: 1888 return (r_epp_D(ppc)); 1889 case PPB_RECR: 1890 return (r_ecr(ppc)); 1891 case PPB_RFIFO: 1892 return (r_fifo(ppc)); 1893 case PPB_WDTR: 1894 w_dtr(ppc, byte); 1895 break; 1896 case PPB_WSTR: 1897 w_str(ppc, byte); 1898 break; 1899 case PPB_WCTR: 1900 w_ctr(ppc, byte); 1901 break; 1902 case PPB_WEPP_A: 1903 w_epp_A(ppc, byte); 1904 break; 1905 case PPB_WEPP_D: 1906 w_epp_D(ppc, byte); 1907 break; 1908 case PPB_WECR: 1909 w_ecr(ppc, byte); 1910 break; 1911 case PPB_WFIFO: 1912 w_fifo(ppc, byte); 1913 break; 1914 default: 1915 panic("%s: unknown I/O operation", __func__); 1916 break; 1917 } 1918 1919 return (0); /* not significative */ 1920 } 1921 1922 int 1923 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1924 { 1925 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1926 1927 switch (index) { 1928 case PPC_IVAR_EPP_PROTO: 1929 PPC_ASSERT_LOCKED(ppc); 1930 *val = (u_long)ppc->ppc_epp; 1931 break; 1932 case PPC_IVAR_LOCK: 1933 *val = (uintptr_t)&ppc->ppc_lock; 1934 break; 1935 default: 1936 return (ENOENT); 1937 } 1938 1939 return (0); 1940 } 1941 1942 int 1943 ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val) 1944 { 1945 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1946 1947 switch (index) { 1948 case PPC_IVAR_INTR_HANDLER: 1949 PPC_ASSERT_LOCKED(ppc); 1950 if (dev != ppc->ppbus) 1951 return (EINVAL); 1952 if (val == 0) { 1953 ppc->ppc_intr_hook = NULL; 1954 break; 1955 } 1956 if (ppc->ppc_intr_hook != NULL) 1957 return (EBUSY); 1958 ppc->ppc_intr_hook = (void *)val; 1959 ppc->ppc_intr_arg = device_get_softc(dev); 1960 break; 1961 default: 1962 return (ENOENT); 1963 } 1964 1965 return (0); 1966 } 1967 1968 /* 1969 * We allow child devices to allocate an IRQ resource at rid 0 for their 1970 * interrupt handlers. 1971 */ 1972 struct resource * 1973 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 1974 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1975 { 1976 struct ppc_data *ppc = DEVTOSOFTC(bus); 1977 1978 switch (type) { 1979 case SYS_RES_IRQ: 1980 if (*rid == 0) 1981 return (ppc->res_irq); 1982 break; 1983 } 1984 return (NULL); 1985 } 1986 1987 int 1988 ppc_release_resource(device_t bus, device_t child, int type, int rid, 1989 struct resource *r) 1990 { 1991 #ifdef INVARIANTS 1992 struct ppc_data *ppc = DEVTOSOFTC(bus); 1993 #endif 1994 1995 switch (type) { 1996 case SYS_RES_IRQ: 1997 if (rid == 0) { 1998 KASSERT(r == ppc->res_irq, 1999 ("ppc child IRQ resource mismatch")); 2000 return (0); 2001 } 2002 break; 2003 } 2004 return (EINVAL); 2005 } 2006 2007 MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2008