1 /*- 2 * Copyright (c) 1997, 1998 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: ppc.c,v 1.16 1999/01/30 15:35:38 nsouch Exp $ 27 * 28 */ 29 #include "ppc.h" 30 31 #if NPPC > 0 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/conf.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 39 #include <machine/clock.h> 40 41 #include <vm/vm.h> 42 #include <vm/vm_param.h> 43 #include <vm/pmap.h> 44 45 #include <i386/isa/isa_device.h> 46 47 #include <dev/ppbus/ppbconf.h> 48 #include <dev/ppbus/ppb_msq.h> 49 50 #include <i386/isa/ppcreg.h> 51 52 #include "opt_ppc.h" 53 54 #define LOG_PPC(function, ppc, string) \ 55 if (bootverbose) printf("%s: %s\n", function, string) 56 57 static int ppcprobe(struct isa_device *); 58 static int ppcattach(struct isa_device *); 59 60 struct isa_driver ppcdriver = { 61 ppcprobe, ppcattach, "ppc" 62 }; 63 64 static struct ppc_data *ppcdata[NPPC]; 65 static int nppc = 0; 66 67 static char *ppc_types[] = { 68 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 69 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 70 }; 71 72 /* list of available modes */ 73 static char *ppc_avms[] = { 74 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 75 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 76 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 77 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 78 }; 79 80 /* list of current executing modes 81 * Note that few modes do not actually exist. 82 */ 83 static char *ppc_modes[] = { 84 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 85 "EPP", "EPP", "EPP", "ECP", 86 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 87 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 88 }; 89 90 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 91 92 /* 93 * BIOS printer list - used by BIOS probe. 94 */ 95 #define BIOS_PPC_PORTS 0x408 96 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 97 #define BIOS_MAX_PPC 4 98 99 /* 100 * All these functions are default actions for IN/OUT operations. 101 * They may be redefined if needed. 102 */ 103 static void ppc_outsb_epp(int unit, char *addr, int cnt) { 104 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 105 static void ppc_outsw_epp(int unit, char *addr, int cnt) { 106 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 107 static void ppc_outsl_epp(int unit, char *addr, int cnt) { 108 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 109 static void ppc_insb_epp(int unit, char *addr, int cnt) { 110 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 111 static void ppc_insw_epp(int unit, char *addr, int cnt) { 112 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 113 static void ppc_insl_epp(int unit, char *addr, int cnt) { 114 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 115 116 static u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); } 117 static u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); } 118 static u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); } 119 static u_char ppc_repp_A(int unit) { return r_epp_A(ppcdata[unit]); } 120 static u_char ppc_repp_D(int unit) { return r_epp_D(ppcdata[unit]); } 121 static u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); } 122 static u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); } 123 124 static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); } 125 static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); } 126 static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); } 127 static void ppc_wepp_A(int unit, char byte) { w_epp_A(ppcdata[unit], byte); } 128 static void ppc_wepp_D(int unit, char byte) { w_epp_D(ppcdata[unit], byte); } 129 static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); } 130 static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); } 131 132 static void ppc_reset_epp_timeout(int); 133 static void ppc_ecp_sync(int); 134 static ointhand2_t ppcintr; 135 136 static int ppc_exec_microseq(int, struct ppb_microseq **); 137 static int ppc_generic_setmode(int, int); 138 static int ppc_smclike_setmode(int, int); 139 140 static int ppc_read(int, char *, int, int); 141 static int ppc_write(int, char *, int, int); 142 143 static struct ppb_adapter ppc_smclike_adapter = { 144 145 0, /* no intr handler, filled by chipset dependent code */ 146 147 ppc_reset_epp_timeout, ppc_ecp_sync, 148 149 ppc_exec_microseq, 150 151 ppc_smclike_setmode, ppc_read, ppc_write, 152 153 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 154 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 155 156 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 157 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 158 }; 159 160 static struct ppb_adapter ppc_generic_adapter = { 161 162 0, /* no intr handler, filled by chipset dependent code */ 163 164 ppc_reset_epp_timeout, ppc_ecp_sync, 165 166 ppc_exec_microseq, 167 168 ppc_generic_setmode, ppc_read, ppc_write, 169 170 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 171 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 172 173 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 174 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 175 }; 176 177 /* 178 * ppc_ecp_sync() XXX 179 */ 180 static void 181 ppc_ecp_sync(int unit) { 182 183 struct ppc_data *ppc = ppcdata[unit]; 184 int i, r; 185 186 if (!(ppc->ppc_avm & PPB_ECP)) 187 return; 188 189 r = r_ecr(ppc); 190 if ((r & 0xe0) != PPC_ECR_EPP) 191 return; 192 193 for (i = 0; i < 100; i++) { 194 r = r_ecr(ppc); 195 if (r & 0x1) 196 return; 197 DELAY(100); 198 } 199 200 printf("ppc%d: ECP sync failed as data still " \ 201 "present in FIFO.\n", unit); 202 203 return; 204 } 205 206 /* 207 * ppc_detect_fifo() 208 * 209 * Detect parallel port FIFO 210 */ 211 static int 212 ppc_detect_fifo(struct ppc_data *ppc) 213 { 214 char ecr_sav; 215 char ctr_sav, ctr, cc; 216 short i; 217 218 /* save registers */ 219 ecr_sav = r_ecr(ppc); 220 ctr_sav = r_ctr(ppc); 221 222 /* enter ECP configuration mode, no interrupt, no DMA */ 223 w_ecr(ppc, 0xf4); 224 225 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 226 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 227 228 /* XXX 16 and 32 bits implementations not supported */ 229 if (ppc->ppc_pword != PPC_PWORD_8) { 230 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 231 goto error; 232 } 233 234 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 235 ctr = r_ctr(ppc); 236 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 237 238 /* enter ECP test mode, no interrupt, no DMA */ 239 w_ecr(ppc, 0xd4); 240 241 /* flush the FIFO */ 242 for (i=0; i<1024; i++) { 243 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 244 break; 245 cc = r_fifo(ppc); 246 } 247 248 if (i >= 1024) { 249 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 250 goto error; 251 } 252 253 /* enable interrupts, no DMA */ 254 w_ecr(ppc, 0xd0); 255 256 /* determine readIntrThreshold 257 * fill the FIFO until serviceIntr is set 258 */ 259 for (i=0; i<1024; i++) { 260 w_fifo(ppc, (char)i); 261 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 262 /* readThreshold reached */ 263 ppc->ppc_rthr = i+1; 264 } 265 if (r_ecr(ppc) & PPC_FIFO_FULL) { 266 ppc->ppc_fifo = i+1; 267 break; 268 } 269 } 270 271 if (i >= 1024) { 272 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 273 goto error; 274 } 275 276 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 277 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 278 w_ecr(ppc, 0xd0); /* enable interrupts */ 279 280 /* determine writeIntrThreshold 281 * empty the FIFO until serviceIntr is set 282 */ 283 for (i=ppc->ppc_fifo; i>0; i--) { 284 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 285 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 286 goto error; 287 } 288 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 289 /* writeIntrThreshold reached */ 290 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 291 } 292 /* if FIFO empty before the last byte, error */ 293 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 294 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 295 goto error; 296 } 297 } 298 299 /* FIFO must be empty after the last byte */ 300 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 301 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 302 goto error; 303 } 304 305 w_ctr(ppc, ctr_sav); 306 w_ecr(ppc, ecr_sav); 307 308 return (0); 309 310 error: 311 w_ctr(ppc, ctr_sav); 312 w_ecr(ppc, ecr_sav); 313 314 return (EINVAL); 315 } 316 317 static int 318 ppc_detect_port(struct ppc_data *ppc) 319 { 320 321 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 322 w_dtr(ppc, 0xaa); 323 if (r_dtr(ppc) != 0xaa) 324 return (0); 325 326 return (1); 327 } 328 329 /* 330 * ppc_pc873xx_detect 331 * 332 * Probe for a Natsemi PC873xx-family part. 333 * 334 * References in this function are to the National Semiconductor 335 * PC87332 datasheet TL/C/11930, May 1995 revision. 336 */ 337 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 338 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 339 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 340 341 static int pc873xx_regstab[] = { 342 PC873_FER, PC873_FAR, PC873_PTR, 343 PC873_FCR, PC873_PCR, PC873_PMC, 344 PC873_TUP, PC873_SID, PC873_PNP0, 345 PC873_PNP1, PC873_LPTBA, -1 346 }; 347 348 static char *pc873xx_rnametab[] = { 349 "FER", "FAR", "PTR", "FCR", "PCR", 350 "PMC", "TUP", "SID", "PNP0", "PNP1", 351 "LPTBA", NULL 352 }; 353 354 static int 355 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 356 { 357 static int index = 0; 358 int idport, irq; 359 int ptr, pcr, val, i; 360 361 while ((idport = pc873xx_basetab[index++])) { 362 363 /* XXX should check first to see if this location is already claimed */ 364 365 /* 366 * Pull the 873xx through the power-on ID cycle (2.2,1.). 367 * We can't use this to locate the chip as it may already have 368 * been used by the BIOS. 369 */ 370 (void)inb(idport); (void)inb(idport); 371 (void)inb(idport); (void)inb(idport); 372 373 /* 374 * Read the SID byte. Possible values are : 375 * 376 * 01010xxx PC87334 377 * 0001xxxx PC87332 378 * 01110xxx PC87306 379 */ 380 outb(idport, PC873_SID); 381 val = inb(idport + 1); 382 if ((val & 0xf0) == 0x10) { 383 ppc->ppc_type = NS_PC87332; 384 } else if ((val & 0xf8) == 0x70) { 385 ppc->ppc_type = NS_PC87306; 386 } else if ((val & 0xf8) == 0x50) { 387 ppc->ppc_type = NS_PC87334; 388 } else { 389 if (bootverbose && (val != 0xff)) 390 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 391 continue ; /* not recognised */ 392 } 393 394 /* print registers */ 395 if (bootverbose) { 396 printf("PC873xx"); 397 for (i=0; pc873xx_regstab[i] != -1; i++) { 398 outb(idport, pc873xx_regstab[i]); 399 printf(" %s=0x%x", pc873xx_rnametab[i], 400 inb(idport + 1) & 0xff); 401 } 402 printf("\n"); 403 } 404 405 /* 406 * We think we have one. Is it enabled and where we want it to be? 407 */ 408 outb(idport, PC873_FER); 409 val = inb(idport + 1); 410 if (!(val & PC873_PPENABLE)) { 411 if (bootverbose) 412 printf("PC873xx parallel port disabled\n"); 413 continue; 414 } 415 outb(idport, PC873_FAR); 416 val = inb(idport + 1) & 0x3; 417 /* XXX we should create a driver instance for every port found */ 418 if (pc873xx_porttab[val] != ppc->ppc_base) { 419 if (bootverbose) 420 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 421 pc873xx_porttab[val], ppc->ppc_base); 422 continue; 423 } 424 425 outb(idport, PC873_PTR); 426 ptr = inb(idport + 1); 427 428 /* get irq settings */ 429 if (ppc->ppc_base == 0x378) 430 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 431 else 432 irq = pc873xx_irqtab[val]; 433 434 if (bootverbose) 435 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 436 437 /* 438 * Check if irq settings are correct 439 */ 440 if (irq != ppc->ppc_irq) { 441 /* 442 * If the chipset is not locked and base address is 0x378, 443 * we have another chance 444 */ 445 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 446 if (ppc->ppc_irq == 7) { 447 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 448 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 449 } else { 450 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 451 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 452 } 453 if (bootverbose) 454 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 455 } else { 456 if (bootverbose) 457 printf("PC873xx sorry, can't change irq setting\n"); 458 } 459 } else { 460 if (bootverbose) 461 printf("PC873xx irq settings are correct\n"); 462 } 463 464 outb(idport, PC873_PCR); 465 pcr = inb(idport + 1); 466 467 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 468 if (bootverbose) 469 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 470 471 ppc->ppc_avm |= PPB_NIBBLE; 472 if (bootverbose) 473 printf(", NIBBLE"); 474 475 if (pcr & PC873_EPPEN) { 476 ppc->ppc_avm |= PPB_EPP; 477 478 if (bootverbose) 479 printf(", EPP"); 480 481 if (pcr & PC873_EPP19) 482 ppc->ppc_epp = EPP_1_9; 483 else 484 ppc->ppc_epp = EPP_1_7; 485 486 if ((ppc->ppc_type == NS_PC87332) && bootverbose) { 487 outb(idport, PC873_PTR); 488 ptr = inb(idport + 1); 489 if (ptr & PC873_EPPRDIR) 490 printf(", Regular mode"); 491 else 492 printf(", Automatic mode"); 493 } 494 } else if (pcr & PC873_ECPEN) { 495 ppc->ppc_avm |= PPB_ECP; 496 if (bootverbose) 497 printf(", ECP"); 498 499 if (pcr & PC873_ECPCLK) { /* XXX */ 500 ppc->ppc_avm |= PPB_PS2; 501 if (bootverbose) 502 printf(", PS/2"); 503 } 504 } else { 505 outb(idport, PC873_PTR); 506 ptr = inb(idport + 1); 507 if (ptr & PC873_EXTENDED) { 508 ppc->ppc_avm |= PPB_SPP; 509 if (bootverbose) 510 printf(", SPP"); 511 } 512 } 513 } else { 514 if (bootverbose) 515 printf("PC873xx unlocked"); 516 517 if (chipset_mode & PPB_ECP) { 518 if ((chipset_mode & PPB_EPP) && bootverbose) 519 printf(", ECP+EPP not supported"); 520 521 pcr &= ~PC873_EPPEN; 522 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 523 outb(idport + 1, pcr); 524 outb(idport + 1, pcr); 525 526 if (bootverbose) 527 printf(", ECP"); 528 529 } else if (chipset_mode & PPB_EPP) { 530 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 531 pcr |= (PC873_EPPEN | PC873_EPP19); 532 outb(idport + 1, pcr); 533 outb(idport + 1, pcr); 534 535 ppc->ppc_epp = EPP_1_9; /* XXX */ 536 537 if (bootverbose) 538 printf(", EPP1.9"); 539 540 /* enable automatic direction turnover */ 541 if (ppc->ppc_type == NS_PC87332) { 542 outb(idport, PC873_PTR); 543 ptr = inb(idport + 1); 544 ptr &= ~PC873_EPPRDIR; 545 outb(idport + 1, ptr); 546 outb(idport + 1, ptr); 547 548 if (bootverbose) 549 printf(", Automatic mode"); 550 } 551 } else { 552 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 553 outb(idport + 1, pcr); 554 outb(idport + 1, pcr); 555 556 /* configure extended bit in PTR */ 557 outb(idport, PC873_PTR); 558 ptr = inb(idport + 1); 559 560 if (chipset_mode & PPB_PS2) { 561 ptr |= PC873_EXTENDED; 562 563 if (bootverbose) 564 printf(", PS/2"); 565 566 } else { 567 /* default to NIBBLE mode */ 568 ptr &= ~PC873_EXTENDED; 569 570 if (bootverbose) 571 printf(", NIBBLE"); 572 } 573 outb(idport + 1, ptr); 574 outb(idport + 1, ptr); 575 } 576 577 ppc->ppc_avm = chipset_mode; 578 } 579 580 if (bootverbose) 581 printf("\n"); 582 583 ppc->ppc_link.adapter = &ppc_generic_adapter; 584 ppc_generic_setmode(ppc->ppc_unit, chipset_mode); 585 586 return(chipset_mode); 587 } 588 return(-1); 589 } 590 591 static int 592 ppc_check_epp_timeout(struct ppc_data *ppc) 593 { 594 ppc_reset_epp_timeout(ppc->ppc_unit); 595 596 return (!(r_str(ppc) & TIMEOUT)); 597 } 598 599 /* 600 * ppc_smc37c66xgt_detect 601 * 602 * SMC FDC37C66xGT configuration. 603 */ 604 static int 605 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 606 { 607 int s, i; 608 u_char r; 609 int type = -1; 610 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 611 612 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 613 614 615 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 616 617 /* 618 * Detection: enter configuration mode and read CRD register. 619 */ 620 621 s = splhigh(); 622 outb(csr, SMC665_iCODE); 623 outb(csr, SMC665_iCODE); 624 splx(s); 625 626 outb(csr, 0xd); 627 if (inb(cio) == 0x65) { 628 type = SMC_37C665GT; 629 goto config; 630 } 631 632 for (i = 0; i < 2; i++) { 633 s = splhigh(); 634 outb(csr, SMC666_iCODE); 635 outb(csr, SMC666_iCODE); 636 splx(s); 637 638 outb(csr, 0xd); 639 if (inb(cio) == 0x66) { 640 type = SMC_37C666GT; 641 break; 642 } 643 644 /* Another chance, CSR may be hard-configured to be at 0x370 */ 645 csr = SMC666_CSR; 646 } 647 648 config: 649 /* 650 * If chipset not found, do not continue. 651 */ 652 if (type == -1) 653 return (-1); 654 655 /* select CR1 */ 656 outb(csr, 0x1); 657 658 /* read the port's address: bits 0 and 1 of CR1 */ 659 r = inb(cio) & SMC_CR1_ADDR; 660 if (port_address[(int)r] != ppc->ppc_base) 661 return (-1); 662 663 ppc->ppc_type = type; 664 665 /* 666 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 667 * If SPP mode is detected, try to set ECP+EPP mode 668 */ 669 670 if (bootverbose) { 671 outb(csr, 0x1); 672 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 673 inb(cio) & 0xff); 674 675 outb(csr, 0x4); 676 printf(" CR4=0x%x", inb(cio) & 0xff); 677 } 678 679 /* select CR1 */ 680 outb(csr, 0x1); 681 682 if (!chipset_mode) { 683 /* autodetect mode */ 684 685 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 686 if (type == SMC_37C666GT) { 687 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 688 if (bootverbose) 689 printf(" configuration hardwired, supposing " \ 690 "ECP+EPP SPP"); 691 692 } else 693 if ((inb(cio) & SMC_CR1_MODE) == 0) { 694 /* already in extended parallel port mode, read CR4 */ 695 outb(csr, 0x4); 696 r = (inb(cio) & SMC_CR4_EMODE); 697 698 switch (r) { 699 case SMC_SPP: 700 ppc->ppc_avm |= PPB_SPP; 701 if (bootverbose) 702 printf(" SPP"); 703 break; 704 705 case SMC_EPPSPP: 706 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 707 if (bootverbose) 708 printf(" EPP SPP"); 709 break; 710 711 case SMC_ECP: 712 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 713 if (bootverbose) 714 printf(" ECP SPP"); 715 break; 716 717 case SMC_ECPEPP: 718 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 719 if (bootverbose) 720 printf(" ECP+EPP SPP"); 721 break; 722 } 723 } else { 724 /* not an extended port mode */ 725 ppc->ppc_avm |= PPB_SPP; 726 if (bootverbose) 727 printf(" SPP"); 728 } 729 730 } else { 731 /* mode forced */ 732 ppc->ppc_avm = chipset_mode; 733 734 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 735 if (type == SMC_37C666GT) 736 goto end_detect; 737 738 r = inb(cio); 739 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 740 /* do not use ECP when the mode is not forced to */ 741 outb(cio, r | SMC_CR1_MODE); 742 if (bootverbose) 743 printf(" SPP"); 744 } else { 745 /* an extended mode is selected */ 746 outb(cio, r & ~SMC_CR1_MODE); 747 748 /* read CR4 register and reset mode field */ 749 outb(csr, 0x4); 750 r = inb(cio) & ~SMC_CR4_EMODE; 751 752 if (chipset_mode & PPB_ECP) { 753 if (chipset_mode & PPB_EPP) { 754 outb(cio, r | SMC_ECPEPP); 755 if (bootverbose) 756 printf(" ECP+EPP"); 757 } else { 758 outb(cio, r | SMC_ECP); 759 if (bootverbose) 760 printf(" ECP"); 761 } 762 } else { 763 /* PPB_EPP is set */ 764 outb(cio, r | SMC_EPPSPP); 765 if (bootverbose) 766 printf(" EPP SPP"); 767 } 768 } 769 ppc->ppc_avm = chipset_mode; 770 } 771 772 /* set FIFO threshold to 16 */ 773 if (ppc->ppc_avm & PPB_ECP) { 774 /* select CRA */ 775 outb(csr, 0xa); 776 outb(cio, 16); 777 } 778 779 end_detect: 780 781 if (bootverbose) 782 printf ("\n"); 783 784 if (ppc->ppc_avm & PPB_EPP) { 785 /* select CR4 */ 786 outb(csr, 0x4); 787 r = inb(cio); 788 789 /* 790 * Set the EPP protocol... 791 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 792 */ 793 if (ppc->ppc_epp == EPP_1_9) 794 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 795 else 796 outb(cio, (r | SMC_CR4_EPPTYPE)); 797 } 798 799 /* end config mode */ 800 outb(csr, 0xaa); 801 802 ppc->ppc_link.adapter = &ppc_smclike_adapter; 803 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode); 804 805 return (chipset_mode); 806 } 807 808 /* 809 * Winbond W83877F stuff 810 * 811 * EFER: extended function enable register 812 * EFIR: extended function index register 813 * EFDR: extended function data register 814 */ 815 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 816 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 817 818 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 819 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 820 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 821 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 822 823 static int 824 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 825 { 826 int i, j, efer; 827 unsigned char r, hefere, hefras; 828 829 for (i = 0; i < 4; i ++) { 830 /* first try to enable configuration registers */ 831 efer = w83877f_efers[i]; 832 833 /* write the key to the EFER */ 834 for (j = 0; j < w83877f_keyiter[i]; j ++) 835 outb (efer, w83877f_keys[i]); 836 837 /* then check HEFERE and HEFRAS bits */ 838 outb (efir, 0x0c); 839 hefere = inb(efdr) & WINB_HEFERE; 840 841 outb (efir, 0x16); 842 hefras = inb(efdr) & WINB_HEFRAS; 843 844 /* 845 * HEFRAS HEFERE 846 * 0 1 write 89h to 250h (power-on default) 847 * 1 0 write 86h twice to 3f0h 848 * 1 1 write 87h twice to 3f0h 849 * 0 0 write 88h to 250h 850 */ 851 if ((hefere | hefras) == w83877f_hefs[i]) 852 goto found; 853 } 854 855 return (-1); /* failed */ 856 857 found: 858 /* check base port address - read from CR23 */ 859 outb(efir, 0x23); 860 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 861 return (-1); 862 863 /* read CHIP ID from CR9/bits0-3 */ 864 outb(efir, 0x9); 865 866 switch (inb(efdr) & WINB_CHIPID) { 867 case WINB_W83877F_ID: 868 ppc->ppc_type = WINB_W83877F; 869 break; 870 871 case WINB_W83877AF_ID: 872 ppc->ppc_type = WINB_W83877AF; 873 break; 874 875 default: 876 ppc->ppc_type = WINB_UNKNOWN; 877 } 878 879 if (bootverbose) { 880 /* dump of registers */ 881 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 882 for (i = 0; i <= 0xd; i ++) { 883 outb(efir, i); 884 printf("0x%x ", inb(efdr)); 885 } 886 for (i = 0x10; i <= 0x17; i ++) { 887 outb(efir, i); 888 printf("0x%x ", inb(efdr)); 889 } 890 outb(efir, 0x1e); 891 printf("0x%x ", inb(efdr)); 892 for (i = 0x20; i <= 0x29; i ++) { 893 outb(efir, i); 894 printf("0x%x ", inb(efdr)); 895 } 896 printf("\n"); 897 printf("ppc%d:", ppc->ppc_unit); 898 } 899 900 ppc->ppc_link.adapter = &ppc_generic_adapter; 901 902 if (!chipset_mode) { 903 /* autodetect mode */ 904 905 /* select CR0 */ 906 outb(efir, 0x0); 907 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 908 909 /* select CR9 */ 910 outb(efir, 0x9); 911 r |= (inb(efdr) & WINB_PRTMODS2); 912 913 switch (r) { 914 case WINB_W83757: 915 if (bootverbose) 916 printf("ppc%d: W83757 compatible mode\n", 917 ppc->ppc_unit); 918 return (-1); /* generic or SMC-like */ 919 920 case WINB_EXTFDC: 921 case WINB_EXTADP: 922 case WINB_EXT2FDD: 923 case WINB_JOYSTICK: 924 if (bootverbose) 925 printf(" not in parallel port mode\n"); 926 return (-1); 927 928 case (WINB_PARALLEL | WINB_EPP_SPP): 929 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 930 if (bootverbose) 931 printf(" EPP SPP"); 932 break; 933 934 case (WINB_PARALLEL | WINB_ECP): 935 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 936 if (bootverbose) 937 printf(" ECP SPP"); 938 break; 939 940 case (WINB_PARALLEL | WINB_ECP_EPP): 941 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 942 ppc->ppc_link.adapter = &ppc_smclike_adapter; 943 944 if (bootverbose) 945 printf(" ECP+EPP SPP"); 946 break; 947 default: 948 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 949 } 950 951 } else { 952 /* mode forced */ 953 954 /* select CR9 and set PRTMODS2 bit */ 955 outb(efir, 0x9); 956 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 957 958 /* select CR0 and reset PRTMODSx bits */ 959 outb(efir, 0x0); 960 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 961 962 if (chipset_mode & PPB_ECP) { 963 if (chipset_mode & PPB_EPP) { 964 outb(efdr, inb(efdr) | WINB_ECP_EPP); 965 if (bootverbose) 966 printf(" ECP+EPP"); 967 968 ppc->ppc_link.adapter = &ppc_smclike_adapter; 969 970 } else { 971 outb(efdr, inb(efdr) | WINB_ECP); 972 if (bootverbose) 973 printf(" ECP"); 974 } 975 } else { 976 /* select EPP_SPP otherwise */ 977 outb(efdr, inb(efdr) | WINB_EPP_SPP); 978 if (bootverbose) 979 printf(" EPP SPP"); 980 } 981 ppc->ppc_avm = chipset_mode; 982 } 983 984 if (bootverbose) 985 printf("\n"); 986 987 /* exit configuration mode */ 988 outb(efer, 0xaa); 989 990 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 991 992 return (chipset_mode); 993 } 994 995 /* 996 * ppc_generic_detect 997 */ 998 static int 999 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1000 { 1001 /* default to generic */ 1002 ppc->ppc_link.adapter = &ppc_generic_adapter; 1003 1004 if (bootverbose) 1005 printf("ppc%d:", ppc->ppc_unit); 1006 1007 if (!chipset_mode) { 1008 /* first, check for ECP */ 1009 w_ecr(ppc, PPC_ECR_PS2); 1010 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1011 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1012 if (bootverbose) 1013 printf(" ECP SPP"); 1014 1015 /* search for SMC style ECP+EPP mode */ 1016 w_ecr(ppc, PPC_ECR_EPP); 1017 } 1018 1019 /* try to reset EPP timeout bit */ 1020 if (ppc_check_epp_timeout(ppc)) { 1021 ppc->ppc_avm |= PPB_EPP; 1022 1023 if (ppc->ppc_avm & PPB_ECP) { 1024 /* SMC like chipset found */ 1025 ppc->ppc_type = SMC_LIKE; 1026 ppc->ppc_link.adapter = &ppc_smclike_adapter; 1027 1028 if (bootverbose) 1029 printf(" ECP+EPP"); 1030 } else { 1031 if (bootverbose) 1032 printf(" EPP"); 1033 } 1034 } else { 1035 /* restore to standard mode */ 1036 w_ecr(ppc, PPC_ECR_STD); 1037 } 1038 1039 /* XXX try to detect NIBBLE and PS2 modes */ 1040 ppc->ppc_avm |= PPB_NIBBLE; 1041 1042 if (bootverbose) 1043 printf(" SPP"); 1044 1045 } else { 1046 ppc->ppc_avm = chipset_mode; 1047 } 1048 1049 if (bootverbose) 1050 printf("\n"); 1051 1052 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 1053 1054 return (chipset_mode); 1055 } 1056 1057 /* 1058 * ppc_detect() 1059 * 1060 * mode is the mode suggested at boot 1061 */ 1062 static int 1063 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1064 1065 int i, mode; 1066 1067 /* list of supported chipsets */ 1068 int (*chipset_detect[])(struct ppc_data *, int) = { 1069 ppc_pc873xx_detect, 1070 ppc_smc37c66xgt_detect, 1071 ppc_w83877f_detect, 1072 ppc_generic_detect, 1073 NULL 1074 }; 1075 1076 /* if can't find the port and mode not forced return error */ 1077 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1078 return (EIO); /* failed, port not present */ 1079 1080 /* assume centronics compatible mode is supported */ 1081 ppc->ppc_avm = PPB_COMPATIBLE; 1082 1083 /* we have to differenciate available chipset modes, 1084 * chipset running modes and IEEE-1284 operating modes 1085 * 1086 * after detection, the port must support running in compatible mode 1087 */ 1088 if (ppc->ppc_flags & 0x40) { 1089 if (bootverbose) 1090 printf("ppc: chipset forced to generic\n"); 1091 1092 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1093 1094 } else { 1095 for (i=0; chipset_detect[i] != NULL; i++) { 1096 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1097 ppc->ppc_mode = mode; 1098 break; 1099 } 1100 } 1101 } 1102 1103 /* configure/detect ECP FIFO */ 1104 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1105 ppc_detect_fifo(ppc); 1106 1107 return (0); 1108 } 1109 1110 /* 1111 * ppc_exec_microseq() 1112 * 1113 * Execute a microsequence. 1114 * Microsequence mechanism is supposed to handle fast I/O operations. 1115 */ 1116 static int 1117 ppc_exec_microseq(int unit, struct ppb_microseq **p_msq) 1118 { 1119 struct ppc_data *ppc = ppcdata[unit]; 1120 struct ppb_microseq *mi; 1121 char cc, *p; 1122 int i, iter, len; 1123 int error; 1124 1125 register int reg; 1126 register char mask; 1127 register int accum = 0; 1128 register char *ptr = 0; 1129 1130 struct ppb_microseq *stack = 0; 1131 1132 /* microsequence registers are equivalent to PC-like port registers */ 1133 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1134 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1135 1136 #define INCR_PC (mi ++) /* increment program counter */ 1137 1138 mi = *p_msq; 1139 for (;;) { 1140 switch (mi->opcode) { 1141 case MS_OP_RSET: 1142 cc = r_reg(mi->arg[0].i, ppc); 1143 cc &= (char)mi->arg[2].i; /* clear mask */ 1144 cc |= (char)mi->arg[1].i; /* assert mask */ 1145 w_reg(mi->arg[0].i, ppc, cc); 1146 INCR_PC; 1147 break; 1148 1149 case MS_OP_RASSERT_P: 1150 reg = mi->arg[1].i; 1151 ptr = ppc->ppc_ptr; 1152 1153 if ((len = mi->arg[0].i) == MS_ACCUM) { 1154 accum = ppc->ppc_accum; 1155 for (; accum; accum--) 1156 w_reg(reg, ppc, *ptr++); 1157 ppc->ppc_accum = accum; 1158 } else 1159 for (i=0; i<len; i++) 1160 w_reg(reg, ppc, *ptr++); 1161 ppc->ppc_ptr = ptr; 1162 1163 INCR_PC; 1164 break; 1165 1166 case MS_OP_RFETCH_P: 1167 reg = mi->arg[1].i; 1168 mask = (char)mi->arg[2].i; 1169 ptr = ppc->ppc_ptr; 1170 1171 if ((len = mi->arg[0].i) == MS_ACCUM) { 1172 accum = ppc->ppc_accum; 1173 for (; accum; accum--) 1174 *ptr++ = r_reg(reg, ppc) & mask; 1175 ppc->ppc_accum = accum; 1176 } else 1177 for (i=0; i<len; i++) 1178 *ptr++ = r_reg(reg, ppc) & mask; 1179 ppc->ppc_ptr = ptr; 1180 1181 INCR_PC; 1182 break; 1183 1184 case MS_OP_RFETCH: 1185 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1186 (char)mi->arg[1].i; 1187 INCR_PC; 1188 break; 1189 1190 case MS_OP_RASSERT: 1191 case MS_OP_DELAY: 1192 1193 /* let's suppose the next instr. is the same */ 1194 prefetch: 1195 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1196 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1197 1198 if (mi->opcode == MS_OP_DELAY) { 1199 DELAY(mi->arg[0].i); 1200 INCR_PC; 1201 goto prefetch; 1202 } 1203 break; 1204 1205 case MS_OP_ADELAY: 1206 if (mi->arg[0].i) 1207 tsleep(NULL, PPBPRI, "ppbdelay", 1208 mi->arg[0].i * (hz/1000)); 1209 INCR_PC; 1210 break; 1211 1212 case MS_OP_TRIG: 1213 reg = mi->arg[0].i; 1214 iter = mi->arg[1].i; 1215 p = (char *)mi->arg[2].p; 1216 1217 /* XXX delay limited to 255 us */ 1218 for (i=0; i<iter; i++) { 1219 w_reg(reg, ppc, *p++); 1220 DELAY((unsigned char)*p++); 1221 } 1222 INCR_PC; 1223 break; 1224 1225 case MS_OP_SET: 1226 ppc->ppc_accum = mi->arg[0].i; 1227 INCR_PC; 1228 break; 1229 1230 case MS_OP_DBRA: 1231 if (--ppc->ppc_accum > 0) 1232 mi += mi->arg[0].i; 1233 INCR_PC; 1234 break; 1235 1236 case MS_OP_BRSET: 1237 cc = r_str(ppc); 1238 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1239 mi += mi->arg[1].i; 1240 INCR_PC; 1241 break; 1242 1243 case MS_OP_BRCLEAR: 1244 cc = r_str(ppc); 1245 if ((cc & (char)mi->arg[0].i) == 0) 1246 mi += mi->arg[1].i; 1247 INCR_PC; 1248 break; 1249 1250 case MS_OP_BRSTAT: 1251 cc = r_str(ppc); 1252 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1253 (char)mi->arg[0].i) 1254 mi += mi->arg[2].i; 1255 INCR_PC; 1256 break; 1257 1258 case MS_OP_C_CALL: 1259 /* 1260 * If the C call returns !0 then end the microseq. 1261 * The current state of ptr is passed to the C function 1262 */ 1263 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1264 return (error); 1265 1266 INCR_PC; 1267 break; 1268 1269 case MS_OP_PTR: 1270 ppc->ppc_ptr = (char *)mi->arg[0].p; 1271 INCR_PC; 1272 break; 1273 1274 case MS_OP_CALL: 1275 if (stack) 1276 panic("%s: too much calls", __FUNCTION__); 1277 1278 if (mi->arg[0].p) { 1279 /* store the state of the actual 1280 * microsequence 1281 */ 1282 stack = mi; 1283 1284 /* jump to the new microsequence */ 1285 mi = (struct ppb_microseq *)mi->arg[0].p; 1286 } else 1287 INCR_PC; 1288 1289 break; 1290 1291 case MS_OP_SUBRET: 1292 /* retrieve microseq and pc state before the call */ 1293 mi = stack; 1294 1295 /* reset the stack */ 1296 stack = 0; 1297 1298 /* XXX return code */ 1299 1300 INCR_PC; 1301 break; 1302 1303 case MS_OP_PUT: 1304 case MS_OP_GET: 1305 case MS_OP_RET: 1306 /* can't return to ppb level during the execution 1307 * of a submicrosequence */ 1308 if (stack) 1309 panic("%s: can't return to ppb level", 1310 __FUNCTION__); 1311 1312 /* update pc for ppb level of execution */ 1313 *p_msq = mi; 1314 1315 /* return to ppb level of execution */ 1316 return (0); 1317 1318 default: 1319 panic("%s: unknown microsequence opcode 0x%x", 1320 __FUNCTION__, mi->opcode); 1321 } 1322 } 1323 1324 /* unreached */ 1325 } 1326 1327 static void 1328 ppcintr(int unit) 1329 { 1330 struct ppc_data *ppc = ppcdata[unit]; 1331 char ctr, ecr; 1332 1333 ctr = r_ctr(ppc); 1334 ecr = r_ecr(ppc); 1335 1336 #ifdef PPC_DEBUG 1337 printf("!"); 1338 #endif 1339 1340 /* don't use ecp mode with IRQENABLE set */ 1341 if (ctr & IRQENABLE) { 1342 /* call upper code */ 1343 ppb_intr(&ppc->ppc_link); 1344 return; 1345 } 1346 1347 if (ctr & nFAULT) { 1348 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1349 1350 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1351 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1352 } else { 1353 /* call upper code */ 1354 ppb_intr(&ppc->ppc_link); 1355 return; 1356 } 1357 } 1358 1359 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1360 /* disable interrupts (should be done by hardware though) */ 1361 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1362 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1363 ecr = r_ecr(ppc); 1364 1365 /* check if DMA completed */ 1366 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1367 #ifdef PPC_DEBUG 1368 printf("a"); 1369 #endif 1370 /* stop DMA */ 1371 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1372 ecr = r_ecr(ppc); 1373 1374 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1375 #ifdef PPC_DEBUG 1376 printf("d"); 1377 #endif 1378 isa_dmadone( 1379 ppc->ppc_dmaflags, 1380 ppc->ppc_dmaddr, 1381 ppc->ppc_dmacnt, 1382 ppc->ppc_dmachan); 1383 1384 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1385 1386 /* wakeup the waiting process */ 1387 wakeup((caddr_t)ppc); 1388 } 1389 } 1390 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1391 1392 /* classic interrupt I/O */ 1393 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1394 1395 } 1396 1397 return; 1398 } 1399 1400 static int 1401 ppc_read(int unit, char *buf, int len, int mode) 1402 { 1403 return (EINVAL); 1404 } 1405 1406 /* 1407 * Call this function if you want to send data in any advanced mode 1408 * of your parallel port: FIFO, DMA 1409 * 1410 * If what you want is not possible (no ECP, no DMA...), 1411 * EINVAL is returned 1412 */ 1413 static int 1414 ppc_write(int unit, char *buf, int len, int how) 1415 { 1416 struct ppc_data *ppc = ppcdata[unit]; 1417 char ecr, ecr_sav, ctr, ctr_sav; 1418 int s, error = 0; 1419 int spin; 1420 1421 #ifdef PPC_DEBUG 1422 printf("w"); 1423 #endif 1424 1425 ecr_sav = r_ecr(ppc); 1426 ctr_sav = r_ctr(ppc); 1427 1428 /* 1429 * Send buffer with DMA, FIFO and interrupts 1430 */ 1431 if (ppc->ppc_avm & PPB_ECP) { 1432 1433 if (ppc->ppc_dmachan >= 0) { 1434 1435 /* byte mode, no intr, no DMA, dir=0, flush fifo 1436 */ 1437 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1438 w_ecr(ppc, ecr); 1439 1440 /* disable nAck interrupts */ 1441 ctr = r_ctr(ppc); 1442 ctr &= ~IRQENABLE; 1443 w_ctr(ppc, ctr); 1444 1445 ppc->ppc_dmaflags = 0; 1446 ppc->ppc_dmaddr = (caddr_t)buf; 1447 ppc->ppc_dmacnt = (u_int)len; 1448 1449 switch (ppc->ppc_mode) { 1450 case PPB_COMPATIBLE: 1451 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1452 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1453 break; 1454 case PPB_ECP: 1455 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1456 break; 1457 default: 1458 error = EINVAL; 1459 goto error; 1460 } 1461 1462 w_ecr(ppc, ecr); 1463 ecr = r_ecr(ppc); 1464 1465 /* enter splhigh() not to be preempted 1466 * by the dma interrupt, we may miss 1467 * the wakeup otherwise 1468 */ 1469 s = splhigh(); 1470 1471 ppc->ppc_dmastat = PPC_DMA_INIT; 1472 1473 /* enable interrupts */ 1474 ecr &= ~PPC_SERVICE_INTR; 1475 ppc->ppc_irqstat = PPC_IRQ_DMA; 1476 w_ecr(ppc, ecr); 1477 1478 isa_dmastart( 1479 ppc->ppc_dmaflags, 1480 ppc->ppc_dmaddr, 1481 ppc->ppc_dmacnt, 1482 ppc->ppc_dmachan); 1483 #ifdef PPC_DEBUG 1484 printf("s%d", ppc->ppc_dmacnt); 1485 #endif 1486 ppc->ppc_dmastat = PPC_DMA_STARTED; 1487 1488 /* Wait for the DMA completed interrupt. We hope we won't 1489 * miss it, otherwise a signal will be necessary to unlock the 1490 * process. 1491 */ 1492 do { 1493 /* release CPU */ 1494 error = tsleep((caddr_t)ppc, 1495 PPBPRI | PCATCH, "ppcdma", 0); 1496 1497 } while (error == EWOULDBLOCK); 1498 1499 splx(s); 1500 1501 if (error) { 1502 #ifdef PPC_DEBUG 1503 printf("i"); 1504 #endif 1505 /* stop DMA */ 1506 isa_dmadone( 1507 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1508 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1509 1510 /* no dma, no interrupt, flush the fifo */ 1511 w_ecr(ppc, PPC_ECR_RESET); 1512 1513 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1514 goto error; 1515 } 1516 1517 /* wait for an empty fifo */ 1518 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1519 1520 for (spin=100; spin; spin--) 1521 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1522 goto fifo_empty; 1523 #ifdef PPC_DEBUG 1524 printf("Z"); 1525 #endif 1526 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1527 if (error != EWOULDBLOCK) { 1528 #ifdef PPC_DEBUG 1529 printf("I"); 1530 #endif 1531 /* no dma, no interrupt, flush the fifo */ 1532 w_ecr(ppc, PPC_ECR_RESET); 1533 1534 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1535 error = EINTR; 1536 goto error; 1537 } 1538 } 1539 1540 fifo_empty: 1541 /* no dma, no interrupt, flush the fifo */ 1542 w_ecr(ppc, PPC_ECR_RESET); 1543 1544 } else 1545 error = EINVAL; /* XXX we should FIFO and 1546 * interrupts */ 1547 } else 1548 error = EINVAL; 1549 1550 error: 1551 1552 /* PDRQ must be kept unasserted until nPDACK is 1553 * deasserted for a minimum of 350ns (SMC datasheet) 1554 * 1555 * Consequence may be a FIFO that never empty 1556 */ 1557 DELAY(1); 1558 1559 w_ecr(ppc, ecr_sav); 1560 w_ctr(ppc, ctr_sav); 1561 1562 return (error); 1563 } 1564 1565 /* 1566 * Configure current operating mode 1567 */ 1568 static int 1569 ppc_generic_setmode(int unit, int mode) 1570 { 1571 struct ppc_data *ppc = ppcdata[unit]; 1572 u_char ecr = 0; 1573 1574 /* check if mode is available */ 1575 if (mode && !(ppc->ppc_avm & mode)) 1576 return (EINVAL); 1577 1578 /* if ECP mode, configure ecr register */ 1579 if (ppc->ppc_avm & PPB_ECP) { 1580 /* return to byte mode (keeping direction bit), 1581 * no interrupt, no DMA to be able to change to 1582 * ECP 1583 */ 1584 w_ecr(ppc, PPC_ECR_RESET); 1585 ecr = PPC_DISABLE_INTR; 1586 1587 if (mode & PPB_EPP) 1588 return (EINVAL); 1589 else if (mode & PPB_ECP) 1590 /* select ECP mode */ 1591 ecr |= PPC_ECR_ECP; 1592 else if (mode & PPB_PS2) 1593 /* select PS2 mode with ECP */ 1594 ecr |= PPC_ECR_PS2; 1595 else 1596 /* select COMPATIBLE/NIBBLE mode */ 1597 ecr |= PPC_ECR_STD; 1598 1599 w_ecr(ppc, ecr); 1600 } 1601 1602 ppc->ppc_mode = mode; 1603 1604 return (0); 1605 } 1606 1607 /* 1608 * The ppc driver is free to choose options like FIFO or DMA 1609 * if ECP mode is available. 1610 * 1611 * The 'RAW' option allows the upper drivers to force the ppc mode 1612 * even with FIFO, DMA available. 1613 */ 1614 int 1615 ppc_smclike_setmode(int unit, int mode) 1616 { 1617 struct ppc_data *ppc = ppcdata[unit]; 1618 u_char ecr = 0; 1619 1620 /* check if mode is available */ 1621 if (mode && !(ppc->ppc_avm & mode)) 1622 return (EINVAL); 1623 1624 /* if ECP mode, configure ecr register */ 1625 if (ppc->ppc_avm & PPB_ECP) { 1626 /* return to byte mode (keeping direction bit), 1627 * no interrupt, no DMA to be able to change to 1628 * ECP or EPP mode 1629 */ 1630 w_ecr(ppc, PPC_ECR_RESET); 1631 ecr = PPC_DISABLE_INTR; 1632 1633 if (mode & PPB_EPP) 1634 /* select EPP mode */ 1635 ecr |= PPC_ECR_EPP; 1636 else if (mode & PPB_ECP) 1637 /* select ECP mode */ 1638 ecr |= PPC_ECR_ECP; 1639 else if (mode & PPB_PS2) 1640 /* select PS2 mode with ECP */ 1641 ecr |= PPC_ECR_PS2; 1642 else 1643 /* select COMPATIBLE/NIBBLE mode */ 1644 ecr |= PPC_ECR_STD; 1645 1646 w_ecr(ppc, ecr); 1647 } 1648 1649 ppc->ppc_mode = mode; 1650 1651 return (0); 1652 } 1653 1654 /* 1655 * EPP timeout, according to the PC87332 manual 1656 * Semantics of clearing EPP timeout bit. 1657 * PC87332 - reading SPP_STR does it... 1658 * SMC - write 1 to EPP timeout bit XXX 1659 * Others - (?) write 0 to EPP timeout bit 1660 */ 1661 static void 1662 ppc_reset_epp_timeout(int unit) 1663 { 1664 struct ppc_data *ppc = ppcdata[unit]; 1665 register char r; 1666 1667 r = r_str(ppc); 1668 w_str(ppc, r | 0x1); 1669 w_str(ppc, r & 0xfe); 1670 1671 return; 1672 } 1673 1674 static int 1675 ppcprobe(struct isa_device *dvp) 1676 { 1677 static short next_bios_ppc = 0; 1678 struct ppc_data *ppc; 1679 1680 /* 1681 * If port not specified, use bios list. 1682 */ 1683 if(dvp->id_iobase < 0) { 1684 if((next_bios_ppc < BIOS_MAX_PPC) && 1685 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1686 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++); 1687 if (bootverbose) 1688 printf("ppc: parallel port found at 0x%x\n", 1689 dvp->id_iobase); 1690 } else 1691 return (0); 1692 } 1693 1694 /* 1695 * Port was explicitly specified. 1696 * This allows probing of ports unknown to the BIOS. 1697 */ 1698 1699 /* 1700 * Allocate the ppc_data structure. 1701 */ 1702 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT); 1703 if (!ppc) { 1704 printf("ppc: cannot malloc!\n"); 1705 goto error; 1706 } 1707 bzero(ppc, sizeof(struct ppc_data)); 1708 1709 ppc->ppc_base = dvp->id_iobase; 1710 ppc->ppc_unit = dvp->id_unit; 1711 ppc->ppc_type = GENERIC; 1712 1713 /* store boot flags */ 1714 ppc->ppc_flags = dvp->id_flags; 1715 1716 ppc->ppc_mode = PPB_COMPATIBLE; 1717 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4; 1718 1719 /* 1720 * XXX Try and detect if interrupts are working 1721 */ 1722 if (!(dvp->id_flags & 0x20)) 1723 ppc->ppc_irq = ffs(dvp->id_irq) - 1; 1724 1725 ppc->ppc_dmachan = dvp->id_drq; 1726 1727 ppcdata[ppc->ppc_unit] = ppc; 1728 nppc ++; 1729 1730 /* 1731 * Link the Parallel Port Chipset (adapter) to 1732 * the future ppbus. Default to a generic chipset 1733 */ 1734 ppc->ppc_link.adapter_unit = ppc->ppc_unit; 1735 ppc->ppc_link.adapter = &ppc_generic_adapter; 1736 1737 /* 1738 * Try to detect the chipset and its mode. 1739 */ 1740 if (ppc_detect(ppc, dvp->id_flags & 0xf)) 1741 goto error; 1742 1743 return (1); 1744 1745 error: 1746 return (0); 1747 } 1748 1749 static int 1750 ppcattach(struct isa_device *isdp) 1751 { 1752 struct ppc_data *ppc = ppcdata[isdp->id_unit]; 1753 struct ppb_data *ppbus; 1754 1755 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit, 1756 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm], 1757 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1758 ppc_epp_protocol[ppc->ppc_epp] : ""); 1759 1760 if (ppc->ppc_fifo) 1761 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n", 1762 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr, 1763 ppc->ppc_rthr); 1764 1765 isdp->id_ointr = ppcintr; 1766 1767 /* 1768 * Prepare ppbus data area for upper level code. 1769 */ 1770 ppbus = ppb_alloc_bus(); 1771 1772 if (!ppbus) 1773 return (0); 1774 1775 ppc->ppc_link.ppbus = ppbus; 1776 ppbus->ppb_link = &ppc->ppc_link; 1777 1778 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1779 1780 /* acquire the DMA channel forever */ 1781 isa_dma_acquire(ppc->ppc_dmachan); 1782 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1783 } 1784 1785 /* 1786 * Probe the ppbus and attach devices found. 1787 */ 1788 ppb_attachdevs(ppbus); 1789 1790 return (1); 1791 } 1792 #endif 1793