1 /*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ppc.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/malloc.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #ifdef __i386__ 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 #include <machine/vmparam.h> 48 #endif 49 50 #include <dev/ppbus/ppbconf.h> 51 #include <dev/ppbus/ppb_msq.h> 52 53 #include <dev/ppc/ppcvar.h> 54 #include <dev/ppc/ppcreg.h> 55 56 #include "ppbus_if.h" 57 58 static void ppcintr(void *arg); 59 60 #define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 61 #define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 62 63 #define LOG_PPC(function, ppc, string) \ 64 if (bootverbose) printf("%s: %s\n", function, string) 65 66 #if defined(__i386__) && defined(PC98) 67 #define PC98_IEEE_1284_DISABLE 0x100 68 #define PC98_IEEE_1284_PORT 0x140 69 #endif 70 71 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 72 73 devclass_t ppc_devclass; 74 const char ppc_driver_name[] = "ppc"; 75 76 static char *ppc_models[] = { 77 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 78 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 79 "SMC FDC37C935", "PC87303", 0 80 }; 81 82 /* list of available modes */ 83 static char *ppc_avms[] = { 84 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 85 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 86 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 87 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 88 }; 89 90 /* list of current executing modes 91 * Note that few modes do not actually exist. 92 */ 93 static char *ppc_modes[] = { 94 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 95 "EPP", "EPP", "EPP", "ECP", 96 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 97 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 98 }; 99 100 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 101 102 #ifdef __i386__ 103 /* 104 * BIOS printer list - used by BIOS probe. 105 */ 106 #define BIOS_PPC_PORTS 0x408 107 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 108 #define BIOS_MAX_PPC 4 109 #endif 110 111 /* 112 * ppc_ecp_sync() XXX 113 */ 114 void 115 ppc_ecp_sync(device_t dev) { 116 117 int i, r; 118 struct ppc_data *ppc = DEVTOSOFTC(dev); 119 120 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 121 return; 122 123 r = r_ecr(ppc); 124 if ((r & 0xe0) != PPC_ECR_EPP) 125 return; 126 127 for (i = 0; i < 100; i++) { 128 r = r_ecr(ppc); 129 if (r & 0x1) 130 return; 131 DELAY(100); 132 } 133 134 printf("ppc%d: ECP sync failed as data still " \ 135 "present in FIFO.\n", ppc->ppc_unit); 136 137 return; 138 } 139 140 /* 141 * ppc_detect_fifo() 142 * 143 * Detect parallel port FIFO 144 */ 145 static int 146 ppc_detect_fifo(struct ppc_data *ppc) 147 { 148 char ecr_sav; 149 char ctr_sav, ctr, cc; 150 short i; 151 152 /* save registers */ 153 ecr_sav = r_ecr(ppc); 154 ctr_sav = r_ctr(ppc); 155 156 /* enter ECP configuration mode, no interrupt, no DMA */ 157 w_ecr(ppc, 0xf4); 158 159 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 160 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 161 162 /* XXX 16 and 32 bits implementations not supported */ 163 if (ppc->ppc_pword != PPC_PWORD_8) { 164 LOG_PPC(__func__, ppc, "PWord not supported"); 165 goto error; 166 } 167 168 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 169 ctr = r_ctr(ppc); 170 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 171 172 /* enter ECP test mode, no interrupt, no DMA */ 173 w_ecr(ppc, 0xd4); 174 175 /* flush the FIFO */ 176 for (i=0; i<1024; i++) { 177 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 178 break; 179 cc = r_fifo(ppc); 180 } 181 182 if (i >= 1024) { 183 LOG_PPC(__func__, ppc, "can't flush FIFO"); 184 goto error; 185 } 186 187 /* enable interrupts, no DMA */ 188 w_ecr(ppc, 0xd0); 189 190 /* determine readIntrThreshold 191 * fill the FIFO until serviceIntr is set 192 */ 193 for (i=0; i<1024; i++) { 194 w_fifo(ppc, (char)i); 195 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 196 /* readThreshold reached */ 197 ppc->ppc_rthr = i+1; 198 } 199 if (r_ecr(ppc) & PPC_FIFO_FULL) { 200 ppc->ppc_fifo = i+1; 201 break; 202 } 203 } 204 205 if (i >= 1024) { 206 LOG_PPC(__func__, ppc, "can't fill FIFO"); 207 goto error; 208 } 209 210 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 211 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 212 w_ecr(ppc, 0xd0); /* enable interrupts */ 213 214 /* determine writeIntrThreshold 215 * empty the FIFO until serviceIntr is set 216 */ 217 for (i=ppc->ppc_fifo; i>0; i--) { 218 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 219 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 220 goto error; 221 } 222 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 223 /* writeIntrThreshold reached */ 224 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 225 } 226 /* if FIFO empty before the last byte, error */ 227 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 228 LOG_PPC(__func__, ppc, "data lost in FIFO"); 229 goto error; 230 } 231 } 232 233 /* FIFO must be empty after the last byte */ 234 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 235 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 236 goto error; 237 } 238 239 w_ctr(ppc, ctr_sav); 240 w_ecr(ppc, ecr_sav); 241 242 return (0); 243 244 error: 245 w_ctr(ppc, ctr_sav); 246 w_ecr(ppc, ecr_sav); 247 248 return (EINVAL); 249 } 250 251 static int 252 ppc_detect_port(struct ppc_data *ppc) 253 { 254 255 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 256 w_dtr(ppc, 0xaa); 257 if (r_dtr(ppc) != 0xaa) 258 return (0); 259 260 return (1); 261 } 262 263 /* 264 * EPP timeout, according to the PC87332 manual 265 * Semantics of clearing EPP timeout bit. 266 * PC87332 - reading SPP_STR does it... 267 * SMC - write 1 to EPP timeout bit XXX 268 * Others - (?) write 0 to EPP timeout bit 269 */ 270 static void 271 ppc_reset_epp_timeout(struct ppc_data *ppc) 272 { 273 register char r; 274 275 r = r_str(ppc); 276 w_str(ppc, r | 0x1); 277 w_str(ppc, r & 0xfe); 278 279 return; 280 } 281 282 static int 283 ppc_check_epp_timeout(struct ppc_data *ppc) 284 { 285 ppc_reset_epp_timeout(ppc); 286 287 return (!(r_str(ppc) & TIMEOUT)); 288 } 289 290 /* 291 * Configure current operating mode 292 */ 293 static int 294 ppc_generic_setmode(struct ppc_data *ppc, int mode) 295 { 296 u_char ecr = 0; 297 298 /* check if mode is available */ 299 if (mode && !(ppc->ppc_avm & mode)) 300 return (EINVAL); 301 302 /* if ECP mode, configure ecr register */ 303 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 304 /* return to byte mode (keeping direction bit), 305 * no interrupt, no DMA to be able to change to 306 * ECP 307 */ 308 w_ecr(ppc, PPC_ECR_RESET); 309 ecr = PPC_DISABLE_INTR; 310 311 if (mode & PPB_EPP) 312 return (EINVAL); 313 else if (mode & PPB_ECP) 314 /* select ECP mode */ 315 ecr |= PPC_ECR_ECP; 316 else if (mode & PPB_PS2) 317 /* select PS2 mode with ECP */ 318 ecr |= PPC_ECR_PS2; 319 else 320 /* select COMPATIBLE/NIBBLE mode */ 321 ecr |= PPC_ECR_STD; 322 323 w_ecr(ppc, ecr); 324 } 325 326 ppc->ppc_mode = mode; 327 328 return (0); 329 } 330 331 /* 332 * The ppc driver is free to choose options like FIFO or DMA 333 * if ECP mode is available. 334 * 335 * The 'RAW' option allows the upper drivers to force the ppc mode 336 * even with FIFO, DMA available. 337 */ 338 static int 339 ppc_smclike_setmode(struct ppc_data *ppc, int mode) 340 { 341 u_char ecr = 0; 342 343 /* check if mode is available */ 344 if (mode && !(ppc->ppc_avm & mode)) 345 return (EINVAL); 346 347 /* if ECP mode, configure ecr register */ 348 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 349 /* return to byte mode (keeping direction bit), 350 * no interrupt, no DMA to be able to change to 351 * ECP or EPP mode 352 */ 353 w_ecr(ppc, PPC_ECR_RESET); 354 ecr = PPC_DISABLE_INTR; 355 356 if (mode & PPB_EPP) 357 /* select EPP mode */ 358 ecr |= PPC_ECR_EPP; 359 else if (mode & PPB_ECP) 360 /* select ECP mode */ 361 ecr |= PPC_ECR_ECP; 362 else if (mode & PPB_PS2) 363 /* select PS2 mode with ECP */ 364 ecr |= PPC_ECR_PS2; 365 else 366 /* select COMPATIBLE/NIBBLE mode */ 367 ecr |= PPC_ECR_STD; 368 369 w_ecr(ppc, ecr); 370 } 371 372 ppc->ppc_mode = mode; 373 374 return (0); 375 } 376 377 #ifdef PPC_PROBE_CHIPSET 378 /* 379 * ppc_pc873xx_detect 380 * 381 * Probe for a Natsemi PC873xx-family part. 382 * 383 * References in this function are to the National Semiconductor 384 * PC87332 datasheet TL/C/11930, May 1995 revision. 385 */ 386 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 387 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 388 static int pc873xx_irqtab[] = {5, 7, 5, 0}; 389 390 static int pc873xx_regstab[] = { 391 PC873_FER, PC873_FAR, PC873_PTR, 392 PC873_FCR, PC873_PCR, PC873_PMC, 393 PC873_TUP, PC873_SID, PC873_PNP0, 394 PC873_PNP1, PC873_LPTBA, -1 395 }; 396 397 static char *pc873xx_rnametab[] = { 398 "FER", "FAR", "PTR", "FCR", "PCR", 399 "PMC", "TUP", "SID", "PNP0", "PNP1", 400 "LPTBA", NULL 401 }; 402 403 static int 404 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 405 { 406 static int index = 0; 407 int idport, irq; 408 int ptr, pcr, val, i; 409 410 while ((idport = pc873xx_basetab[index++])) { 411 412 /* XXX should check first to see if this location is already claimed */ 413 414 /* 415 * Pull the 873xx through the power-on ID cycle (2.2,1.). 416 * We can't use this to locate the chip as it may already have 417 * been used by the BIOS. 418 */ 419 (void)inb(idport); (void)inb(idport); 420 (void)inb(idport); (void)inb(idport); 421 422 /* 423 * Read the SID byte. Possible values are : 424 * 425 * 01010xxx PC87334 426 * 0001xxxx PC87332 427 * 01110xxx PC87306 428 * 00110xxx PC87303 429 */ 430 outb(idport, PC873_SID); 431 val = inb(idport + 1); 432 if ((val & 0xf0) == 0x10) { 433 ppc->ppc_model = NS_PC87332; 434 } else if ((val & 0xf8) == 0x70) { 435 ppc->ppc_model = NS_PC87306; 436 } else if ((val & 0xf8) == 0x50) { 437 ppc->ppc_model = NS_PC87334; 438 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 439 documentation, but probing 440 yielded 0x40... */ 441 ppc->ppc_model = NS_PC87303; 442 } else { 443 if (bootverbose && (val != 0xff)) 444 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 445 continue ; /* not recognised */ 446 } 447 448 /* print registers */ 449 if (bootverbose) { 450 printf("PC873xx"); 451 for (i=0; pc873xx_regstab[i] != -1; i++) { 452 outb(idport, pc873xx_regstab[i]); 453 printf(" %s=0x%x", pc873xx_rnametab[i], 454 inb(idport + 1) & 0xff); 455 } 456 printf("\n"); 457 } 458 459 /* 460 * We think we have one. Is it enabled and where we want it to be? 461 */ 462 outb(idport, PC873_FER); 463 val = inb(idport + 1); 464 if (!(val & PC873_PPENABLE)) { 465 if (bootverbose) 466 printf("PC873xx parallel port disabled\n"); 467 continue; 468 } 469 outb(idport, PC873_FAR); 470 val = inb(idport + 1); 471 /* XXX we should create a driver instance for every port found */ 472 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 473 474 /* First try to change the port address to that requested... */ 475 476 switch(ppc->ppc_base) { 477 case 0x378: 478 val &= 0xfc; 479 break; 480 481 case 0x3bc: 482 val &= 0xfd; 483 break; 484 485 case 0x278: 486 val &= 0xfe; 487 break; 488 489 default: 490 val &= 0xfd; 491 break; 492 } 493 494 outb(idport, PC873_FAR); 495 outb(idport + 1, val); 496 outb(idport + 1, val); 497 498 /* Check for success by reading back the value we supposedly 499 wrote and comparing...*/ 500 501 outb(idport, PC873_FAR); 502 val = inb(idport + 1) & 0x3; 503 504 /* If we fail, report the failure... */ 505 506 if (pc873xx_porttab[val] != ppc->ppc_base) { 507 if (bootverbose) 508 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 509 pc873xx_porttab[val], ppc->ppc_base); 510 } 511 continue; 512 } 513 514 outb(idport, PC873_PTR); 515 ptr = inb(idport + 1); 516 517 /* get irq settings */ 518 if (ppc->ppc_base == 0x378) 519 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 520 else 521 irq = pc873xx_irqtab[val]; 522 523 if (bootverbose) 524 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 525 526 /* 527 * Check if irq settings are correct 528 */ 529 if (irq != ppc->ppc_irq) { 530 /* 531 * If the chipset is not locked and base address is 0x378, 532 * we have another chance 533 */ 534 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 535 if (ppc->ppc_irq == 7) { 536 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 537 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 538 } else { 539 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 540 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 541 } 542 if (bootverbose) 543 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 544 } else { 545 if (bootverbose) 546 printf("PC873xx sorry, can't change irq setting\n"); 547 } 548 } else { 549 if (bootverbose) 550 printf("PC873xx irq settings are correct\n"); 551 } 552 553 outb(idport, PC873_PCR); 554 pcr = inb(idport + 1); 555 556 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 557 if (bootverbose) 558 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 559 560 ppc->ppc_avm |= PPB_NIBBLE; 561 if (bootverbose) 562 printf(", NIBBLE"); 563 564 if (pcr & PC873_EPPEN) { 565 ppc->ppc_avm |= PPB_EPP; 566 567 if (bootverbose) 568 printf(", EPP"); 569 570 if (pcr & PC873_EPP19) 571 ppc->ppc_epp = EPP_1_9; 572 else 573 ppc->ppc_epp = EPP_1_7; 574 575 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 576 outb(idport, PC873_PTR); 577 ptr = inb(idport + 1); 578 if (ptr & PC873_EPPRDIR) 579 printf(", Regular mode"); 580 else 581 printf(", Automatic mode"); 582 } 583 } else if (pcr & PC873_ECPEN) { 584 ppc->ppc_avm |= PPB_ECP; 585 if (bootverbose) 586 printf(", ECP"); 587 588 if (pcr & PC873_ECPCLK) { /* XXX */ 589 ppc->ppc_avm |= PPB_PS2; 590 if (bootverbose) 591 printf(", PS/2"); 592 } 593 } else { 594 outb(idport, PC873_PTR); 595 ptr = inb(idport + 1); 596 if (ptr & PC873_EXTENDED) { 597 ppc->ppc_avm |= PPB_SPP; 598 if (bootverbose) 599 printf(", SPP"); 600 } 601 } 602 } else { 603 if (bootverbose) 604 printf("PC873xx unlocked"); 605 606 if (chipset_mode & PPB_ECP) { 607 if ((chipset_mode & PPB_EPP) && bootverbose) 608 printf(", ECP+EPP not supported"); 609 610 pcr &= ~PC873_EPPEN; 611 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 612 outb(idport + 1, pcr); 613 outb(idport + 1, pcr); 614 615 if (bootverbose) 616 printf(", ECP"); 617 618 } else if (chipset_mode & PPB_EPP) { 619 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 620 pcr |= (PC873_EPPEN | PC873_EPP19); 621 outb(idport + 1, pcr); 622 outb(idport + 1, pcr); 623 624 ppc->ppc_epp = EPP_1_9; /* XXX */ 625 626 if (bootverbose) 627 printf(", EPP1.9"); 628 629 /* enable automatic direction turnover */ 630 if (ppc->ppc_model == NS_PC87332) { 631 outb(idport, PC873_PTR); 632 ptr = inb(idport + 1); 633 ptr &= ~PC873_EPPRDIR; 634 outb(idport + 1, ptr); 635 outb(idport + 1, ptr); 636 637 if (bootverbose) 638 printf(", Automatic mode"); 639 } 640 } else { 641 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 642 outb(idport + 1, pcr); 643 outb(idport + 1, pcr); 644 645 /* configure extended bit in PTR */ 646 outb(idport, PC873_PTR); 647 ptr = inb(idport + 1); 648 649 if (chipset_mode & PPB_PS2) { 650 ptr |= PC873_EXTENDED; 651 652 if (bootverbose) 653 printf(", PS/2"); 654 655 } else { 656 /* default to NIBBLE mode */ 657 ptr &= ~PC873_EXTENDED; 658 659 if (bootverbose) 660 printf(", NIBBLE"); 661 } 662 outb(idport + 1, ptr); 663 outb(idport + 1, ptr); 664 } 665 666 ppc->ppc_avm = chipset_mode; 667 } 668 669 if (bootverbose) 670 printf("\n"); 671 672 ppc->ppc_type = PPC_TYPE_GENERIC; 673 ppc_generic_setmode(ppc, chipset_mode); 674 675 return(chipset_mode); 676 } 677 return(-1); 678 } 679 680 /* 681 * ppc_smc37c66xgt_detect 682 * 683 * SMC FDC37C66xGT configuration. 684 */ 685 static int 686 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 687 { 688 int s, i; 689 u_char r; 690 int type = -1; 691 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 692 693 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 694 695 696 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 697 698 /* 699 * Detection: enter configuration mode and read CRD register. 700 */ 701 702 s = splhigh(); 703 outb(csr, SMC665_iCODE); 704 outb(csr, SMC665_iCODE); 705 splx(s); 706 707 outb(csr, 0xd); 708 if (inb(cio) == 0x65) { 709 type = SMC_37C665GT; 710 goto config; 711 } 712 713 for (i = 0; i < 2; i++) { 714 s = splhigh(); 715 outb(csr, SMC666_iCODE); 716 outb(csr, SMC666_iCODE); 717 splx(s); 718 719 outb(csr, 0xd); 720 if (inb(cio) == 0x66) { 721 type = SMC_37C666GT; 722 break; 723 } 724 725 /* Another chance, CSR may be hard-configured to be at 0x370 */ 726 csr = SMC666_CSR; 727 } 728 729 config: 730 /* 731 * If chipset not found, do not continue. 732 */ 733 if (type == -1) 734 return (-1); 735 736 /* select CR1 */ 737 outb(csr, 0x1); 738 739 /* read the port's address: bits 0 and 1 of CR1 */ 740 r = inb(cio) & SMC_CR1_ADDR; 741 if (port_address[(int)r] != ppc->ppc_base) 742 return (-1); 743 744 ppc->ppc_model = type; 745 746 /* 747 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 748 * If SPP mode is detected, try to set ECP+EPP mode 749 */ 750 751 if (bootverbose) { 752 outb(csr, 0x1); 753 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 754 inb(cio) & 0xff); 755 756 outb(csr, 0x4); 757 printf(" CR4=0x%x", inb(cio) & 0xff); 758 } 759 760 /* select CR1 */ 761 outb(csr, 0x1); 762 763 if (!chipset_mode) { 764 /* autodetect mode */ 765 766 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 767 if (type == SMC_37C666GT) { 768 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 769 if (bootverbose) 770 printf(" configuration hardwired, supposing " \ 771 "ECP+EPP SPP"); 772 773 } else 774 if ((inb(cio) & SMC_CR1_MODE) == 0) { 775 /* already in extended parallel port mode, read CR4 */ 776 outb(csr, 0x4); 777 r = (inb(cio) & SMC_CR4_EMODE); 778 779 switch (r) { 780 case SMC_SPP: 781 ppc->ppc_avm |= PPB_SPP; 782 if (bootverbose) 783 printf(" SPP"); 784 break; 785 786 case SMC_EPPSPP: 787 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 788 if (bootverbose) 789 printf(" EPP SPP"); 790 break; 791 792 case SMC_ECP: 793 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 794 if (bootverbose) 795 printf(" ECP SPP"); 796 break; 797 798 case SMC_ECPEPP: 799 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 800 if (bootverbose) 801 printf(" ECP+EPP SPP"); 802 break; 803 } 804 } else { 805 /* not an extended port mode */ 806 ppc->ppc_avm |= PPB_SPP; 807 if (bootverbose) 808 printf(" SPP"); 809 } 810 811 } else { 812 /* mode forced */ 813 ppc->ppc_avm = chipset_mode; 814 815 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 816 if (type == SMC_37C666GT) 817 goto end_detect; 818 819 r = inb(cio); 820 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 821 /* do not use ECP when the mode is not forced to */ 822 outb(cio, r | SMC_CR1_MODE); 823 if (bootverbose) 824 printf(" SPP"); 825 } else { 826 /* an extended mode is selected */ 827 outb(cio, r & ~SMC_CR1_MODE); 828 829 /* read CR4 register and reset mode field */ 830 outb(csr, 0x4); 831 r = inb(cio) & ~SMC_CR4_EMODE; 832 833 if (chipset_mode & PPB_ECP) { 834 if (chipset_mode & PPB_EPP) { 835 outb(cio, r | SMC_ECPEPP); 836 if (bootverbose) 837 printf(" ECP+EPP"); 838 } else { 839 outb(cio, r | SMC_ECP); 840 if (bootverbose) 841 printf(" ECP"); 842 } 843 } else { 844 /* PPB_EPP is set */ 845 outb(cio, r | SMC_EPPSPP); 846 if (bootverbose) 847 printf(" EPP SPP"); 848 } 849 } 850 ppc->ppc_avm = chipset_mode; 851 } 852 853 /* set FIFO threshold to 16 */ 854 if (ppc->ppc_avm & PPB_ECP) { 855 /* select CRA */ 856 outb(csr, 0xa); 857 outb(cio, 16); 858 } 859 860 end_detect: 861 862 if (bootverbose) 863 printf ("\n"); 864 865 if (ppc->ppc_avm & PPB_EPP) { 866 /* select CR4 */ 867 outb(csr, 0x4); 868 r = inb(cio); 869 870 /* 871 * Set the EPP protocol... 872 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 873 */ 874 if (ppc->ppc_epp == EPP_1_9) 875 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 876 else 877 outb(cio, (r | SMC_CR4_EPPTYPE)); 878 } 879 880 /* end config mode */ 881 outb(csr, 0xaa); 882 883 ppc->ppc_type = PPC_TYPE_SMCLIKE; 884 ppc_smclike_setmode(ppc, chipset_mode); 885 886 return (chipset_mode); 887 } 888 889 /* 890 * SMC FDC37C935 configuration 891 * Found on many Alpha machines 892 */ 893 static int 894 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 895 { 896 int s; 897 int type = -1; 898 899 s = splhigh(); 900 outb(SMC935_CFG, 0x55); /* enter config mode */ 901 outb(SMC935_CFG, 0x55); 902 splx(s); 903 904 outb(SMC935_IND, SMC935_ID); /* check device id */ 905 if (inb(SMC935_DAT) == 0x2) 906 type = SMC_37C935; 907 908 if (type == -1) { 909 outb(SMC935_CFG, 0xaa); /* exit config mode */ 910 return (-1); 911 } 912 913 ppc->ppc_model = type; 914 915 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 916 outb(SMC935_DAT, 3); /* which is logical device 3 */ 917 918 /* set io port base */ 919 outb(SMC935_IND, SMC935_PORTHI); 920 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 921 outb(SMC935_IND, SMC935_PORTLO); 922 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 923 924 if (!chipset_mode) 925 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 926 else { 927 ppc->ppc_avm = chipset_mode; 928 outb(SMC935_IND, SMC935_PPMODE); 929 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 930 931 /* SPP + EPP or just plain SPP */ 932 if (chipset_mode & (PPB_SPP)) { 933 if (chipset_mode & PPB_EPP) { 934 if (ppc->ppc_epp == EPP_1_9) { 935 outb(SMC935_IND, SMC935_PPMODE); 936 outb(SMC935_DAT, SMC935_EPP19SPP); 937 } 938 if (ppc->ppc_epp == EPP_1_7) { 939 outb(SMC935_IND, SMC935_PPMODE); 940 outb(SMC935_DAT, SMC935_EPP17SPP); 941 } 942 } else { 943 outb(SMC935_IND, SMC935_PPMODE); 944 outb(SMC935_DAT, SMC935_SPP); 945 } 946 } 947 948 /* ECP + EPP or just plain ECP */ 949 if (chipset_mode & PPB_ECP) { 950 if (chipset_mode & PPB_EPP) { 951 if (ppc->ppc_epp == EPP_1_9) { 952 outb(SMC935_IND, SMC935_PPMODE); 953 outb(SMC935_DAT, SMC935_ECPEPP19); 954 } 955 if (ppc->ppc_epp == EPP_1_7) { 956 outb(SMC935_IND, SMC935_PPMODE); 957 outb(SMC935_DAT, SMC935_ECPEPP17); 958 } 959 } else { 960 outb(SMC935_IND, SMC935_PPMODE); 961 outb(SMC935_DAT, SMC935_ECP); 962 } 963 } 964 } 965 966 outb(SMC935_CFG, 0xaa); /* exit config mode */ 967 968 ppc->ppc_type = PPC_TYPE_SMCLIKE; 969 ppc_smclike_setmode(ppc, chipset_mode); 970 971 return (chipset_mode); 972 } 973 974 /* 975 * Winbond W83877F stuff 976 * 977 * EFER: extended function enable register 978 * EFIR: extended function index register 979 * EFDR: extended function data register 980 */ 981 #define efir ((efer == 0x250) ? 0x251 : 0x3f0) 982 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 983 984 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 985 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 986 static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 987 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 988 989 static int 990 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 991 { 992 int i, j, efer; 993 unsigned char r, hefere, hefras; 994 995 for (i = 0; i < 4; i ++) { 996 /* first try to enable configuration registers */ 997 efer = w83877f_efers[i]; 998 999 /* write the key to the EFER */ 1000 for (j = 0; j < w83877f_keyiter[i]; j ++) 1001 outb (efer, w83877f_keys[i]); 1002 1003 /* then check HEFERE and HEFRAS bits */ 1004 outb (efir, 0x0c); 1005 hefere = inb(efdr) & WINB_HEFERE; 1006 1007 outb (efir, 0x16); 1008 hefras = inb(efdr) & WINB_HEFRAS; 1009 1010 /* 1011 * HEFRAS HEFERE 1012 * 0 1 write 89h to 250h (power-on default) 1013 * 1 0 write 86h twice to 3f0h 1014 * 1 1 write 87h twice to 3f0h 1015 * 0 0 write 88h to 250h 1016 */ 1017 if ((hefere | hefras) == w83877f_hefs[i]) 1018 goto found; 1019 } 1020 1021 return (-1); /* failed */ 1022 1023 found: 1024 /* check base port address - read from CR23 */ 1025 outb(efir, 0x23); 1026 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1027 return (-1); 1028 1029 /* read CHIP ID from CR9/bits0-3 */ 1030 outb(efir, 0x9); 1031 1032 switch (inb(efdr) & WINB_CHIPID) { 1033 case WINB_W83877F_ID: 1034 ppc->ppc_model = WINB_W83877F; 1035 break; 1036 1037 case WINB_W83877AF_ID: 1038 ppc->ppc_model = WINB_W83877AF; 1039 break; 1040 1041 default: 1042 ppc->ppc_model = WINB_UNKNOWN; 1043 } 1044 1045 if (bootverbose) { 1046 /* dump of registers */ 1047 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1048 for (i = 0; i <= 0xd; i ++) { 1049 outb(efir, i); 1050 printf("0x%x ", inb(efdr)); 1051 } 1052 for (i = 0x10; i <= 0x17; i ++) { 1053 outb(efir, i); 1054 printf("0x%x ", inb(efdr)); 1055 } 1056 outb(efir, 0x1e); 1057 printf("0x%x ", inb(efdr)); 1058 for (i = 0x20; i <= 0x29; i ++) { 1059 outb(efir, i); 1060 printf("0x%x ", inb(efdr)); 1061 } 1062 printf("\n"); 1063 printf("ppc%d:", ppc->ppc_unit); 1064 } 1065 1066 ppc->ppc_type = PPC_TYPE_GENERIC; 1067 1068 if (!chipset_mode) { 1069 /* autodetect mode */ 1070 1071 /* select CR0 */ 1072 outb(efir, 0x0); 1073 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1074 1075 /* select CR9 */ 1076 outb(efir, 0x9); 1077 r |= (inb(efdr) & WINB_PRTMODS2); 1078 1079 switch (r) { 1080 case WINB_W83757: 1081 if (bootverbose) 1082 printf("ppc%d: W83757 compatible mode\n", 1083 ppc->ppc_unit); 1084 return (-1); /* generic or SMC-like */ 1085 1086 case WINB_EXTFDC: 1087 case WINB_EXTADP: 1088 case WINB_EXT2FDD: 1089 case WINB_JOYSTICK: 1090 if (bootverbose) 1091 printf(" not in parallel port mode\n"); 1092 return (-1); 1093 1094 case (WINB_PARALLEL | WINB_EPP_SPP): 1095 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1096 if (bootverbose) 1097 printf(" EPP SPP"); 1098 break; 1099 1100 case (WINB_PARALLEL | WINB_ECP): 1101 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1102 if (bootverbose) 1103 printf(" ECP SPP"); 1104 break; 1105 1106 case (WINB_PARALLEL | WINB_ECP_EPP): 1107 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1108 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1109 1110 if (bootverbose) 1111 printf(" ECP+EPP SPP"); 1112 break; 1113 default: 1114 printf("%s: unknown case (0x%x)!\n", __func__, r); 1115 } 1116 1117 } else { 1118 /* mode forced */ 1119 1120 /* select CR9 and set PRTMODS2 bit */ 1121 outb(efir, 0x9); 1122 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1123 1124 /* select CR0 and reset PRTMODSx bits */ 1125 outb(efir, 0x0); 1126 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1127 1128 if (chipset_mode & PPB_ECP) { 1129 if (chipset_mode & PPB_EPP) { 1130 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1131 if (bootverbose) 1132 printf(" ECP+EPP"); 1133 1134 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1135 1136 } else { 1137 outb(efdr, inb(efdr) | WINB_ECP); 1138 if (bootverbose) 1139 printf(" ECP"); 1140 } 1141 } else { 1142 /* select EPP_SPP otherwise */ 1143 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1144 if (bootverbose) 1145 printf(" EPP SPP"); 1146 } 1147 ppc->ppc_avm = chipset_mode; 1148 } 1149 1150 if (bootverbose) 1151 printf("\n"); 1152 1153 /* exit configuration mode */ 1154 outb(efer, 0xaa); 1155 1156 switch (ppc->ppc_type) { 1157 case PPC_TYPE_SMCLIKE: 1158 ppc_smclike_setmode(ppc, chipset_mode); 1159 break; 1160 default: 1161 ppc_generic_setmode(ppc, chipset_mode); 1162 break; 1163 } 1164 1165 return (chipset_mode); 1166 } 1167 #endif 1168 1169 /* 1170 * ppc_generic_detect 1171 */ 1172 static int 1173 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1174 { 1175 /* default to generic */ 1176 ppc->ppc_type = PPC_TYPE_GENERIC; 1177 1178 if (bootverbose) 1179 printf("ppc%d:", ppc->ppc_unit); 1180 1181 /* first, check for ECP */ 1182 w_ecr(ppc, PPC_ECR_PS2); 1183 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1184 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1185 if (bootverbose) 1186 printf(" ECP SPP"); 1187 1188 /* search for SMC style ECP+EPP mode */ 1189 w_ecr(ppc, PPC_ECR_EPP); 1190 } 1191 1192 /* try to reset EPP timeout bit */ 1193 if (ppc_check_epp_timeout(ppc)) { 1194 ppc->ppc_dtm |= PPB_EPP; 1195 1196 if (ppc->ppc_dtm & PPB_ECP) { 1197 /* SMC like chipset found */ 1198 ppc->ppc_model = SMC_LIKE; 1199 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1200 1201 if (bootverbose) 1202 printf(" ECP+EPP"); 1203 } else { 1204 if (bootverbose) 1205 printf(" EPP"); 1206 } 1207 } else { 1208 /* restore to standard mode */ 1209 w_ecr(ppc, PPC_ECR_STD); 1210 } 1211 1212 /* XXX try to detect NIBBLE and PS2 modes */ 1213 ppc->ppc_dtm |= PPB_NIBBLE; 1214 1215 if (bootverbose) 1216 printf(" SPP"); 1217 1218 if (chipset_mode) 1219 ppc->ppc_avm = chipset_mode; 1220 else 1221 ppc->ppc_avm = ppc->ppc_dtm; 1222 1223 if (bootverbose) 1224 printf("\n"); 1225 1226 switch (ppc->ppc_type) { 1227 case PPC_TYPE_SMCLIKE: 1228 ppc_smclike_setmode(ppc, chipset_mode); 1229 break; 1230 default: 1231 ppc_generic_setmode(ppc, chipset_mode); 1232 break; 1233 } 1234 1235 return (chipset_mode); 1236 } 1237 1238 /* 1239 * ppc_detect() 1240 * 1241 * mode is the mode suggested at boot 1242 */ 1243 static int 1244 ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1245 1246 #ifdef PPC_PROBE_CHIPSET 1247 int i, mode; 1248 1249 /* list of supported chipsets */ 1250 int (*chipset_detect[])(struct ppc_data *, int) = { 1251 ppc_pc873xx_detect, 1252 ppc_smc37c66xgt_detect, 1253 ppc_w83877f_detect, 1254 ppc_smc37c935_detect, 1255 ppc_generic_detect, 1256 NULL 1257 }; 1258 #endif 1259 1260 /* if can't find the port and mode not forced return error */ 1261 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1262 return (EIO); /* failed, port not present */ 1263 1264 /* assume centronics compatible mode is supported */ 1265 ppc->ppc_avm = PPB_COMPATIBLE; 1266 1267 #ifdef PPC_PROBE_CHIPSET 1268 /* we have to differenciate available chipset modes, 1269 * chipset running modes and IEEE-1284 operating modes 1270 * 1271 * after detection, the port must support running in compatible mode 1272 */ 1273 if (ppc->ppc_flags & 0x40) { 1274 if (bootverbose) 1275 printf("ppc: chipset forced to generic\n"); 1276 #endif 1277 1278 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1279 1280 #ifdef PPC_PROBE_CHIPSET 1281 } else { 1282 for (i=0; chipset_detect[i] != NULL; i++) { 1283 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1284 ppc->ppc_mode = mode; 1285 break; 1286 } 1287 } 1288 } 1289 #endif 1290 1291 /* configure/detect ECP FIFO */ 1292 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1293 ppc_detect_fifo(ppc); 1294 1295 return (0); 1296 } 1297 1298 /* 1299 * ppc_exec_microseq() 1300 * 1301 * Execute a microsequence. 1302 * Microsequence mechanism is supposed to handle fast I/O operations. 1303 */ 1304 int 1305 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1306 { 1307 struct ppc_data *ppc = DEVTOSOFTC(dev); 1308 struct ppb_microseq *mi; 1309 char cc, *p; 1310 int i, iter, len; 1311 int error; 1312 1313 register int reg; 1314 register char mask; 1315 register int accum = 0; 1316 register char *ptr = 0; 1317 1318 struct ppb_microseq *stack = 0; 1319 1320 /* microsequence registers are equivalent to PC-like port registers */ 1321 1322 #define r_reg(reg,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, reg)) 1323 #define w_reg(reg, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, reg, byte)) 1324 1325 #define INCR_PC (mi ++) /* increment program counter */ 1326 1327 mi = *p_msq; 1328 for (;;) { 1329 switch (mi->opcode) { 1330 case MS_OP_RSET: 1331 cc = r_reg(mi->arg[0].i, ppc); 1332 cc &= (char)mi->arg[2].i; /* clear mask */ 1333 cc |= (char)mi->arg[1].i; /* assert mask */ 1334 w_reg(mi->arg[0].i, ppc, cc); 1335 INCR_PC; 1336 break; 1337 1338 case MS_OP_RASSERT_P: 1339 reg = mi->arg[1].i; 1340 ptr = ppc->ppc_ptr; 1341 1342 if ((len = mi->arg[0].i) == MS_ACCUM) { 1343 accum = ppc->ppc_accum; 1344 for (; accum; accum--) 1345 w_reg(reg, ppc, *ptr++); 1346 ppc->ppc_accum = accum; 1347 } else 1348 for (i=0; i<len; i++) 1349 w_reg(reg, ppc, *ptr++); 1350 ppc->ppc_ptr = ptr; 1351 1352 INCR_PC; 1353 break; 1354 1355 case MS_OP_RFETCH_P: 1356 reg = mi->arg[1].i; 1357 mask = (char)mi->arg[2].i; 1358 ptr = ppc->ppc_ptr; 1359 1360 if ((len = mi->arg[0].i) == MS_ACCUM) { 1361 accum = ppc->ppc_accum; 1362 for (; accum; accum--) 1363 *ptr++ = r_reg(reg, ppc) & mask; 1364 ppc->ppc_accum = accum; 1365 } else 1366 for (i=0; i<len; i++) 1367 *ptr++ = r_reg(reg, ppc) & mask; 1368 ppc->ppc_ptr = ptr; 1369 1370 INCR_PC; 1371 break; 1372 1373 case MS_OP_RFETCH: 1374 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1375 (char)mi->arg[1].i; 1376 INCR_PC; 1377 break; 1378 1379 case MS_OP_RASSERT: 1380 case MS_OP_DELAY: 1381 1382 /* let's suppose the next instr. is the same */ 1383 prefetch: 1384 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1385 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1386 1387 if (mi->opcode == MS_OP_DELAY) { 1388 DELAY(mi->arg[0].i); 1389 INCR_PC; 1390 goto prefetch; 1391 } 1392 break; 1393 1394 case MS_OP_ADELAY: 1395 if (mi->arg[0].i) 1396 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1397 INCR_PC; 1398 break; 1399 1400 case MS_OP_TRIG: 1401 reg = mi->arg[0].i; 1402 iter = mi->arg[1].i; 1403 p = (char *)mi->arg[2].p; 1404 1405 /* XXX delay limited to 255 us */ 1406 for (i=0; i<iter; i++) { 1407 w_reg(reg, ppc, *p++); 1408 DELAY((unsigned char)*p++); 1409 } 1410 INCR_PC; 1411 break; 1412 1413 case MS_OP_SET: 1414 ppc->ppc_accum = mi->arg[0].i; 1415 INCR_PC; 1416 break; 1417 1418 case MS_OP_DBRA: 1419 if (--ppc->ppc_accum > 0) 1420 mi += mi->arg[0].i; 1421 INCR_PC; 1422 break; 1423 1424 case MS_OP_BRSET: 1425 cc = r_str(ppc); 1426 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1427 mi += mi->arg[1].i; 1428 INCR_PC; 1429 break; 1430 1431 case MS_OP_BRCLEAR: 1432 cc = r_str(ppc); 1433 if ((cc & (char)mi->arg[0].i) == 0) 1434 mi += mi->arg[1].i; 1435 INCR_PC; 1436 break; 1437 1438 case MS_OP_BRSTAT: 1439 cc = r_str(ppc); 1440 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1441 (char)mi->arg[0].i) 1442 mi += mi->arg[2].i; 1443 INCR_PC; 1444 break; 1445 1446 case MS_OP_C_CALL: 1447 /* 1448 * If the C call returns !0 then end the microseq. 1449 * The current state of ptr is passed to the C function 1450 */ 1451 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1452 return (error); 1453 1454 INCR_PC; 1455 break; 1456 1457 case MS_OP_PTR: 1458 ppc->ppc_ptr = (char *)mi->arg[0].p; 1459 INCR_PC; 1460 break; 1461 1462 case MS_OP_CALL: 1463 if (stack) 1464 panic("%s: too much calls", __func__); 1465 1466 if (mi->arg[0].p) { 1467 /* store the state of the actual 1468 * microsequence 1469 */ 1470 stack = mi; 1471 1472 /* jump to the new microsequence */ 1473 mi = (struct ppb_microseq *)mi->arg[0].p; 1474 } else 1475 INCR_PC; 1476 1477 break; 1478 1479 case MS_OP_SUBRET: 1480 /* retrieve microseq and pc state before the call */ 1481 mi = stack; 1482 1483 /* reset the stack */ 1484 stack = 0; 1485 1486 /* XXX return code */ 1487 1488 INCR_PC; 1489 break; 1490 1491 case MS_OP_PUT: 1492 case MS_OP_GET: 1493 case MS_OP_RET: 1494 /* can't return to ppb level during the execution 1495 * of a submicrosequence */ 1496 if (stack) 1497 panic("%s: can't return to ppb level", 1498 __func__); 1499 1500 /* update pc for ppb level of execution */ 1501 *p_msq = mi; 1502 1503 /* return to ppb level of execution */ 1504 return (0); 1505 1506 default: 1507 panic("%s: unknown microsequence opcode 0x%x", 1508 __func__, mi->opcode); 1509 } 1510 } 1511 1512 /* unreached */ 1513 } 1514 1515 static void 1516 ppcintr(void *arg) 1517 { 1518 device_t dev = (device_t)arg; 1519 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1520 u_char ctr, ecr, str; 1521 1522 str = r_str(ppc); 1523 ctr = r_ctr(ppc); 1524 ecr = r_ecr(ppc); 1525 1526 #if defined(PPC_DEBUG) && PPC_DEBUG > 1 1527 printf("![%x/%x/%x]", ctr, ecr, str); 1528 #endif 1529 1530 /* don't use ecp mode with IRQENABLE set */ 1531 if (ctr & IRQENABLE) { 1532 return; 1533 } 1534 1535 /* interrupts are generated by nFault signal 1536 * only in ECP mode */ 1537 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1538 /* check if ppc driver has programmed the 1539 * nFault interrupt */ 1540 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1541 1542 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1543 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1544 } else { 1545 /* shall be handled by underlying layers XXX */ 1546 return; 1547 } 1548 } 1549 1550 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1551 /* disable interrupts (should be done by hardware though) */ 1552 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1553 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1554 ecr = r_ecr(ppc); 1555 1556 /* check if DMA completed */ 1557 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1558 #ifdef PPC_DEBUG 1559 printf("a"); 1560 #endif 1561 /* stop DMA */ 1562 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1563 ecr = r_ecr(ppc); 1564 1565 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1566 #ifdef PPC_DEBUG 1567 printf("d"); 1568 #endif 1569 ppc->ppc_dmadone(ppc); 1570 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1571 1572 /* wakeup the waiting process */ 1573 wakeup(ppc); 1574 } 1575 } 1576 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1577 1578 /* classic interrupt I/O */ 1579 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1580 } 1581 1582 return; 1583 } 1584 1585 int 1586 ppc_read(device_t dev, char *buf, int len, int mode) 1587 { 1588 return (EINVAL); 1589 } 1590 1591 int 1592 ppc_write(device_t dev, char *buf, int len, int how) 1593 { 1594 return (EINVAL); 1595 } 1596 1597 void 1598 ppc_reset_epp(device_t dev) 1599 { 1600 struct ppc_data *ppc = DEVTOSOFTC(dev); 1601 1602 ppc_reset_epp_timeout(ppc); 1603 1604 return; 1605 } 1606 1607 int 1608 ppc_setmode(device_t dev, int mode) 1609 { 1610 struct ppc_data *ppc = DEVTOSOFTC(dev); 1611 1612 switch (ppc->ppc_type) { 1613 case PPC_TYPE_SMCLIKE: 1614 return (ppc_smclike_setmode(ppc, mode)); 1615 break; 1616 1617 case PPC_TYPE_GENERIC: 1618 default: 1619 return (ppc_generic_setmode(ppc, mode)); 1620 break; 1621 } 1622 1623 /* not reached */ 1624 return (ENXIO); 1625 } 1626 1627 int 1628 ppc_probe(device_t dev, int rid) 1629 { 1630 #ifdef __i386__ 1631 static short next_bios_ppc = 0; 1632 #ifdef PC98 1633 unsigned int pc98_ieee_mode = 0x00; 1634 unsigned int tmp; 1635 #endif 1636 #endif 1637 struct ppc_data *ppc; 1638 int error; 1639 u_long port; 1640 1641 /* 1642 * Allocate the ppc_data structure. 1643 */ 1644 ppc = DEVTOSOFTC(dev); 1645 bzero(ppc, sizeof(struct ppc_data)); 1646 1647 ppc->rid_ioport = rid; 1648 1649 /* retrieve ISA parameters */ 1650 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1651 1652 #ifdef __i386__ 1653 /* 1654 * If port not specified, use bios list. 1655 */ 1656 if (error) { 1657 #ifdef PC98 1658 if (next_bios_ppc == 0) { 1659 /* Use default IEEE-1284 port of NEC PC-98x1 */ 1660 port = PC98_IEEE_1284_PORT; 1661 next_bios_ppc += 1; 1662 if (bootverbose) 1663 device_printf(dev, 1664 "parallel port found at 0x%x\n", 1665 (int) port); 1666 } 1667 #else 1668 if((next_bios_ppc < BIOS_MAX_PPC) && 1669 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1670 port = *(BIOS_PORTS+next_bios_ppc++); 1671 if (bootverbose) 1672 device_printf(dev, "parallel port found at 0x%x\n", 1673 (int) port); 1674 } else { 1675 device_printf(dev, "parallel port not found.\n"); 1676 return ENXIO; 1677 } 1678 #endif /* PC98 */ 1679 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1680 IO_LPTSIZE_EXTENDED); 1681 } 1682 #endif 1683 1684 /* IO port is mandatory */ 1685 1686 /* Try "extended" IO port range...*/ 1687 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1688 &ppc->rid_ioport, 0, ~0, 1689 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1690 1691 if (ppc->res_ioport != 0) { 1692 if (bootverbose) 1693 device_printf(dev, "using extended I/O port range\n"); 1694 } else { 1695 /* Failed? If so, then try the "normal" IO port range... */ 1696 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1697 &ppc->rid_ioport, 0, ~0, 1698 IO_LPTSIZE_NORMAL, 1699 RF_ACTIVE); 1700 if (ppc->res_ioport != 0) { 1701 if (bootverbose) 1702 device_printf(dev, "using normal I/O port range\n"); 1703 } else { 1704 device_printf(dev, "cannot reserve I/O port range\n"); 1705 goto error; 1706 } 1707 } 1708 1709 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1710 1711 ppc->bsh = rman_get_bushandle(ppc->res_ioport); 1712 ppc->bst = rman_get_bustag(ppc->res_ioport); 1713 1714 ppc->ppc_flags = device_get_flags(dev); 1715 1716 if (!(ppc->ppc_flags & 0x20)) { 1717 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1718 &ppc->rid_irq, 1719 RF_SHAREABLE); 1720 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1721 &ppc->rid_drq, 1722 RF_ACTIVE); 1723 } 1724 1725 if (ppc->res_irq) 1726 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1727 if (ppc->res_drq) 1728 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1729 1730 ppc->ppc_unit = device_get_unit(dev); 1731 ppc->ppc_model = GENERIC; 1732 1733 ppc->ppc_mode = PPB_COMPATIBLE; 1734 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1735 1736 ppc->ppc_type = PPC_TYPE_GENERIC; 1737 1738 #if defined(__i386__) && defined(PC98) 1739 /* 1740 * IEEE STD 1284 Function Check and Enable 1741 * for default IEEE-1284 port of NEC PC-98x1 1742 */ 1743 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1744 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1745 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1746 pc98_ieee_mode = tmp; 1747 if ((tmp & 0x10) == 0x10) { 1748 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); 1749 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1750 if ((tmp & 0x10) == 0x10) 1751 goto error; 1752 } else { 1753 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); 1754 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1755 if ((tmp & 0x10) != 0x10) 1756 goto error; 1757 } 1758 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); 1759 } 1760 #endif 1761 1762 /* 1763 * Try to detect the chipset and its mode. 1764 */ 1765 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1766 goto error; 1767 1768 return (0); 1769 1770 error: 1771 #if defined(__i386__) && defined(PC98) 1772 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1773 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1774 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); 1775 } 1776 #endif 1777 if (ppc->res_irq != 0) { 1778 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1779 ppc->res_irq); 1780 } 1781 if (ppc->res_ioport != 0) { 1782 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1783 ppc->res_ioport); 1784 } 1785 if (ppc->res_drq != 0) { 1786 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1787 ppc->res_drq); 1788 } 1789 return (ENXIO); 1790 } 1791 1792 int 1793 ppc_attach(device_t dev) 1794 { 1795 struct ppc_data *ppc = DEVTOSOFTC(dev); 1796 1797 device_t ppbus; 1798 1799 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1800 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1801 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1802 ppc_epp_protocol[ppc->ppc_epp] : ""); 1803 1804 if (ppc->ppc_fifo) 1805 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1806 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1807 1808 /* add ppbus as a child of this isa to parallel bridge */ 1809 ppbus = device_add_child(dev, "ppbus", -1); 1810 1811 /* 1812 * Probe the ppbus and attach devices found. 1813 */ 1814 device_probe_and_attach(ppbus); 1815 1816 /* register the ppc interrupt handler as default */ 1817 if (ppc->res_irq) { 1818 /* default to the tty mask for registration */ /* XXX */ 1819 if (bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY, 1820 NULL, ppcintr, dev, &ppc->intr_cookie) == 0) { 1821 1822 /* remember the ppcintr is registered */ 1823 ppc->ppc_registered = 1; 1824 } 1825 } 1826 1827 return (0); 1828 } 1829 1830 int 1831 ppc_detach(device_t dev) 1832 { 1833 struct ppc_data *ppc = DEVTOSOFTC(dev); 1834 device_t *children; 1835 int nchildren, i; 1836 1837 if (ppc->res_irq == 0) { 1838 return (ENXIO); 1839 } 1840 1841 /* detach & delete all children */ 1842 if (!device_get_children(dev, &children, &nchildren)) { 1843 for (i = 0; i < nchildren; i++) 1844 if (children[i]) 1845 device_delete_child(dev, children[i]); 1846 free(children, M_TEMP); 1847 } 1848 1849 if (ppc->res_irq != 0) { 1850 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1851 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1852 ppc->res_irq); 1853 } 1854 if (ppc->res_ioport != 0) { 1855 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1856 ppc->res_ioport); 1857 } 1858 if (ppc->res_drq != 0) { 1859 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1860 ppc->res_drq); 1861 } 1862 1863 return (0); 1864 } 1865 1866 u_char 1867 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1868 { 1869 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1870 switch (iop) { 1871 case PPB_OUTSB_EPP: 1872 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 1873 break; 1874 case PPB_OUTSW_EPP: 1875 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1876 break; 1877 case PPB_OUTSL_EPP: 1878 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1879 break; 1880 case PPB_INSB_EPP: 1881 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 1882 break; 1883 case PPB_INSW_EPP: 1884 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1885 break; 1886 case PPB_INSL_EPP: 1887 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1888 break; 1889 case PPB_RDTR: 1890 return (r_dtr(ppc)); 1891 case PPB_RSTR: 1892 return (r_str(ppc)); 1893 case PPB_RCTR: 1894 return (r_ctr(ppc)); 1895 case PPB_REPP_A: 1896 return (r_epp_A(ppc)); 1897 case PPB_REPP_D: 1898 return (r_epp_D(ppc)); 1899 case PPB_RECR: 1900 return (r_ecr(ppc)); 1901 case PPB_RFIFO: 1902 return (r_fifo(ppc)); 1903 case PPB_WDTR: 1904 w_dtr(ppc, byte); 1905 break; 1906 case PPB_WSTR: 1907 w_str(ppc, byte); 1908 break; 1909 case PPB_WCTR: 1910 w_ctr(ppc, byte); 1911 break; 1912 case PPB_WEPP_A: 1913 w_epp_A(ppc, byte); 1914 break; 1915 case PPB_WEPP_D: 1916 w_epp_D(ppc, byte); 1917 break; 1918 case PPB_WECR: 1919 w_ecr(ppc, byte); 1920 break; 1921 case PPB_WFIFO: 1922 w_fifo(ppc, byte); 1923 break; 1924 default: 1925 panic("%s: unknown I/O operation", __func__); 1926 break; 1927 } 1928 1929 return (0); /* not significative */ 1930 } 1931 1932 int 1933 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1934 { 1935 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1936 1937 switch (index) { 1938 case PPC_IVAR_EPP_PROTO: 1939 *val = (u_long)ppc->ppc_epp; 1940 break; 1941 case PPC_IVAR_IRQ: 1942 *val = (u_long)ppc->ppc_irq; 1943 break; 1944 default: 1945 return (ENOENT); 1946 } 1947 1948 return (0); 1949 } 1950 1951 /* 1952 * Resource is useless here since ppbus devices' interrupt handlers are 1953 * multiplexed to the same resource initially allocated by ppc 1954 */ 1955 int 1956 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 1957 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep) 1958 { 1959 int error; 1960 struct ppc_data *ppc = DEVTOSOFTC(bus); 1961 1962 if (ppc->ppc_registered) { 1963 /* XXX refuse registration if DMA is in progress */ 1964 1965 /* first, unregister the default interrupt handler */ 1966 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 1967 bus, ppc->res_irq, ppc->intr_cookie))) 1968 return (error); 1969 1970 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 1971 /* ppc->res_irq); */ 1972 1973 /* DMA/FIFO operation won't be possible anymore */ 1974 ppc->ppc_registered = 0; 1975 } 1976 1977 /* 1978 * pass registration to the upper layer, ignore the incoming 1979 * resource 1980 */ 1981 return (BUS_SETUP_INTR(device_get_parent(bus), child, 1982 r, flags, filt, ihand, arg, cookiep)); 1983 } 1984 1985 /* 1986 * When no underlying device has a registered interrupt, register the ppc 1987 * layer one 1988 */ 1989 int 1990 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 1991 { 1992 int error; 1993 struct ppc_data *ppc = DEVTOSOFTC(bus); 1994 device_t parent = device_get_parent(bus); 1995 1996 /* pass unregistration to the upper layer */ 1997 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 1998 return (error); 1999 2000 /* default to the tty mask for registration */ /* XXX */ 2001 if (ppc->ppc_irq && 2002 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2003 INTR_TYPE_TTY, NULL, ppcintr, bus, &ppc->intr_cookie))) { 2004 2005 /* remember the ppcintr is registered */ 2006 ppc->ppc_registered = 1; 2007 } 2008 2009 return (error); 2010 } 2011 2012 MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2013