1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Maxim Sobolev <sobomax@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/module.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/sx.h> 37 #include <sys/uio.h> 38 39 #include <dev/ofw/openfirm.h> 40 #include <dev/ofw/ofw_bus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <machine/bus.h> 44 #include <machine/md_var.h> 45 #include <machine/pio.h> 46 #include <machine/resource.h> 47 48 #include <sys/rman.h> 49 50 #include <dev/powermac_nvram/powermac_nvramvar.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 /* 56 * Device interface. 57 */ 58 static int powermac_nvram_probe(device_t); 59 static int powermac_nvram_attach(device_t); 60 static int powermac_nvram_detach(device_t); 61 62 /* Helper functions */ 63 static int powermac_nvram_check(void *data); 64 static int chrp_checksum(int sum, uint8_t *, uint8_t *); 65 static uint32_t adler_checksum(uint8_t *, int); 66 static int erase_bank(device_t, uint8_t *); 67 static int write_bank(device_t, uint8_t *, uint8_t *); 68 69 /* 70 * Driver methods. 71 */ 72 static device_method_t powermac_nvram_methods[] = { 73 /* Device interface */ 74 DEVMETHOD(device_probe, powermac_nvram_probe), 75 DEVMETHOD(device_attach, powermac_nvram_attach), 76 DEVMETHOD(device_detach, powermac_nvram_detach), 77 { 0, 0 } 78 }; 79 80 static driver_t powermac_nvram_driver = { 81 "powermac_nvram", 82 powermac_nvram_methods, 83 sizeof(struct powermac_nvram_softc) 84 }; 85 86 DRIVER_MODULE(powermac_nvram, ofwbus, powermac_nvram_driver, 0, 0); 87 88 /* 89 * Cdev methods. 90 */ 91 92 static d_open_t powermac_nvram_open; 93 static d_close_t powermac_nvram_close; 94 static d_read_t powermac_nvram_read; 95 static d_write_t powermac_nvram_write; 96 97 static struct cdevsw powermac_nvram_cdevsw = { 98 .d_version = D_VERSION, 99 .d_open = powermac_nvram_open, 100 .d_close = powermac_nvram_close, 101 .d_read = powermac_nvram_read, 102 .d_write = powermac_nvram_write, 103 .d_name = "powermac_nvram", 104 }; 105 106 static int 107 powermac_nvram_probe(device_t dev) 108 { 109 const char *type, *compatible; 110 111 type = ofw_bus_get_type(dev); 112 compatible = ofw_bus_get_compat(dev); 113 114 if (type == NULL || compatible == NULL) 115 return ENXIO; 116 117 if (strcmp(type, "nvram") != 0) 118 return ENXIO; 119 if (strcmp(compatible, "amd-0137") != 0 && 120 !ofw_bus_is_compatible(dev, "nvram,flash")) 121 return ENXIO; 122 123 device_set_desc(dev, "Apple NVRAM"); 124 return 0; 125 } 126 127 static int 128 powermac_nvram_attach(device_t dev) 129 { 130 struct powermac_nvram_softc *sc; 131 const char *compatible; 132 phandle_t node; 133 u_int32_t reg[3]; 134 int gen0, gen1, i; 135 136 node = ofw_bus_get_node(dev); 137 sc = device_get_softc(dev); 138 139 if ((i = OF_getprop(node, "reg", reg, sizeof(reg))) < 8) 140 return ENXIO; 141 142 sc->sc_dev = dev; 143 sc->sc_node = node; 144 145 compatible = ofw_bus_get_compat(dev); 146 if (strcmp(compatible, "amd-0137") == 0) 147 sc->sc_type = FLASH_TYPE_AMD; 148 else 149 sc->sc_type = FLASH_TYPE_SM; 150 151 /* 152 * Find which byte of reg corresponds to the 32-bit physical address. 153 * We should probably read #address-cells from /chosen instead. 154 */ 155 i = (i/4) - 2; 156 157 sc->sc_bank0 = pmap_mapdev(reg[i], NVRAM_SIZE * 2); 158 sc->sc_bank1 = (char *)sc->sc_bank0 + NVRAM_SIZE; 159 160 gen0 = powermac_nvram_check(sc->sc_bank0); 161 gen1 = powermac_nvram_check(sc->sc_bank1); 162 163 if (gen0 == -1 && gen1 == -1) { 164 if (sc->sc_bank0 != NULL) 165 pmap_unmapdev(sc->sc_bank0, NVRAM_SIZE * 2); 166 device_printf(dev, "both banks appear to be corrupt\n"); 167 return ENXIO; 168 } 169 device_printf(dev, "bank0 generation %d, bank1 generation %d\n", 170 gen0, gen1); 171 172 sc->sc_bank = (gen0 > gen1) ? sc->sc_bank0 : sc->sc_bank1; 173 bcopy(sc->sc_bank, sc->sc_data, NVRAM_SIZE); 174 175 sc->sc_cdev = make_dev(&powermac_nvram_cdevsw, 0, 0, 0, 0600, 176 "powermac_nvram"); 177 sc->sc_cdev->si_drv1 = sc; 178 179 sx_init(&sc->sc_lock, "powermac_nvram"); 180 181 return 0; 182 } 183 184 static int 185 powermac_nvram_detach(device_t dev) 186 { 187 struct powermac_nvram_softc *sc; 188 189 sc = device_get_softc(dev); 190 191 if (sc->sc_bank0 != NULL) 192 pmap_unmapdev(sc->sc_bank0, NVRAM_SIZE * 2); 193 194 if (sc->sc_cdev != NULL) 195 destroy_dev(sc->sc_cdev); 196 197 sx_destroy(&sc->sc_lock); 198 199 return 0; 200 } 201 202 static int 203 powermac_nvram_open(struct cdev *dev, int flags, int fmt, struct thread *td) 204 { 205 struct powermac_nvram_softc *sc = dev->si_drv1; 206 int err; 207 208 err = 0; 209 sx_xlock(&sc->sc_lock); 210 if (sc->sc_isopen) 211 err = EBUSY; 212 else 213 sc->sc_isopen = 1; 214 sc->sc_rpos = sc->sc_wpos = 0; 215 sx_xunlock(&sc->sc_lock); 216 217 return (err); 218 } 219 220 static int 221 powermac_nvram_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 222 { 223 struct powermac_nvram_softc *sc = dev->si_drv1; 224 struct core99_header *header; 225 void *bank; 226 227 sx_xlock(&sc->sc_lock); 228 if (sc->sc_wpos != sizeof(sc->sc_data)) { 229 /* Short write, restore in-memory copy */ 230 bcopy(sc->sc_bank, sc->sc_data, NVRAM_SIZE); 231 sc->sc_isopen = 0; 232 sx_xunlock(&sc->sc_lock); 233 return 0; 234 } 235 236 header = (struct core99_header *)sc->sc_data; 237 238 header->generation = ((struct core99_header *)sc->sc_bank)->generation; 239 header->generation++; 240 header->chrp_header.signature = CORE99_SIGNATURE; 241 242 header->adler_checksum = 243 adler_checksum((uint8_t *)&(header->generation), 244 NVRAM_SIZE - offsetof(struct core99_header, generation)); 245 header->chrp_header.chrp_checksum = chrp_checksum(header->chrp_header.signature, 246 (uint8_t *)&(header->chrp_header.length), 247 (uint8_t *)&(header->adler_checksum)); 248 249 bank = (sc->sc_bank == sc->sc_bank0) ? sc->sc_bank1 : sc->sc_bank0; 250 if (erase_bank(sc->sc_dev, bank) != 0 || 251 write_bank(sc->sc_dev, bank, sc->sc_data) != 0) { 252 sc->sc_isopen = 0; 253 sx_xunlock(&sc->sc_lock); 254 return ENOSPC; 255 } 256 sc->sc_bank = bank; 257 sc->sc_isopen = 0; 258 sx_xunlock(&sc->sc_lock); 259 return 0; 260 } 261 262 static int 263 powermac_nvram_read(struct cdev *dev, struct uio *uio, int ioflag) 264 { 265 int rv, amnt, data_available; 266 struct powermac_nvram_softc *sc = dev->si_drv1; 267 268 rv = 0; 269 270 sx_xlock(&sc->sc_lock); 271 while (uio->uio_resid > 0) { 272 data_available = sizeof(sc->sc_data) - sc->sc_rpos; 273 if (data_available > 0) { 274 amnt = MIN(uio->uio_resid, data_available); 275 rv = uiomove((void *)(sc->sc_data + sc->sc_rpos), 276 amnt, uio); 277 if (rv != 0) 278 break; 279 sc->sc_rpos += amnt; 280 } else { 281 break; 282 } 283 } 284 sx_xunlock(&sc->sc_lock); 285 286 return rv; 287 } 288 289 static int 290 powermac_nvram_write(struct cdev *dev, struct uio *uio, int ioflag) 291 { 292 int rv, amnt, data_available; 293 struct powermac_nvram_softc *sc = dev->si_drv1; 294 295 if (sc->sc_wpos >= sizeof(sc->sc_data)) 296 return EINVAL; 297 298 rv = 0; 299 300 sx_xlock(&sc->sc_lock); 301 while (uio->uio_resid > 0) { 302 data_available = sizeof(sc->sc_data) - sc->sc_wpos; 303 if (data_available > 0) { 304 amnt = MIN(uio->uio_resid, data_available); 305 rv = uiomove((void *)(sc->sc_data + sc->sc_wpos), 306 amnt, uio); 307 if (rv != 0) 308 break; 309 sc->sc_wpos += amnt; 310 } else { 311 break; 312 } 313 } 314 sx_xunlock(&sc->sc_lock); 315 316 return rv; 317 } 318 319 static int 320 powermac_nvram_check(void *data) 321 { 322 struct core99_header *header; 323 324 header = (struct core99_header *)data; 325 326 if (header->chrp_header.signature != CORE99_SIGNATURE) 327 return -1; 328 if (header->chrp_header.chrp_checksum != 329 chrp_checksum(header->chrp_header.signature, 330 (uint8_t *)&(header->chrp_header.length), 331 (uint8_t *)&(header->adler_checksum))) 332 return -1; 333 if (header->adler_checksum != 334 adler_checksum((uint8_t *)&(header->generation), 335 NVRAM_SIZE - offsetof(struct core99_header, generation))) 336 return -1; 337 return header->generation; 338 } 339 340 static int 341 chrp_checksum(int sum, uint8_t *data, uint8_t *end) 342 { 343 344 for (; data < end; data++) 345 sum += data[0]; 346 while (sum > 0xff) 347 sum = (sum & 0xff) + (sum >> 8); 348 return sum; 349 } 350 351 static uint32_t 352 adler_checksum(uint8_t *data, int len) 353 { 354 uint32_t low, high; 355 int i; 356 357 low = 1; 358 high = 0; 359 for (i = 0; i < len; i++) { 360 if ((i % 5000) == 0) { 361 low %= 65521UL; 362 high %= 65521UL; 363 } 364 low += data[i]; 365 high += low; 366 } 367 low %= 65521UL; 368 high %= 65521UL; 369 370 return (high << 16) | low; 371 } 372 373 #define OUTB_DELAY(a, v) outb(a, v); DELAY(1); 374 375 static int 376 wait_operation_complete_amd(uint8_t *bank) 377 { 378 int i; 379 380 for (i = 1000000; i != 0; i--) 381 if ((inb(bank) ^ inb(bank)) == 0) 382 return 0; 383 return -1; 384 } 385 386 static int 387 erase_bank_amd(device_t dev, uint8_t *bank) 388 { 389 unsigned int i; 390 391 /* Unlock 1 */ 392 OUTB_DELAY(bank + 0x555, 0xaa); 393 /* Unlock 2 */ 394 OUTB_DELAY(bank + 0x2aa, 0x55); 395 396 /* Sector-Erase */ 397 OUTB_DELAY(bank + 0x555, 0x80); 398 OUTB_DELAY(bank + 0x555, 0xaa); 399 OUTB_DELAY(bank + 0x2aa, 0x55); 400 OUTB_DELAY(bank, 0x30); 401 402 if (wait_operation_complete_amd(bank) != 0) { 403 device_printf(dev, "flash erase timeout\n"); 404 return -1; 405 } 406 407 /* Reset */ 408 OUTB_DELAY(bank, 0xf0); 409 410 for (i = 0; i < NVRAM_SIZE; i++) { 411 if (bank[i] != 0xff) { 412 device_printf(dev, "flash erase has failed\n"); 413 return -1; 414 } 415 } 416 return 0; 417 } 418 419 static int 420 write_bank_amd(device_t dev, uint8_t *bank, uint8_t *data) 421 { 422 unsigned int i; 423 424 for (i = 0; i < NVRAM_SIZE; i++) { 425 /* Unlock 1 */ 426 OUTB_DELAY(bank + 0x555, 0xaa); 427 /* Unlock 2 */ 428 OUTB_DELAY(bank + 0x2aa, 0x55); 429 430 /* Write single word */ 431 OUTB_DELAY(bank + 0x555, 0xa0); 432 OUTB_DELAY(bank + i, data[i]); 433 if (wait_operation_complete_amd(bank) != 0) { 434 device_printf(dev, "flash write timeout\n"); 435 return -1; 436 } 437 } 438 439 /* Reset */ 440 OUTB_DELAY(bank, 0xf0); 441 442 for (i = 0; i < NVRAM_SIZE; i++) { 443 if (bank[i] != data[i]) { 444 device_printf(dev, "flash write has failed\n"); 445 return -1; 446 } 447 } 448 return 0; 449 } 450 451 static int 452 wait_operation_complete_sm(uint8_t *bank) 453 { 454 int i; 455 456 for (i = 1000000; i != 0; i--) { 457 outb(bank, SM_FLASH_CMD_READ_STATUS); 458 if (inb(bank) & SM_FLASH_STATUS_DONE) 459 return (0); 460 } 461 return (-1); 462 } 463 464 static int 465 erase_bank_sm(device_t dev, uint8_t *bank) 466 { 467 unsigned int i; 468 469 outb(bank, SM_FLASH_CMD_ERASE_SETUP); 470 outb(bank, SM_FLASH_CMD_ERASE_CONFIRM); 471 472 if (wait_operation_complete_sm(bank) != 0) { 473 device_printf(dev, "flash erase timeout\n"); 474 return (-1); 475 } 476 477 outb(bank, SM_FLASH_CMD_CLEAR_STATUS); 478 outb(bank, SM_FLASH_CMD_RESET); 479 480 for (i = 0; i < NVRAM_SIZE; i++) { 481 if (bank[i] != 0xff) { 482 device_printf(dev, "flash write has failed\n"); 483 return (-1); 484 } 485 } 486 return (0); 487 } 488 489 static int 490 write_bank_sm(device_t dev, uint8_t *bank, uint8_t *data) 491 { 492 unsigned int i; 493 494 for (i = 0; i < NVRAM_SIZE; i++) { 495 OUTB_DELAY(bank + i, SM_FLASH_CMD_WRITE_SETUP); 496 outb(bank + i, data[i]); 497 if (wait_operation_complete_sm(bank) != 0) { 498 device_printf(dev, "flash write error/timeout\n"); 499 break; 500 } 501 } 502 503 outb(bank, SM_FLASH_CMD_CLEAR_STATUS); 504 outb(bank, SM_FLASH_CMD_RESET); 505 506 for (i = 0; i < NVRAM_SIZE; i++) { 507 if (bank[i] != data[i]) { 508 device_printf(dev, "flash write has failed\n"); 509 return (-1); 510 } 511 } 512 return (0); 513 } 514 515 static int 516 erase_bank(device_t dev, uint8_t *bank) 517 { 518 struct powermac_nvram_softc *sc; 519 520 sc = device_get_softc(dev); 521 522 sx_assert(&sc->sc_lock, SA_XLOCKED); 523 if (sc->sc_type == FLASH_TYPE_AMD) 524 return (erase_bank_amd(dev, bank)); 525 else 526 return (erase_bank_sm(dev, bank)); 527 } 528 529 static int 530 write_bank(device_t dev, uint8_t *bank, uint8_t *data) 531 { 532 struct powermac_nvram_softc *sc; 533 534 sc = device_get_softc(dev); 535 536 sx_assert(&sc->sc_lock, SA_XLOCKED); 537 if (sc->sc_type == FLASH_TYPE_AMD) 538 return (write_bank_amd(dev, bank, data)); 539 else 540 return (write_bank_sm(dev, bank, data)); 541 } 542