1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 /** \file 25 * 26 * The file contains defines and data structures for SAS/SATA TD layer 27 * 28 */ 29 30 #ifndef __TDDEFS_H__ 31 #define __TDDEFS_H__ 32 33 34 35 #ifndef agTRUE 36 #define agTRUE 1 37 #endif 38 39 #ifndef agFALSE 40 #define agFALSE 0 41 #endif 42 43 #ifndef agNULL 44 #define agNULL ((void *)0) 45 #endif 46 47 #ifndef IN 48 #define IN 49 #endif 50 51 #ifndef OUT 52 #define OUT 53 #endif 54 55 #ifndef IN_OUT 56 #define IN_OUT 57 #endif 58 59 #ifndef os_bit8 60 #define os_bit8 bit8 61 #endif 62 63 #ifndef os_bit16 64 #define os_bit16 bit16 65 #endif 66 67 #ifndef os_bit32 68 #define os_bit32 bit32 69 #endif 70 71 #ifndef OFF 72 #define OFF 0 73 #endif 74 75 #ifndef ON 76 #define ON 1 77 #endif 78 79 #ifndef MIN 80 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 81 #endif 82 83 #ifndef MAX 84 #define MAX(a,b) ((a) < (b) ? (b) : (a)) 85 #endif 86 87 #define TD_OPERATION_INITIATOR 0x1 88 #define TD_OPERATION_TARGET 0x2 89 90 /* indices for mem_t structures */ 91 #define DEK_MEM_INDEX_1 15 92 #define DEK_MEM_INDEX_2 16 93 94 /* some useful macros */ 95 #ifndef AG_ALIGNSIZE 96 #define AG_ALIGNSIZE(count, alignment) (bit32) ( (bitptr)(count)+(bitptr)(alignment) ) 97 #endif 98 99 #define DEFAULT_KEY_BUFFER_SIZE 64 100 101 /**< the default maximum number of phys */ 102 #ifdef FPGA_CARD 103 104 #define TD_MAX_NUM_PHYS 2 105 106 #else 107 #define TD_MAX_NUM_PHYS 16 108 #define TD_MAX_CARD_NUM 20 109 #endif 110 111 #define TD_CARD_ID_FREE 0 112 #define TD_CARD_ID_ALLOC 1 113 #define TD_CARD_ID_LEN 128 114 115 /**< the maximum number of port context */ 116 /* should be the number of phyical phys in chip + 1 */ 117 #define TD_MAX_PORT_CONTEXT 16 118 /**< the maximum number of target device */ 119 /* For Initiator and Target 120 this is initial value for MaxTargets in the configuration(adj) file */ 121 #define DEFAULT_MAX_DEV 256 122 /* the maximum number of interrupt coalesce context */ 123 #define TD_MAX_INT_COALESCE 512 124 125 #if (defined(__FreeBSD__)) 126 #define MAX_OUTSTANDING_IO_PER_LUN 64 127 #else 128 #define MAX_OUTSTANDING_IO_PER_LUN 254 //64 129 #endif 130 131 /* default values */ 132 #define DEFAULT_MAX_ACTIVE_IOS 128 133 #define DEFAULT_NUM_REG_CLIENTS 256 134 #define DEFAULT_NUM_INBOUND_QUEUE 1 135 #define DEFAULT_NUM_OUTBOUND_QUEUE 1 136 #define DEFAULT_INBOUND_QUEUE_SIZE 512 137 #define DEFAULT_INBOUND_QUEUE_ELE_SIZE 128 138 #define DEFAULT_OUTBOUND_QUEUE_SIZE 512 139 #define DEFAULT_OUTBOUND_QUEUE_ELE_SIZE 128 140 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY 0 141 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_COUNT 1 142 #define DEFAULT_OUTBOUND_INTERRUPT_ENABLE 1 143 #define DEFAULT_INBOUND_QUEUE_PRIORITY 0 144 #define DEFAULT_QUEUE_OPTION 0 145 #define DEFAULT_FW_MAX_PORTS 8 146 147 148 149 /* SAS device type definition. SAS spec(r.7) p206 */ 150 #define SAS_NO_DEVICE 0 151 #define SAS_END_DEVICE 1 152 #define SAS_EDGE_EXPANDER_DEVICE 2 153 #define SAS_FANOUT_EXPANDER_DEVICE 3 154 155 /* routing attributes */ 156 #define SAS_ROUTING_DIRECT 0x00 157 #define SAS_ROUTING_SUBTRACTIVE 0x01 158 #define SAS_ROUTING_TABLE 0x02 159 160 #define SAS_CONNECTION_RATE_1_5G 0x08 161 #define SAS_CONNECTION_RATE_3_0G 0x09 162 #define SAS_CONNECTION_RATE_6_0G 0x0A 163 #define SAS_CONNECTION_RATE_12_0G 0x0B 164 165 /**< defines the maximum number of expanders */ 166 #define TD_MAX_EXPANDER_PHYS 256 167 /**< the maximum number of expanders at TD */ 168 #define TD_MAX_EXPANDER 128 169 170 /***************************************************************************** 171 ** SCSI Operation Codes (first byte in CDB) 172 *****************************************************************************/ 173 174 175 #define SCSIOPC_TEST_UNIT_READY 0x00 176 #define SCSIOPC_INQUIRY 0x12 177 #define SCSIOPC_MODE_SENSE_6 0x1A 178 #define SCSIOPC_MODE_SENSE_10 0x5A 179 #define SCSIOPC_MODE_SELECT_6 0x15 180 #define SCSIOPC_START_STOP_UNIT 0x1B 181 #define SCSIOPC_READ_CAPACITY_10 0x25 182 #define SCSIOPC_READ_CAPACITY_16 0x9E 183 #define SCSIOPC_READ_6 0x08 184 #define SCSIOPC_READ_10 0x28 185 #define SCSIOPC_READ_12 0xA8 186 #define SCSIOPC_READ_16 0x88 187 #define SCSIOPC_WRITE_6 0x0A 188 #define SCSIOPC_WRITE_10 0x2A 189 #define SCSIOPC_WRITE_12 0xAA 190 #define SCSIOPC_WRITE_16 0x8A 191 #define SCSIOPC_WRITE_VERIFY 0x2E 192 #define SCSIOPC_VERIFY_10 0x2F 193 #define SCSIOPC_VERIFY_12 0xAF 194 #define SCSIOPC_VERIFY_16 0x8F 195 #define SCSIOPC_REQUEST_SENSE 0x03 196 #define SCSIOPC_REPORT_LUN 0xA0 197 #define SCSIOPC_FORMAT_UNIT 0x04 198 #define SCSIOPC_SEND_DIAGNOSTIC 0x1D 199 #define SCSIOPC_WRITE_SAME_10 0x41 200 #define SCSIOPC_WRITE_SAME_16 0x93 201 #define SCSIOPC_READ_BUFFER 0x3C 202 #define SCSIOPC_WRITE_BUFFER 0x3B 203 204 #define SCSIOPC_GET_CONFIG 0x46 205 #define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a 206 #define SCSIOPC_REPORT_KEY 0xA4 207 #define SCSIOPC_SEND_KEY 0xA3 208 #define SCSIOPC_READ_DVD_STRUCTURE 0xAD 209 #define SCSIOPC_TOC 0x43 210 #define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E 211 #define SCSIOPC_READ_VERIFY 0x42 212 213 #define SCSIOPC_LOG_SENSE 0x4D 214 #define SCSIOPC_LOG_SELECT 0x4C 215 #define SCSIOPC_MODE_SELECT_6 0x15 216 #define SCSIOPC_MODE_SELECT_10 0x55 217 #define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35 218 #define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91 219 #define SCSIOPC_WRITE_AND_VERIFY_10 0x2E 220 #define SCSIOPC_WRITE_AND_VERIFY_12 0xAE 221 #define SCSIOPC_WRITE_AND_VERIFY_16 0x8E 222 #define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB 223 #define SCSIOPC_REASSIGN_BLOCKS 0x07 224 225 226 227 228 229 /***************************************************************************** 230 ** SCSI GENERIC 6 BYTE CDB 231 *****************************************************************************/ 232 typedef struct CBD6_s { 233 bit8 opcode; 234 bit8 rsv; /* not 100% correct */ 235 bit8 lba[2]; /* not 100% correct */ 236 bit8 len; 237 bit8 control; 238 } CDB6_t; 239 240 241 242 /***************************************************************************** 243 ** SCSI GENERIC 10 BYTE CDB 244 *****************************************************************************/ 245 typedef struct CBD10_s { 246 bit8 opcode; 247 bit8 rsv_service; 248 bit8 lba[4]; 249 bit8 rsv; 250 bit8 len[2]; 251 bit8 control; 252 } CDB10_t; 253 254 /***************************************************************************** 255 ** SCSI GENERIC 12 BYTE CDB 256 *****************************************************************************/ 257 typedef struct CBD12_s { 258 bit8 opcode; 259 bit8 rsv_service; 260 bit8 lba[4]; 261 bit8 len[4]; 262 bit8 rsv; 263 bit8 control; 264 } CDB12_t; 265 266 267 /***************************************************************************** 268 ** SCSI GENERIC 16 BYTE CDB 269 *****************************************************************************/ 270 typedef struct CBD16_s { 271 bit8 opcode; 272 bit8 rsv_service; 273 bit8 lba[4]; 274 bit8 add_cdb[4]; 275 bit8 len[4]; 276 bit8 rsv; 277 bit8 control; 278 } CDB16_t; 279 280 #define BLOCK_BYTE_LENGTH 512 281 282 /***************************************************************************** 283 ** SCSI STATUS BYTES 284 *****************************************************************************/ 285 286 #define SCSI_STATUS_GOOD 0x00 287 #define SCSI_STATUS_CHECK_CONDITION 0x02 288 #define SCSI_STATUS_BUSY 0x08 289 #define SCSI_STATUS_COMMAND_TERMINATED 0x22 290 #define SCSI_STATUS_TASK_SET_FULL 0x28 291 292 /***************************************************************************** 293 ** SAS TM Function data present see SAS spec p311 Table 109 (Revision 7) 294 *****************************************************************************/ 295 #define NO_DATA 0 296 #define RESPONSE_DATA 1 297 #define SENSE_DATA 2 298 299 /* 4 bytes, SAS spec p312 Table 110 (Revision 7) */ 300 #define RESPONSE_DATA_LEN 4 301 302 #define SAS_CMND 0 303 #define SAS_TM 1 304 305 /* SMP frame type */ 306 #define SMP_REQUEST 0x40 307 #define SMP_RESPONSE 0x41 308 309 #define SMP_INITIATOR 0x01 310 #define SMP_TARGET 0x02 311 312 /* default SMP timeout: 0xFFFF is the Maximum Allowed */ 313 #define DEFAULT_SMP_TIMEOUT 0xFFFF 314 315 /* SMP direct payload size limit: IOMB direct payload size = 48 */ 316 #define SMP_DIRECT_PAYLOAD_LIMIT 44 317 318 /* SMP function */ 319 #define SMP_REPORT_GENERAL 0x00 320 #define SMP_REPORT_MANUFACTURE_INFORMATION 0x01 321 #define SMP_READ_GPIO_REGISTER 0x02 322 #define SMP_DISCOVER 0x10 323 #define SMP_REPORT_PHY_ERROR_LOG 0x11 324 #define SMP_REPORT_PHY_SATA 0x12 325 #define SMP_REPORT_ROUTING_INFORMATION 0x13 326 #define SMP_WRITE_GPIO_REGISTER 0x82 327 #define SMP_CONFIGURE_ROUTING_INFORMATION 0x90 328 #define SMP_PHY_CONTROL 0x91 329 #define SMP_PHY_TEST_FUNCTION 0x92 330 #define SMP_PMC_SPECIFIC 0xC0 331 332 333 /* SMP function results */ 334 #define SMP_FUNCTION_ACCEPTED 0x00 335 #define UNKNOWN_SMP_FUNCTION 0x01 336 #define SMP_FUNCTION_FAILED 0x02 337 #define INVALID_REQUEST_FRAME_LENGTH 0x03 338 #define INVALID_EXPANDER_CHANGE_COUNT 0x04 339 #define SMP_FN_BUSY 0x05 340 #define INCOMPLETE_DESCRIPTOR_LIST 0x06 341 #define PHY_DOES_NOT_EXIST 0x10 342 #define INDEX_DOES_NOT_EXIST 0x11 343 #define PHY_DOES_NOT_SUPPORT_SATA 0x12 344 #define UNKNOWN_PHY_OPERATION 0x13 345 #define UNKNOWN_PHY_TEST_FUNCTION 0x14 346 #define PHY_TEST_FUNCTION_IN_PROGRESS 0x15 347 #define PHY_VACANT 0x16 348 #define UNKNOWN_PHY_EVENT_SOURCE 0x17 349 #define UNKNOWN_DESCRIPTOT_TYPE 0x18 350 #define UNKNOWN_PHY_FILETER 0x19 351 #define AFFILIATION_VIOLATION 0x1A 352 #define SMP_ZONE_VIOLATION 0x20 353 #define NO_MANAGEMENT_ACCESS_RIGHTS 0x21 354 #define UNKNOWN_ENABLE_DISABLE_ZONING_VALUE 0x22 355 #define ZONE_LOCK_VIOLATION 0x23 356 #define NOT_ACTIVATED 0x24 357 #define ZONE_GROUP_OUT_OF_RANGE 0x25 358 #define NO_PHYSICAL_PRESENCE 0x26 359 #define SAVING_NOT_SUPPORTED 0x27 360 #define SOURCE_ZONE_GROUP_DOES_NOT_EXIST 0x28 361 #define DISABLED_PASSWORD_NOT_SUPPORTED 0x29 362 363 /* SMP PHY CONTROL OPERATION */ 364 #define SMP_PHY_CONTROL_NOP 0x00 365 #define SMP_PHY_CONTROL_LINK_RESET 0x01 366 #define SMP_PHY_CONTROL_HARD_RESET 0x02 367 #define SMP_PHY_CONTROL_DISABLE 0x03 368 #define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 369 #define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 370 #define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 371 372 373 #define IT_NEXUS_TIMEOUT 0x7D0 /* 2000 ms; old value was 0xFFFF */ 374 375 #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30) /* 5000 ms; in 100ms; should be large than IT_NEXUS_TIMEOUT */ 376 377 #define STP_IDLE_TIME 5 /* 5 us; the defaulf of the controller */ 378 379 #define SET_ESGL_EXTEND(val) \ 380 ((val) = (val) | 0x80000000) 381 382 #define CLEAR_ESGL_EXTEND(val) \ 383 ((val) = (val) & 0x7FFFFFFF) 384 385 #define DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ 386 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) 387 388 #define DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ 389 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) 390 391 /* this macro is based on SAS spec, not sTSDK 0xC0 */ 392 #define DEVINFO_GET_DEVICETTYPE(devInfo) \ 393 (((devInfo)->devType_S_Rate & 0xC0) >> 6) 394 395 #define DEVINFO_GET_LINKRATE(devInfo) \ 396 ((devInfo)->devType_S_Rate & 0x0F) 397 398 #define DEVINFO_GET_EXT_MCN(devInfo) \ 399 (((devInfo)->ext & 0x7800) >> 11) 400 401 402 #define DEVINFO_PUT_SMPTO(devInfo, smpto) \ 403 ((devInfo)->smpTimeout) = smpto 404 405 #define DEVINFO_PUT_ITNEXUSTO(devInfo, itnexusto) \ 406 ((devInfo)->it_NexusTimeout) = itnexusto 407 408 #define DEVINFO_PUT_FBS(devInfo, fbs) \ 409 ((devInfo)->firstBurstSize) = fbs 410 411 #define DEVINFO_PUT_FLAG(devInfo, tlr) \ 412 ((devInfo)->flag) = tlr 413 414 #define DEVINFO_PUT_DEV_S_RATE(devInfo, dev_s_rate) \ 415 ((devInfo)->devType_S_Rate) = dev_s_rate 416 417 #define DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ 418 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 419 420 #define DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ 421 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 422 423 #define DEVICE_SSP_BIT 0x8 /* SSP Initiator port */ 424 #define DEVICE_STP_BIT 0x4 /* STP Initiator port */ 425 #define DEVICE_SMP_BIT 0x2 /* SMP Initiator port */ 426 #define DEVICE_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */ 427 428 #define DEVICE_IS_SSP_INITIATOR(DeviceData) \ 429 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) 430 431 #define DEVICE_IS_STP_INITIATOR(DeviceData) \ 432 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) 433 434 #define DEVICE_IS_SMP_INITIATOR(DeviceData) \ 435 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) 436 437 #define DEVICE_IS_SSP_TARGET(DeviceData) \ 438 (((DeviceData)->target_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT) 439 440 #define DEVICE_IS_STP_TARGET(DeviceData) \ 441 (((DeviceData)->target_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT) 442 443 #define DEVICE_IS_SMP_TARGET(DeviceData) \ 444 (((DeviceData)->target_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT) 445 446 #define DEVICE_IS_SATA_DEVICE(DeviceData) \ 447 (((DeviceData)->target_ssp_stp_smp & DEVICE_SATA_BIT) == DEVICE_SATA_BIT) 448 449 450 451 452 /* Negotiated Phyical Link Rate 453 #define Phy_ENABLED_UNKNOWN 454 */ 455 /* old SMP header definition */ 456 typedef struct tdssSMPFrameHeader_s 457 { 458 bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ 459 bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ 460 bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ 461 bit8 smpReserved; /* reserved */ 462 } tdssSMPFrameHeader_t; 463 464 /**************************************************************** 465 * report general request 466 ****************************************************************/ 467 #ifdef FOR_COMPLETENESS 468 typedef struct smpReqReportGeneral_s 469 { 470 /* nothing. some compiler disallowed structure with no member */ 471 } smpReqReportGeneral_t; 472 #endif 473 474 /**************************************************************** 475 * report general response 476 ****************************************************************/ 477 #define REPORT_GENERAL_CONFIGURING_BIT 0x2 478 #define REPORT_GENERAL_CONFIGURABLE_BIT 0x1 479 480 typedef struct smpRespReportGeneral_s 481 { 482 bit8 expanderChangeCount16[2]; 483 bit8 expanderRouteIndexes16[2]; 484 bit8 reserved1; 485 bit8 numOfPhys; 486 bit8 configuring_configurable; 487 /* B7-2 : reserved */ 488 /* B1 : configuring */ 489 /* B0 : configurable */ 490 bit8 reserved4[17]; 491 } smpRespReportGeneral_t; 492 493 #define REPORT_GENERAL_IS_CONFIGURING(pResp) \ 494 (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURING_BIT) == \ 495 REPORT_GENERAL_CONFIGURING_BIT) 496 497 #define REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ 498 (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURABLE_BIT) == \ 499 REPORT_GENERAL_CONFIGURABLE_BIT) 500 501 #define REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ 502 DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16)) 503 504 505 /**************************************************************** 506 * report manufacturer info response 507 ****************************************************************/ 508 typedef struct smpRespReportManufactureInfo_s 509 { 510 bit8 reserved1[8]; 511 bit8 vendorIdentification[8]; 512 bit8 productIdentification[16]; 513 bit8 productRevisionLevel[4]; 514 bit8 vendorSpecific[20]; 515 } smpRespReportManufactureInfo_t; 516 517 /**************************************************************** 518 * discover request 519 ****************************************************************/ 520 typedef struct smpReqDiscover_s 521 { 522 bit32 reserved1; 523 bit8 reserved2; 524 bit8 phyIdentifier; 525 bit8 ignored; 526 bit8 reserved3; 527 } smpReqDiscover_t; 528 529 /**************************************************************** 530 * discover response 531 ****************************************************************/ 532 typedef struct smpRespDiscover_s 533 { 534 bit8 reserved1[4]; 535 bit8 reserved2; 536 bit8 phyIdentifier; 537 bit8 reserved3[2]; 538 bit8 attachedDeviceType; 539 /* B7 : reserved */ 540 /* B6-4 : attachedDeviceType */ 541 /* B3-0 : reserved */ 542 bit8 negotiatedPhyLinkRate; 543 /* B7-4 : reserved */ 544 /* B3-0 : negotiatedPhyLinkRate */ 545 bit8 attached_Ssp_Stp_Smp_Sata_Initiator; 546 /* B7-4 : reserved */ 547 /* B3 : attachedSspInitiator */ 548 /* B2 : attachedStpInitiator */ 549 /* B1 : attachedSmpInitiator */ 550 /* B0 : attachedSataHost */ 551 bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target; 552 /* B7 : attachedSataPortSelector */ 553 /* B6-4 : reserved */ 554 /* B3 : attachedSspTarget */ 555 /* B2 : attachedStpTarget */ 556 /* B1 : attachedSmpTarget */ 557 /* B0 : attachedSatadevice */ 558 bit8 sasAddressHi[4]; 559 bit8 sasAddressLo[4]; 560 bit8 attachedSasAddressHi[4]; 561 bit8 attachedSasAddressLo[4]; 562 bit8 attachedPhyIdentifier; 563 bit8 reserved9[7]; 564 bit8 programmedAndHardware_MinPhyLinkRate; 565 /* B7-4 : programmedMinPhyLinkRate */ 566 /* B3-0 : hardwareMinPhyLinkRate */ 567 bit8 programmedAndHardware_MaxPhyLinkRate; 568 /* B7-4 : programmedMaxPhyLinkRate */ 569 /* B3-0 : hardwareMaxPhyLinkRate */ 570 bit8 phyChangeCount; 571 bit8 virtualPhy_partialPathwayTimeout; 572 /* B7 : virtualPhy*/ 573 /* B6-4 : reserved */ 574 /* B3-0 : partialPathwayTimeout */ 575 bit8 routingAttribute; 576 /* B7-4 : reserved */ 577 /* B3-0 : routingAttribute */ 578 bit8 reserved13[5]; 579 bit8 vendorSpecific[2]; 580 } smpRespDiscover_t; 581 582 #define DISCRSP_SSP_BIT 0x08 583 #define DISCRSP_STP_BIT 0x04 584 #define DISCRSP_SMP_BIT 0x02 585 #define DISCRSP_SATA_BIT 0x01 586 587 #define DISCRSP_SATA_PS_BIT 0x80 588 589 #define DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ 590 (((pResp)->attachedDeviceType & 0x70) >> 4) 591 #define DISCRSP_GET_LINKRATE(pResp) \ 592 ((bit8)((pResp)->negotiatedPhyLinkRate & 0x0F)) 593 594 #define DISCRSP_IS_SSP_INITIATOR(pResp) \ 595 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) 596 #define DISCRSP_IS_STP_INITIATOR(pResp) \ 597 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) 598 #define DISCRSP_IS_SMP_INITIATOR(pResp) \ 599 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) 600 #define DISCRSP_IS_SATA_HOST(pResp) \ 601 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) 602 603 #define DISCRSP_IS_SSP_TARGET(pResp) \ 604 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT) 605 #define DISCRSP_IS_STP_TARGET(pResp) \ 606 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_STP_BIT) == DISCRSP_STP_BIT) 607 #define DISCRSP_IS_SMP_TARGET(pResp) \ 608 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT) 609 #define DISCRSP_IS_SATA_DEVICE(pResp) \ 610 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT) 611 #define DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ 612 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_PS_BIT) == DISCRSP_SATA_PS_BIT) 613 614 #define DISCRSP_GET_SAS_ADDRESSHI(pResp) \ 615 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi) 616 #define DISCRSP_GET_SAS_ADDRESSLO(pResp) \ 617 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo) 618 619 #define DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ 620 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi) 621 #define DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ 622 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo) 623 624 #define DISCRSP_VIRTUALPHY_BIT 0x80 625 #define DISCRSP_IS_VIRTUALPHY(pResp) \ 626 (((pResp)->virtualPhy_partialPathwayTimeout & DISCRSP_VIRTUALPHY_BIT) == DISCRSP_VIRTUALPHY_BIT) 627 628 #define DISCRSP_GET_ROUTINGATTRIB(pResp) \ 629 ((bit8)((pResp)->routingAttribute & 0x0F)) 630 631 /**************************************************************** 632 * report route table request 633 ****************************************************************/ 634 typedef struct smpReqReportRouteTable_s 635 { 636 bit8 reserved1[2]; 637 bit8 expanderRouteIndex16[20]; 638 bit8 reserved2; 639 bit8 phyIdentifier; 640 bit8 reserved3[2]; 641 } smpReqReportRouteTable_t; 642 643 /**************************************************************** 644 * report route response 645 ****************************************************************/ 646 typedef struct smpRespReportRouteTable_s 647 { 648 bit8 reserved1[2]; 649 bit8 expanderRouteIndex16[2]; 650 bit8 reserved2; 651 bit8 phyIdentifier; 652 bit8 reserved3[2]; 653 bit8 disabled; 654 /* B7 : expander route entry disabled */ 655 /* B6-0 : reserved */ 656 bit8 reserved5[3]; 657 bit8 routedSasAddressHi32[4]; 658 bit8 routedSasAddressLo32[4]; 659 bit8 reserved6[16]; 660 } smpRespReportRouteTable_t; 661 662 /**************************************************************** 663 * configure route information request 664 ****************************************************************/ 665 typedef struct smpReqConfigureRouteInformation_s 666 { 667 bit8 reserved1[2]; 668 bit8 expanderRouteIndex[2]; 669 bit8 reserved2; 670 bit8 phyIdentifier; 671 bit8 reserved3[2]; 672 bit8 disabledBit_reserved4; 673 bit8 reserved5[3]; 674 bit8 routedSasAddressHi[4]; 675 bit8 routedSasAddressLo[4]; 676 bit8 reserved6[16]; 677 } smpReqConfigureRouteInformation_t; 678 679 /**************************************************************** 680 * configure route response 681 ****************************************************************/ 682 #ifdef FOR_COMPLETENESS 683 typedef struct smpRespConfigureRouteInformation_s 684 { 685 /* nothing. some compiler disallowed structure with no member */ 686 } smpRespConfigureRouteInformation_t; 687 #endif 688 689 /**************************************************************** 690 * report Phy Sata request 691 ****************************************************************/ 692 typedef struct smpReqReportPhySata_s 693 { 694 bit8 reserved1[4]; 695 bit8 reserved2; 696 bit8 phyIdentifier; 697 bit8 reserved3[2]; 698 } smpReqReportPhySata_t; 699 700 /**************************************************************** 701 * report Phy Sata response 702 ****************************************************************/ 703 typedef struct smpRespReportPhySata_s 704 { 705 bit8 reserved1[4]; 706 bit8 reserved2; 707 bit8 phyIdentifier; 708 bit8 reserved3; 709 bit8 affiliations_sup_valid; 710 /* b7-2 : reserved */ 711 /* b1 : Affiliations supported */ 712 /* b0 : Affiliation valid */ 713 bit8 reserved5[4]; 714 bit8 stpSasAddressHi[4]; 715 bit8 stpSasAddressLo[4]; 716 bit8 regDevToHostFis[20]; 717 bit8 reserved6[4]; 718 bit8 affiliatedStpInitiatorSasAddressHi[4]; 719 bit8 affiliatedStpInitiatorSasAddressLo[4]; 720 } smpRespReportPhySata_t; 721 722 723 /**************************************************************** 724 * Phy Control request 725 ****************************************************************/ 726 typedef struct smpReqPhyControl_s 727 { 728 bit8 reserved1[4]; 729 bit8 reserved2; 730 bit8 phyIdentifier; 731 bit8 phyOperation; 732 bit8 updatePartialPathwayTOValue; 733 /* b7-1 : reserved */ 734 /* b0 : update partial pathway timeout value */ 735 bit8 reserved3[20]; 736 bit8 programmedMinPhysicalLinkRate; 737 /* b7-4 : programmed Minimum Physical Link Rate*/ 738 /* b3-0 : reserved */ 739 bit8 programmedMaxPhysicalLinkRate; 740 /* b7-4 : programmed Maximum Physical Link Rate*/ 741 /* b3-0 : reserved */ 742 bit8 reserved4[2]; 743 bit8 partialPathwayTOValue; 744 /* b7-4 : reserved */ 745 /* b3-0 : partial Pathway TO Value */ 746 bit8 reserved5[3]; 747 } smpReqPhyControl_t; 748 749 /**************************************************************** 750 * Phy Control response 751 ****************************************************************/ 752 #ifdef FOR_COMPLETENESS 753 typedef struct smpRespPhyControl_s 754 { 755 /* nothing. some compiler disallowed structure with no member */ 756 } smpRespPhyControl_t; 757 #endif 758 759 760 /***************************************************************************** 761 ** SCSI SENSE KEY VALUES 762 *****************************************************************************/ 763 764 #define SCSI_SNSKEY_NO_SENSE 0x00 765 #define SCSI_SNSKEY_RECOVERED_ERROR 0x01 766 #define SCSI_SNSKEY_NOT_READY 0x02 767 #define SCSI_SNSKEY_MEDIUM_ERROR 0x03 768 #define SCSI_SNSKEY_HARDWARE_ERROR 0x04 769 #define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05 770 #define SCSI_SNSKEY_UNIT_ATTENTION 0x06 771 #define SCSI_SNSKEY_DATA_PROTECT 0x07 772 #define SCSI_SNSKEY_ABORTED_COMMAND 0x0B 773 #define SCSI_SNSKEY_MISCOMPARE 0x0E 774 775 /***************************************************************************** 776 ** SCSI Additional Sense Codes and Qualifiers combo two-bytes 777 *****************************************************************************/ 778 779 #define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000 780 #define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803 781 #define SCSI_SNSCODE_INVALID_COMMAND 0x2000 782 #define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100 783 #define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400 784 #define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500 785 #define SCSI_SNSCODE_POWERON_RESET 0x2900 786 #define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00 787 #define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400 788 #define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00 789 #define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100 790 #define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401 791 #define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800 792 #define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01 793 #define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703 794 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404 795 #define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10 796 #define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00 797 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402 798 #define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600 799 #define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471 800 #define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B 801 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03 802 #define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00 803 #define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100 804 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01 805 #define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300 806 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402 807 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400 808 #define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500 809 #define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000 810 #define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00 811 #define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02 812 /***************************************************************************** 813 ** SCSI Additional Sense Codes and Qualifiers saparate bytes 814 *****************************************************************************/ 815 816 #define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04 817 #define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02 818 819 820 /***************************************************************************** 821 ** Inquiry command fields and response sizes 822 *****************************************************************************/ 823 #define SCSIOP_INQUIRY_CMDDT 0x02 824 #define SCSIOP_INQUIRY_EVPD 0x01 825 #define STANDARD_INQUIRY_SIZE 36 826 #define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */ 827 #define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */ 828 #define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */ 829 #define SATA_PAGE0_INQUIRY_SIZE 8 /* SPC-4, 7.6.9 Table331, p345 */ 830 #define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */ 831 832 833 /* not sure here */ 834 /* define byte swap macro */ 835 #define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ 836 ((((bit16)(_x))&0xFF00)>>8))) 837 838 #define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ 839 ((((bit32)(_x))&0x0000FF00)<<8)| \ 840 ((((bit32)(_x))&0x00FF0000)>>8)| \ 841 ((((bit32)(_x))&0xFF000000)>>24))) 842 843 844 /********************************************************************* 845 ** BUFFER CONVERTION MACROS 846 *********************************************************************/ 847 848 /********************************************************************* 849 * CPU buffer access macro * 850 * * 851 */ 852 853 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 854 (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 855 856 857 #if defined(SA_CPU_LITTLE_ENDIAN) 858 859 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 860 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 861 862 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 863 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 864 865 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 866 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 867 868 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 869 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 870 871 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 872 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 873 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 874 875 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 876 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 877 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 878 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 879 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 880 881 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 882 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 883 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 884 885 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 886 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 887 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 888 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 889 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 890 891 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 892 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 893 894 895 #elif defined(SA_CPU_BIG_ENDIAN) 896 897 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 898 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 899 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 900 901 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 902 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 903 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 904 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 905 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 906 907 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 908 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 909 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 910 911 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 912 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 913 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 914 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 915 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 916 917 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 918 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 919 920 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 921 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 922 923 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 924 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 925 926 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 927 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 928 929 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 930 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 931 932 #else 933 934 #error (Host CPU endianess undefined!!) 935 936 #endif 937 938 939 #if defined(SA_CPU_LITTLE_ENDIAN) 940 941 #ifndef LEBIT16_TO_BIT16 942 #define LEBIT16_TO_BIT16(_x) (_x) 943 #endif 944 945 #ifndef BIT16_TO_LEBIT16 946 #define BIT16_TO_LEBIT16(_x) (_x) 947 #endif 948 949 #ifndef BIT16_TO_BEBIT16 950 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 951 #endif 952 953 #ifndef BEBIT16_TO_BIT16 954 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 955 #endif 956 957 #ifndef LEBIT32_TO_BIT32 958 #define LEBIT32_TO_BIT32(_x) (_x) 959 #endif 960 961 #ifndef BIT32_TO_LEBIT32 962 #define BIT32_TO_LEBIT32(_x) (_x) 963 #endif 964 965 966 #ifndef BEBIT32_TO_BIT32 967 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 968 #endif 969 970 #ifndef BIT32_TO_BEBIT32 971 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 972 #endif 973 974 #elif defined(SA_CPU_BIG_ENDIAN) 975 976 #ifndef LEBIT16_TO_BIT16 977 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 978 #endif 979 980 #ifndef BIT16_TO_LEBIT16 981 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 982 #endif 983 984 #ifndef BIT16_TO_BEBIT16 985 #define BIT16_TO_BEBIT16(_x) (_x) 986 #endif 987 988 #ifndef BEBIT16_TO_BIT16 989 #define BEBIT16_TO_BIT16(_x) (_x) 990 #endif 991 992 #ifndef LEBIT32_TO_BIT32 993 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 994 #endif 995 996 #ifndef BIT32_TO_LEBIT32 997 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 998 #endif 999 1000 #ifndef BEBIT32_TO_BIT32 1001 #define BEBIT32_TO_BIT32(_x) (_x) 1002 #endif 1003 1004 #ifndef BIT32_TO_BEBIT32 1005 #define BIT32_TO_BEBIT32(_x) (_x) 1006 #endif 1007 1008 #else 1009 1010 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 1011 1012 #endif 1013 1014 1015 #define TargetUnknown 0 1016 #define TargetRead 1 1017 #define TargetWrite 2 1018 1019 1020 #define CDB_GRP_MASK 0xE0 /* 1110 0000 */ 1021 #define CDB_6BYTE 0x00 1022 #define CDB_10BYTE1 0x20 1023 #define CDB_10BYTE2 0x40 1024 #define CDB_12BYTE 0xA0 1025 #define CDB_16BYTE 0x80 1026 1027 /* ATA device type */ 1028 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ 1029 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ 1030 #define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ 1031 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ 1032 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ 1033 #define UNKNOWN_DEVICE 0xFF 1034 1035 /**************************************************************** 1036 * SATA Specification related defines * 1037 ****************************************************************/ 1038 #define SATA_MAX_QUEUED_COMMANDS 32 1039 #define SATA_MAX_PM_PORTS 15 1040 1041 1042 /* PMC IOCTL signature */ 1043 #define PMC_IOCTL_SIGNATURE 0x1234 1044 1045 1046 1047 /* 1048 * FIS type 1049 */ 1050 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F 1051 #define REG_DEV_TO_HOST_FIS 0x34 1052 #define SET_DEV_BITS_FIS 0xA1 1053 1054 #define TD_ASSERT OS_ASSERT 1055 1056 #ifdef TD_DISCOVER 1057 #define TDSA_DISCOVERY_OPTION_FULL_START 0 1058 #define TDSA_DISCOVERY_OPTION_INCREMENTAL_START 1 1059 #define TDSA_DISCOVERY_OPTION_ABORT 2 1060 1061 #define TDSA_DISCOVERY_TYPE_SAS 0 1062 #define TDSA_DISCOVERY_TYPE_SATA 1 1063 1064 1065 #define DISCOVERY_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */ 1066 #define DISCOVERY_RETRIES 3 1067 #define CONFIGURE_ROUTE_TIMER_VALUE (1 * 1000 * 1000) /* 1 seconds */ 1068 #define DEVICE_REGISTRATION_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */ 1069 #define SMP_RETRIES 5 1070 #define SMP_BUSY_TIMER_VALUE (1 * 1000 * 1000) /* 1 second */ 1071 #define SMP_BUSY_RETRIES 5 1072 #define SATA_ID_DEVICE_DATA_TIMER_VALUE (3 * 1000 * 1000) /* 3 second */ 1073 #define SATA_ID_DEVICE_DATA_RETRIES 3 1074 #define BC_TIMER_VALUE (5 * 1000 * 1000 ) /* 5 second */ 1075 #define SMP_TIMER_VALUE (10 * 1000 * 1000) /* 10 second */ 1076 1077 #endif 1078 #define STP_DEVICE_TYPE 0 /* SATA behind expander 00*/ 1079 #define SAS_DEVICE_TYPE 1 /* SSP or SMP 01 */ 1080 #define SATA_DEVICE_TYPE 2 /* direct SATA 10 */ 1081 1082 #define ATAPI_DEVICE_FLAG 0x200000 /* ATAPI device flag*/ 1083 1084 #define TD_INTERNAL_TM_RESET 0xFF 1085 1086 /* in terms of Kbytes*/ 1087 #define HOST_EVENT_LOG_SIZE 128 1088 #define DEFAULT_EVENT_LOG_OPTION 3 1089 1090 /* Device state */ 1091 #define SAT_DEV_STATE_NORMAL 0 /* Normal */ 1092 #define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */ 1093 #define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */ 1094 #define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/ 1095 #define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/ 1096 1097 #define TD_GET_PHY_ID(input) (input & 0x0F) 1098 #define TD_GET_PHY_NUMS(input) ((input & 0xF0) >> 4) 1099 #define TD_GET_LINK_RATE(input) ((input & 0xFF00) >> 8) 1100 #define TD_GET_PORT_STATE(input) ((input & 0xF0000) >> 16) 1101 #define TD_GET_PHY_STATUS(input) ((input & 0xFF00) >> 8) 1102 #define TD_GET_RESET_STATUS(input) ((input & 0xFF00) >> 8) 1103 1104 #define TD_MAX_NUM_NOTIFY_SPINUP 20 1105 1106 #define SPC_VPD_SIGNATURE 0xFEDCBA98 1107 1108 #define TD_GET_FRAME_TYPE(input) (input & 0xFF) 1109 #define TD_GET_TLR(input) ((input & 0x300) >> 8) 1110 1111 /* PORT RESET TMO is in 100ms */ 1112 #define SAS_PORT_RESET_TMO 3 /* 300 ms */ 1113 #define SATA_PORT_RESET_TMO 80 /* 8000 ms = 8 sec */ 1114 #define SAS_12G_PORT_RESET_TMO 8 /* 800 ms */ 1115 1116 /* task attribute based on sTSDK API */ 1117 #define TD_TASK_SIMPLE 0x0 /* Simple */ 1118 #define TD_TASK_ORDERED 0x2 /* Ordered */ 1119 #define TD_TASK_HEAD_OF_QUEUE 0x1 /* Head of Queue */ 1120 #define TD_TASK_ACA 0x4 /* ACA */ 1121 1122 /* compiler flag for direct smp */ 1123 #define DIRECT_SMP 1124 //#undef DIRECT_SMP 1125 1126 #define CONFIGURE_FW_MAX_PORTS 0x20000000 1127 1128 #define NO_ACK 0xFFFF 1129 1130 #define OPEN_RETRY_RETRIES 10 1131 1132 #ifdef AGTIAPI_CTL 1133 /* scsi command/page */ 1134 #define MODE_SELECT 0x15 1135 #define PAGE_FORMAT 0x10 1136 #define DR_MODE_PG_SZ 16 1137 #define DR_MODE_PG_CODE 0x02 1138 #define DR_MODE_PG_LENGTH 0x0e 1139 #endif /* AGTIAPI_CTL */ 1140 1141 enum td_locks_e 1142 { 1143 /* for tdsaAllShared->FreeDeviceList, tdsaAllShared->MainDeviceList, 1144 oneDeviceData->MainLink, oneDeviceData->FreeLink */ 1145 TD_DEVICE_LOCK, 1146 /* for tdsaAllShared->FreePortContextList, tdsaAllShared->MainPortContextList, 1147 onePortContext->MainLink, onePortContext->FreeLink */ 1148 TD_PORT_LOCK, 1149 /* for onePortContext->discovery.discoveringExpanderList, 1150 onePortContext->discovery.UpdiscoveringExpanderList, 1151 tdsaAllShared->freeExpanderList */ 1152 TD_DISC_LOCK, 1153 /* for onePortContext->discovery.DiscoverySMPTimer, 1154 oneDeviceData->SATAIDDeviceTimer, discovery->discoveryTimer, 1155 discovery->SMPBusyTimer, discovery->BCTimer, 1156 discovery->deviceRegistrationTimer, discovery->configureRouteTimer, 1157 tdsaAllShared->itdsaIni->timerlist, tdsaAllShared->timerlist */ 1158 TD_TIMER_LOCK, 1159 #ifdef INITIATOR_DRIVER 1160 /* for tdsaAllShared->pEsglAllInfo->freelist 1161 tdsaAllShared->pEsglAllInfo->NumFreeEsglPages 1162 tdsaAllShared->pEsglPageInfo->tdlist */ 1163 TD_ESGL_LOCK, 1164 /* for satIOContext->pSatDevData->satVerifyState, 1165 satIOContext->pSatDevData->satSectorDone, 1166 satIOContext->pSatDevData->satPendingNCQIO, 1167 satIOContext->pSatDevData->satPendingIO, 1168 satIOContext->pSatDevData->satPendingNONNCQIO, 1169 satIOContext->pSatDevData->satFreeIntIoLinkList, 1170 satIOContext->pSatDevData->satActiveIntIoLinkList, 1171 satIOContext->pSatDevData->freeSATAFDMATagBitmap, 1172 satIOContext->satIoContextLink, 1173 oneDeviceData->satDevData.satIoLinkList */ 1174 TD_SATA_LOCK, 1175 #ifdef TD_INT_COALESCE 1176 /* for tdsaIntCoalCxt->FreeLink, tdsaIntCoalCxt->MainLink, 1177 tdsaIntCoalCxtHead->FreeLink, tdsaIntCoalCxtHead->MainLink */ 1178 TD_INTCOAL_LOCK, 1179 #endif 1180 #endif 1181 #ifdef TARGET_DRIVER 1182 /* for tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgFreeList, 1183 tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgBusyList */ 1184 TD_TGT_LOCK, 1185 #endif 1186 TD_MAX_LOCKS 1187 }; 1188 1189 #define TD_GET_SAS_ADDRESSLO(sasAddressLo) \ 1190 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) 1191 1192 #define TD_GET_SAS_ADDRESSHI(sasAddressHi) \ 1193 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) 1194 1195 #define TD_XFER_RDY_PRIORTY_DEVICE_FLAG (1 << 22) 1196 1197 1198 #ifdef FDS_DM 1199 /* bit32 -> bit8 array[4] */ 1200 #define PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(portInfo, src32) \ 1201 *(bit32 *)((portInfo)->sasLocalAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 1202 1203 #define PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(portInfo, src32) \ 1204 *(bit32 *)((portInfo)->sasLocalAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 1205 /* bit32 -> bit8 array[4] */ 1206 #define PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(portInfo, src32) \ 1207 *(bit32 *)((portInfo)->sasRemoteAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 1208 #define PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(portInfo, src32) \ 1209 *(bit32 *)((portInfo)->sasRemoteAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 1210 #endif /* FDS_DM */ 1211 1212 #ifdef FDS_SM 1213 /* this applies to ID data and all other SATA IOs */ 1214 #define SM_RETRIES 10 1215 #endif 1216 1217 #define TI_TIROOT_TO_tdsaRoot(t_r) (((tdsaRoot_t *)((tiRoot_t *)t_r)->tdData) ) 1218 1219 #define TI_TIROOT_TO_tdsaAllShared(t_r1) (tdsaContext_t *)&(t_r1->tdsaAllShared) 1220 1221 #define TI_TIROOT_TO_agroot(t_r2) (agsaRoot_t *)&((t_r2)->agRootNonInt) 1222 1223 1224 #define TI_TIROOT_TO_AGROOT(t_root) (TI_TIROOT_TO_agroot(TI_TIROOT_TO_tdsaAllShared(TI_TIROOT_TO_tdsaRoot(t_root)) )) 1225 1226 #define TI_VEN_DEV_SPC 0x80010000 1227 #define TI_VEN_DEV_SPCADAP 0x80810000 1228 #define TI_VEN_DEV_SPCv 0x80080000 1229 #define TI_VEN_DEV_SPCve 0x80090000 1230 #define TI_VEN_DEV_SPCvplus 0x80180000 1231 #define TI_VEN_DEV_SPCveplus 0x80190000 1232 #define TI_VEN_DEV_SPCADAPvplus 0x80880000 1233 #define TI_VEN_DEV_SPCADAPveplus 0x80890000 1234 1235 #define TI_VEN_DEV_SPC12Gv 0x80700000 1236 #define TI_VEN_DEV_SPC12Gve 0x80710000 1237 #define TI_VEN_DEV_SPC12Gvplus 0x80720000 1238 #define TI_VEN_DEV_SPC12Gveplus 0x80730000 1239 #define TI_VEN_DEV_9015 0x90150000 1240 #define TI_VEN_DEV_SPC12ADP 0x80740000 /* 8 ports KBP added*/ 1241 #define TI_VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */ 1242 #define TI_VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */ 1243 #define TI_VEN_DEV_9060 0x90600000 1244 1245 #define tIsSPC(agr) (TI_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ 1246 #define tIsSPCHIL(agr) (TI_VEN_DEV_SPCADAP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ 1247 #define tIsSPCv(agr) (TI_VEN_DEV_SPCv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 1248 #define tIsSPCve(agr) (TI_VEN_DEV_SPCve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve */ 1249 #define tIsSPCvplus(agr) (TI_VEN_DEV_SPCvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ 1250 #define tIsSPCveplus(agr) (TI_VEN_DEV_SPCveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ 1251 #define tIsSPCADAPvplus(agr) (TI_VEN_DEV_SPCADAPvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ 1252 #define tIsSPCADAPveplus(agr) (TI_VEN_DEV_SPCADAPveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ 1253 1254 #define tIsSPC12Gv(agr) (TI_VEN_DEV_SPC12Gv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv */ 1255 #define tIsSPC12Gve(agr) (TI_VEN_DEV_SPC12Gve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve */ 1256 #define tIsSPC12Gvplus(agr) (TI_VEN_DEV_SPC12Gvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv+ */ 1257 #define tIsSPC12Gveplus(agr) (TI_VEN_DEV_SPC12Gveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ 1258 #define tIsSPC9015(agr) (TI_VEN_DEV_9015 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ 1259 #define tIsSPC9060(agr) (TI_VEN_DEV_9060 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */ 1260 #define tIsSPC12ADP(agr) (TI_VEN_DEV_SPC12ADP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) 1261 #define tIsSPC12ADPP(agr) (TI_VEN_DEV_SPC12ADPP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) 1262 #define tIsSPC12SATA(agr) (TI_VEN_DEV_SPC12SATA == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) 1263 1264 #define tiIS_SPC(agr) (( tIsSPC((agr)) == 1) ? 1 : \ 1265 ( tIsSPCHIL((agr)) == 1) ? 1 : 0 ) 1266 1267 #define tiIS_HIL(agr) ((tIsSPCHIL ((agr)) == 1) ? 1 : \ 1268 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ 1269 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) 1270 1271 #define tiIS_SPC6V(agr) ((tIsSPCv((agr)) == 1) ? 1 : \ 1272 (tIsSPCve((agr)) == 1) ? 1 : \ 1273 (tIsSPCvplus((agr)) == 1) ? 1 : \ 1274 (tIsSPCveplus((agr)) == 1) ? 1 : \ 1275 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ 1276 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) 1277 1278 #define tIsSPCV12G(agr) ((tIsSPC12Gv(agr) == 1) ? 1 : \ 1279 (tIsSPC12Gve(agr) == 1) ? 1 : \ 1280 (tIsSPC12Gvplus(agr)== 1) ? 1 : \ 1281 (tIsSPC12Gveplus(agr)== 1) ? 1 : \ 1282 (tIsSPC9015(agr)== 1) ? 1 : \ 1283 (tIsSPC12ADP(agr)== 1) ? 1 : \ 1284 (tIsSPC12ADPP(agr)== 1) ? 1 : \ 1285 (tIsSPC12SATA(agr) == 1) ? 1 : \ 1286 (tIsSPC9060(agr) == 1) ? 1 : 0) 1287 1288 #define tiIS_8PHY(agr) ((tIsSPCv((agr)) == 1) ? 1 : \ 1289 (tIsSPCve((agr)) == 1) ? 1 : \ 1290 (tIsSPC12Gv((agr)) == 1) ? 1 : \ 1291 (tIsSPC12Gve((agr)) == 1) ? 1 : \ 1292 (tIsSPC12ADP(agr) == 1) ? 1 : 0 ) 1293 1294 #define tiIS_16PHY(agr) ((tIsSPCvplus((agr)) == 1) ? 1 : \ 1295 (tIsSPCveplus((agr)) == 1) ? 1 : \ 1296 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \ 1297 (tIsSPCADAPveplus((agr)) == 1) ? 1 : \ 1298 (tIsSPC12ADPP(agr) == 1) ? 1 : \ 1299 (tIsSPC12SATA(agr) == 1) ? 1 : 0 ) 1300 1301 #define tiIS_SPC_ENC(agr)((tIsSPCve((agr)) == 1) ? 1 : \ 1302 (tIsSPCveplus((agr)) == 1) ? 1 : \ 1303 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 ) 1304 1305 #define tIsSPCV12or6G(agr) ((tiIS_SPC6V(agr) == 1) ? 1 : \ 1306 (tIsSPCV12G(agr) == 1) ? 1 : 0) 1307 1308 #endif /* __TDDEFS_H__ */ 1309