1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * $FreeBSD$ 22 * 23 ********************************************************************************/ 24 #ifndef __SMDEFS_H__ 25 #define __SMDEFS_H__ 26 27 #include <dev/pms/RefTisa/tisa/sassata/common/ossa.h> 28 29 /* the index for memory requirement, must be continious */ 30 #define SM_ROOT_MEM_INDEX 0 /**< the index of dm root memory */ 31 #define SM_DEVICE_MEM_INDEX 1 /**< the index of Device descriptors memory */ 32 #define SM_IO_MEM_INDEX 2 /**< the index of IO command descriptors memory */ 33 34 35 #define SM_MAX_DEV 256 36 #define SM_MAX_IO 1024 37 38 #define SM_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 10ms */ 39 40 enum sm_locks_e 41 { 42 SM_TIMER_LOCK = 0, 43 SM_DEVICE_LOCK, 44 SM_INTERNAL_IO_LOCK, 45 SM_EXTERNAL_IO_LOCK, 46 SM_NCQ_TAG_LOCK, 47 SM_TBD_LOCK, 48 SM_MAX_LOCKS 49 }; 50 51 /* ATA device type */ 52 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */ 53 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */ 54 #define SATA_PM_DEVICE 0x03 /**< ATA PM device type */ 55 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */ 56 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */ 57 #define UNKNOWN_DEVICE 0xFF 58 59 /* 60 * FIS type 61 */ 62 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F 63 #define REG_DEV_TO_HOST_FIS 0x34 64 #define SET_DEV_BITS_FIS 0xA1 65 66 /* 67 * ATA Command code 68 */ 69 #define SAT_READ_FPDMA_QUEUED 0x60 70 #define SAT_READ_DMA_EXT 0x25 71 #define SAT_READ_DMA 0xC8 72 #define SAT_WRITE_FPDMA_QUEUED 0x61 73 #define SAT_WRITE_DMA_EXT 0x35 74 #define SAT_WRITE_DMA_FUA_EXT 0x3D 75 #define SAT_WRITE_DMA 0xCA 76 #define SAT_CHECK_POWER_MODE 0xE5 77 #define SAT_READ_LOG_EXT 0x2F 78 #define SAT_READ_VERIFY_SECTORS 0x40 79 #define SAT_READ_VERIFY_SECTORS_EXT 0x42 80 #define SAT_SMART 0xB0 81 #define SAT_SMART_EXEUTE_OFF_LINE_IMMEDIATE 0xD4 82 #define SAT_SMART_RETURN_STATUS 0xDA 83 #define SAT_SMART_READ_LOG 0xD5 84 #define SAT_SMART_ENABLE_OPERATIONS 0xD8 85 #define SAT_SMART_DISABLE_OPERATIONS 0xD9 86 #define SAT_FLUSH_CACHE 0xE7 87 #define SAT_FLUSH_CACHE_EXT 0xEA 88 #define SAT_STANDBY 0xE2 89 #define SAT_MEDIA_EJECT 0xED 90 #define SAT_WRITE_SECTORS 0x30 91 #define SAT_WRITE_SECTORS_EXT 0x34 92 #define SAT_READ_SECTORS 0x20 93 #define SAT_READ_SECTORS_EXT 0x24 94 #define SAT_GET_MEDIA_STATUS 0xDA 95 #define SAT_SET_FEATURES 0xEF 96 #define SAT_IDENTIFY_DEVICE 0xEC 97 #define SAT_READ_BUFFER 0xE4 98 #define SAT_WRITE_BUFFER 0xE8 99 100 /* 101 * ATAPI Command code 102 */ 103 #define SAT_IDENTIFY_PACKET_DEVICE 0xA1 104 #define SAT_PACKET 0xA0 105 #define SAT_DEVICE_RESET 0x08 106 #define SAT_EXECUTE_DEVICE_DIAGNOSTIC 0x90 107 108 109 /* 110 * ATA Status Register Mask 111 */ 112 #define ERR_ATA_STATUS_MASK 0x01 /* Error/check bit */ 113 #define DRQ_ATA_STATUS_MASK 0x08 /* Data Request bit */ 114 #define DF_ATA_STATUS_MASK 0x20 /* Device Fault bit */ 115 #define DRDY_ATA_STATUS_MASK 0x40 /* Device Ready bit */ 116 #define BSY_ATA_STATUS_MASK 0x80 /* Busy bit */ 117 118 /* 119 * ATA Error Register Mask 120 */ 121 #define NM_ATA_ERROR_MASK 0x02 /* No media present bit */ 122 #define ABRT_ATA_ERROR_MASK 0x04 /* Command aborted bit */ 123 #define MCR_ATA_ERROR_MASK 0x08 /* Media change request bit */ 124 #define IDNF_ATA_ERROR_MASK 0x10 /* Address not found bit */ 125 #define MC_ATA_ERROR_MASK 0x20 /* Media has changed bit */ 126 #define UNC_ATA_ERROR_MASK 0x40 /* Uncorrectable data error bit */ 127 #define ICRC_ATA_ERROR_MASK 0x80 /* Interface CRC error bit */ 128 129 130 131 132 /* 133 * transfer length and LBA limit 2^28 See identify device data word 61:60 134 * ATA spec p125 135 * 7 zeros 136 */ 137 #define SAT_TR_LBA_LIMIT 0x10000000 138 139 /* 140 * transfer length and LBA limit 2^48 See identify device data word 61:60 141 * ATA spec p125 142 * 12 zeros 143 */ 144 #define SAT_EXT_TR_LBA_LIMIT 0x1000000000000 145 146 147 /* 148 * ATA command type. This is for setting LBA, Sector Count 149 */ 150 #define SAT_NON_EXT_TYPE 0 151 #define SAT_EXT_TYPE 1 152 #define SAT_FP_TYPE 2 153 154 155 /* 156 * Report LUNs response data. 157 */ 158 typedef struct smScsiReportLun_s 159 { 160 bit8 len[4]; 161 bit32 reserved; 162 tiLUN_t lunList[1]; 163 } smScsiReportLun_t; 164 165 /* Inquiry vendor string */ 166 #define AG_SAT_VENDOR_ID_STRING "ATA " 167 168 /* 169 * Simple form of SATA Identify Device Data, similar definition is defined by 170 * LL Layer as agsaSATAIdentifyData_t. 171 */ 172 typedef struct satSimpleSATAIdentifyData_s 173 { 174 bit16 word[256]; 175 } satSimpleSATAIdentifyData_t; 176 177 178 /* 179 * READ LOG EXT page 10h 180 */ 181 typedef struct satReadLogExtPage10h_s 182 { 183 bit8 byte[512]; 184 } satReadLogExtPage10h_t; 185 186 /* 187 * READ LOG EXT Extended Self-test log 188 * ATA Table27 p196 189 */ 190 typedef struct satReadLogExtSelfTest_s 191 { 192 bit8 byte[512]; 193 } satReadLogExtSelfTest_t; 194 195 /* 196 * SMART READ LOG Self-test log 197 * ATA Table60 p296 198 */ 199 typedef struct satSmartReadLogSelfTest_s 200 { 201 bit8 byte[512]; 202 } satSmartReadLogSelfTest_t; 203 204 205 /* 206 * Flag definition for satIntFlag field in smSatInternalIo_t. 207 */ 208 209 /* Original NCQ I/O already completed, so at the completion of READ LOG EXT 210 * page 10h, ignore the TAG tranaltion to get the failed I/O 211 */ 212 #define AG_SAT_INT_IO_FLAG_ORG_IO_COMPLETED 0x00000001 213 214 #define INQUIRY_SUPPORTED_VPD_PAGE 0x00 215 #define INQUIRY_UNIT_SERIAL_NUMBER_VPD_PAGE 0x80 216 #define INQUIRY_DEVICE_IDENTIFICATION_VPD_PAGE 0x83 217 #define INQUIRY_ATA_INFORMATION_VPD_PAGE 0x89 218 #define INQUIRY_BLOCK_DEVICE_CHARACTERISTICS_VPD_PAGE 0xB1 219 220 #define MODESENSE_CONTROL_PAGE 0x0A 221 #define MODESENSE_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 222 #define MODESENSE_CACHING 0x08 223 #define MODESENSE_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C 224 #define MODESENSE_RETURN_ALL_PAGES 0x3F 225 #define MODESENSE_VENDOR_SPECIFIC_PAGE 0x00 226 227 #define MODESELECT_CONTROL_PAGE 0x0A 228 #define MODESELECT_READ_WRITE_ERROR_RECOVERY_PAGE 0x01 229 #define MODESELECT_CACHING 0x08 230 #define MODESELECT_INFORMATION_EXCEPTION_CONTROL_PAGE 0x1C 231 #define MODESELECT_RETURN_ALL_PAGES 0x3F 232 #define MODESELECT_VENDOR_SPECIFIC_PAGE 0x00 233 234 #define LOGSENSE_SUPPORTED_LOG_PAGES 0x00 235 #define LOGSENSE_SELFTEST_RESULTS_PAGE 0x10 236 #define LOGSENSE_INFORMATION_EXCEPTIONS_PAGE 0x2F 237 238 239 /* 240 * Bit mask definition 241 */ 242 #define SCSI_EVPD_MASK 0x01 243 #define SCSI_IMMED_MASK 0x01 244 #define SCSI_NACA_MASK 0x04 245 #define SCSI_LINK_MASK 0x01 246 #define SCSI_PF_MASK 0x10 247 #define SCSI_DEVOFFL_MASK 0x02 248 #define SCSI_UNITOFFL_MASK 0x01 249 #define SCSI_START_MASK 0x01 250 #define SCSI_LOEJ_MASK 0x02 251 #define SCSI_NM_MASK 0x02 252 #define SCSI_FLUSH_CACHE_IMMED_MASK 0x02 253 #define SCSI_FUA_NV_MASK 0x02 254 #define SCSI_VERIFY_BYTCHK_MASK 0x02 255 #define SCSI_FORMAT_UNIT_IMMED_MASK 0x02 256 #define SCSI_FORMAT_UNIT_FOV_MASK 0x80 257 #define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 258 #define SCSI_FORMAT_UNIT_IP_MASK 0x08 259 #define SCSI_WRITE_SAME_LBDATA_MASK 0x02 260 #define SCSI_WRITE_SAME_PBDATA_MASK 0x04 261 #define SCSI_SYNC_CACHE_IMMED_MASK 0x02 262 #define SCSI_WRITE_N_VERIFY_BYTCHK_MASK 0x02 263 #define SCSI_SEND_DIAGNOSTIC_SELFTEST_MASK 0x04 264 #define SCSI_FORMAT_UNIT_DEFECT_LIST_FORMAT_MASK 0x07 265 #define SCSI_FORMAT_UNIT_FMTDATA_MASK 0x10 266 #define SCSI_FORMAT_UNIT_DCRT_MASK 0x20 267 #define SCSI_FORMAT_UNIT_CMPLIST_MASK 0x08 268 #define SCSI_FORMAT_UNIT_LONGLIST_MASK 0x20 269 #define SCSI_READ10_FUA_MASK 0x08 270 #define SCSI_READ12_FUA_MASK 0x08 271 #define SCSI_READ16_FUA_MASK 0x08 272 #define SCSI_WRITE10_FUA_MASK 0x08 273 #define SCSI_WRITE12_FUA_MASK 0x08 274 #define SCSI_WRITE16_FUA_MASK 0x08 275 #define SCSI_READ_CAPACITY10_PMI_MASK 0x01 276 #define SCSI_READ_CAPACITY16_PMI_MASK 0x01 277 #define SCSI_MODE_SENSE6_PC_MASK 0xC0 278 #define SCSI_MODE_SENSE6_PAGE_CODE_MASK 0x3F 279 #define SCSI_MODE_SENSE10_PC_MASK 0xC0 280 #define SCSI_MODE_SENSE10_LLBAA_MASK 0x10 281 #define SCSI_MODE_SENSE10_PAGE_CODE_MASK 0x3F 282 #define SCSI_SEND_DIAGNOSTIC_TEST_CODE_MASK 0xE0 283 #define SCSI_LOG_SENSE_PAGE_CODE_MASK 0x3F 284 #define SCSI_MODE_SELECT6_PF_MASK 0x10 285 #define SCSI_MODE_SELECT6_AWRE_MASK 0x80 286 #define SCSI_MODE_SELECT6_RC_MASK 0x10 287 #define SCSI_MODE_SELECT6_EER_MASK 0x08 288 #define SCSI_MODE_SELECT6_PER_MASK 0x04 289 #define SCSI_MODE_SELECT6_DTE_MASK 0x02 290 #define SCSI_MODE_SELECT6_DCR_MASK 0x01 291 #define SCSI_MODE_SELECT6_WCE_MASK 0x04 292 #define SCSI_MODE_SELECT6_DRA_MASK 0x20 293 #define SCSI_MODE_SELECT6_PERF_MASK 0x80 294 #define SCSI_MODE_SELECT6_TEST_MASK 0x04 295 #define SCSI_MODE_SELECT6_DEXCPT_MASK 0x08 296 #define SCSI_MODE_SELECT10_PF_MASK 0x10 297 #define SCSI_MODE_SELECT10_LONGLBA_MASK 0x01 298 #define SCSI_MODE_SELECT10_AWRE_MASK 0x80 299 #define SCSI_MODE_SELECT10_RC_MASK 0x10 300 #define SCSI_MODE_SELECT10_EER_MASK 0x08 301 #define SCSI_MODE_SELECT10_PER_MASK 0x04 302 #define SCSI_MODE_SELECT10_DTE_MASK 0x02 303 #define SCSI_MODE_SELECT10_DCR_MASK 0x01 304 #define SCSI_MODE_SELECT10_WCE_MASK 0x04 305 #define SCSI_MODE_SELECT10_DRA_MASK 0x20 306 #define SCSI_MODE_SELECT10_PERF_MASK 0x80 307 #define SCSI_MODE_SELECT10_TEST_MASK 0x04 308 #define SCSI_MODE_SELECT10_DEXCPT_MASK 0x08 309 #define SCSI_WRITE_N_VERIFY10_FUA_MASK 0x08 310 #define SCSI_REQUEST_SENSE_DESC_MASK 0x01 311 #define SCSI_READ_BUFFER_MODE_MASK 0x1F 312 313 #define ATA_REMOVABLE_MEDIA_DEVICE_MASK 0x80 314 #define SCSI_REASSIGN_BLOCKS_LONGLIST_MASK 0x01 315 #define SCSI_REASSIGN_BLOCKS_LONGLBA_MASK 0x02 316 317 318 #define SENSE_DATA_LENGTH 0x12 /* 18 */ 319 #define SELFTEST_RESULTS_LOG_PAGE_LENGTH 404 320 #define INFORMATION_EXCEPTIONS_LOG_PAGE_LENGTH 11 321 #define ZERO_MEDIA_SERIAL_NUMBER_LENGTH 8 322 323 #define LOG_SENSE_0 0 324 #define LOG_SENSE_1 1 325 #define LOG_SENSE_2 2 326 327 #define READ_BUFFER_DATA_MODE 0x02 328 #define READ_BUFFER_DESCRIPTOR_MODE 0x03 329 #define READ_BUFFER_DESCRIPTOR_MODE_DATA_LEN 0x04 330 331 #define WRITE_BUFFER_DATA_MODE 0x02 332 #define WRITE_BUFFER_DL_MICROCODE_SAVE_MODE 0x05 333 334 /* bit mask */ 335 #define BIT0_MASK 0x01 336 #define BIT1_MASK 0x02 337 #define BIT2_MASK 0x04 338 #define BIT3_MASK 0x08 339 #define BIT4_MASK 0x10 340 #define BIT5_MASK 0x20 341 #define BIT6_MASK 0x40 342 #define BIT7_MASK 0x80 343 344 #define MODE_SENSE6_RETURN_ALL_PAGES_LEN 68 345 #define MODE_SENSE6_CONTROL_PAGE_LEN 24 346 #define MODE_SENSE6_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 347 #define MODE_SENSE6_CACHING_LEN 32 348 #define MODE_SENSE6_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 349 350 351 #define MODE_SENSE10_RETURN_ALL_PAGES_LEN 68 + 4 352 #define MODE_SENSE10_CONTROL_PAGE_LEN 24 + 4 353 #define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LEN 24 + 4 354 #define MODE_SENSE10_CACHING_LEN 32 + 4 355 #define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LEN 24 + 4 356 357 #define MODE_SENSE10_RETURN_ALL_PAGES_LLBAA_LEN 68 + 4 + 8 358 #define MODE_SENSE10_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 359 #define MODE_SENSE10_READ_WRITE_ERROR_RECOVERY_PAGE_LLBAA_LEN 24 + 4 + 8 360 #define MODE_SENSE10_CACHING_LLBAA_LEN 32 + 4 + 8 361 #define MODE_SENSE10_INFORMATION_EXCEPTION_CONTROL_PAGE_LLBAA_LEN 24 + 4 + 8 362 363 /***************************************************************************** 364 ** SCSI SENSE KEY VALUES 365 *****************************************************************************/ 366 367 #define SCSI_SNSKEY_NO_SENSE 0x00 368 #define SCSI_SNSKEY_RECOVERED_ERROR 0x01 369 #define SCSI_SNSKEY_NOT_READY 0x02 370 #define SCSI_SNSKEY_MEDIUM_ERROR 0x03 371 #define SCSI_SNSKEY_HARDWARE_ERROR 0x04 372 #define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05 373 #define SCSI_SNSKEY_UNIT_ATTENTION 0x06 374 #define SCSI_SNSKEY_DATA_PROTECT 0x07 375 #define SCSI_SNSKEY_ABORTED_COMMAND 0x0B 376 #define SCSI_SNSKEY_MISCOMPARE 0x0E 377 378 /***************************************************************************** 379 ** SCSI Additional Sense Codes and Qualifiers combo two-bytes 380 *****************************************************************************/ 381 382 #define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000 383 #define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803 384 #define SCSI_SNSCODE_INVALID_COMMAND 0x2000 385 #define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100 386 #define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400 387 #define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500 388 #define SCSI_SNSCODE_POWERON_RESET 0x2900 389 #define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00 390 #define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400 391 #define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00 392 #define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100 393 #define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401 394 #define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800 395 #define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01 396 #define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703 397 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404 398 #define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10 399 #define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00 400 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402 401 #define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600 402 #define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471 403 #define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B 404 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03 405 #define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00 406 #define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100 407 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01 408 #define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300 409 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402 410 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400 411 #define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500 412 #define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000 413 #define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00 414 #define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02 415 #define SCSI_SNSCODE_ATA_PASS_THROUGH_INFORMATION_AVAILABLE 0x001D 416 417 /***************************************************************************** 418 ** SCSI Additional Sense Codes and Qualifiers saparate bytes 419 *****************************************************************************/ 420 421 #define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04 422 #define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02 423 424 425 /***************************************************************************** 426 ** Inquiry command fields and response sizes 427 *****************************************************************************/ 428 #define SCSIOP_INQUIRY_CMDDT 0x02 429 #define SCSIOP_INQUIRY_EVPD 0x01 430 #define STANDARD_INQUIRY_SIZE 36 431 #define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */ 432 #define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */ 433 #define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */ 434 #define SATA_PAGE0_INQUIRY_SIZE 9 /* SPC-4, 7.6.9 Table331, p345 */ 435 #define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */ 436 #define SATA_PAGEB1_INQUIRY_SIZE 64 /* SBC-3, revision31, Table193, p273 */ 437 438 /***************************************************************************** 439 ** SCSI Operation Codes (first byte in CDB) 440 *****************************************************************************/ 441 442 443 #define SCSIOPC_TEST_UNIT_READY 0x00 444 #define SCSIOPC_INQUIRY 0x12 445 #define SCSIOPC_MODE_SENSE_6 0x1A 446 #define SCSIOPC_MODE_SENSE_10 0x5A 447 #define SCSIOPC_MODE_SELECT_6 0x15 448 #define SCSIOPC_START_STOP_UNIT 0x1B 449 #define SCSIOPC_READ_CAPACITY_10 0x25 450 #define SCSIOPC_READ_CAPACITY_16 0x9E 451 #define SCSIOPC_READ_6 0x08 452 #define SCSIOPC_READ_10 0x28 453 #define SCSIOPC_READ_12 0xA8 454 #define SCSIOPC_READ_16 0x88 455 #define SCSIOPC_WRITE_6 0x0A 456 #define SCSIOPC_WRITE_10 0x2A 457 #define SCSIOPC_WRITE_12 0xAA 458 #define SCSIOPC_WRITE_16 0x8A 459 #define SCSIOPC_WRITE_VERIFY 0x2E 460 #define SCSIOPC_VERIFY_10 0x2F 461 #define SCSIOPC_VERIFY_12 0xAF 462 #define SCSIOPC_VERIFY_16 0x8F 463 #define SCSIOPC_REQUEST_SENSE 0x03 464 #define SCSIOPC_REPORT_LUN 0xA0 465 #define SCSIOPC_FORMAT_UNIT 0x04 466 #define SCSIOPC_SEND_DIAGNOSTIC 0x1D 467 #define SCSIOPC_WRITE_SAME_10 0x41 468 #define SCSIOPC_WRITE_SAME_16 0x93 469 #define SCSIOPC_READ_BUFFER 0x3C 470 #define SCSIOPC_WRITE_BUFFER 0x3B 471 472 #define SCSIOPC_LOG_SENSE 0x4D 473 #define SCSIOPC_LOG_SELECT 0x4C 474 #define SCSIOPC_MODE_SELECT_6 0x15 475 #define SCSIOPC_MODE_SELECT_10 0x55 476 #define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35 477 #define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91 478 #define SCSIOPC_WRITE_AND_VERIFY_10 0x2E 479 #define SCSIOPC_WRITE_AND_VERIFY_12 0xAE 480 #define SCSIOPC_WRITE_AND_VERIFY_16 0x8E 481 #define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB 482 #define SCSIOPC_REASSIGN_BLOCKS 0x07 483 484 #define SCSIOPC_GET_CONFIG 0x46 485 #define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a 486 #define SCSIOPC_REPORT_KEY 0xA4 487 #define SCSIOPC_SEND_KEY 0xA3 488 #define SCSIOPC_READ_DVD_STRUCTURE 0xAD 489 #define SCSIOPC_TOC 0x43 490 #define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E 491 #define SCSIOPC_READ_VERIFY 0x42 492 #define SCSIOPC_ATA_PASS_THROUGH12 0xA1 493 #define SCSIOPC_ATA_PASS_THROUGH16 0x85 494 495 496 /*! \def MIN(a,b) 497 * \brief MIN macro 498 * 499 * use to find MIN of two values 500 */ 501 #ifndef MIN 502 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 503 #endif 504 505 /*! \def MAX(a,b) 506 * \brief MAX macro 507 * 508 * use to find MAX of two values 509 */ 510 #ifndef MAX 511 #define MAX(a,b) ((a) < (b) ? (b) : (a)) 512 #endif 513 514 /* for debugging print */ 515 #if defined(SM_DEBUG) 516 517 /* 518 * for debugging purposes. 519 */ 520 extern bit32 gSMDebugLevel; 521 522 #define SM_DBG0(format) tdsmLogDebugString(gSMDebugLevel, 0, format) 523 #define SM_DBG1(format) tdsmLogDebugString(gSMDebugLevel, 1, format) 524 #define SM_DBG2(format) tdsmLogDebugString(gSMDebugLevel, 2, format) 525 #define SM_DBG3(format) tdsmLogDebugString(gSMDebugLevel, 3, format) 526 #define SM_DBG4(format) tdsmLogDebugString(gSMDebugLevel, 4, format) 527 #define SM_DBG5(format) tdsmLogDebugString(gSMDebugLevel, 5, format) 528 #define SM_DBG6(format) tdsmLogDebugString(gSMDebugLevel, 6, format) 529 530 #else 531 532 #define SM_DBG0(format) 533 #define SM_DBG1(format) 534 #define SM_DBG2(format) 535 #define SM_DBG3(format) 536 #define SM_DBG4(format) 537 #define SM_DBG5(format) 538 #define SM_DBG6(format) 539 540 #endif /* SM_DEBUG */ 541 542 //#define SM_ASSERT OS_ASSERT 543 //#define tdsmLogDebugString TIDEBUG_MSG 544 545 /* 546 * SAT specific structure per SATA drive 547 */ 548 #define SAT_NONNCQ_MAX 1 549 #define SAT_NCQ_MAX 32 550 #define SAT_MAX_INT_IO 16 551 #define SAT_APAPI_CMDQ_MAX 2 552 553 /* Device state */ 554 #define SAT_DEV_STATE_NORMAL 0 /* Normal */ 555 #define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */ 556 #define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */ 557 #define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/ 558 #define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/ 559 560 #ifndef agNULL 561 #define agNULL ((void *)0) 562 #endif 563 564 #define SM_SET_ESGL_EXTEND(val) \ 565 ((val) = (val) | 0x80000000) 566 567 #define SM_CLEAR_ESGL_EXTEND(val) \ 568 ((val) = (val) & 0x7FFFFFFF) 569 570 #ifndef OPEN_RETRY_RETRIES 571 #define OPEN_RETRY_RETRIES 10 572 #endif 573 574 /********************************************************************* 575 * CPU buffer access macro * 576 * * 577 */ 578 579 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 580 (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 581 582 583 #if defined(SA_CPU_LITTLE_ENDIAN) 584 585 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 586 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 587 588 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 589 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 590 591 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 592 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 593 594 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 595 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 596 597 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 598 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 599 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 600 601 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 602 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 603 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 604 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 605 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 606 607 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 608 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 609 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 610 611 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 612 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 613 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 614 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 615 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 616 617 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 618 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 619 620 621 #elif defined(SA_CPU_BIG_ENDIAN) 622 623 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 624 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 625 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 626 627 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 628 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 629 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 630 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 631 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 632 633 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 634 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 635 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 636 637 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 638 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 639 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 640 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 641 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 642 643 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 644 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 645 646 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 647 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 648 649 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 650 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 651 652 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 653 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 654 655 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 656 si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 657 658 #else 659 660 #error (Host CPU endianess undefined!!) 661 662 #endif 663 664 665 #if defined(SA_CPU_LITTLE_ENDIAN) 666 667 #ifndef LEBIT16_TO_BIT16 668 #define LEBIT16_TO_BIT16(_x) (_x) 669 #endif 670 671 #ifndef BIT16_TO_LEBIT16 672 #define BIT16_TO_LEBIT16(_x) (_x) 673 #endif 674 675 #ifndef BIT16_TO_BEBIT16 676 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 677 #endif 678 679 #ifndef BEBIT16_TO_BIT16 680 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 681 #endif 682 683 #ifndef LEBIT32_TO_BIT32 684 #define LEBIT32_TO_BIT32(_x) (_x) 685 #endif 686 687 #ifndef BIT32_TO_LEBIT32 688 #define BIT32_TO_LEBIT32(_x) (_x) 689 #endif 690 691 692 #ifndef BEBIT32_TO_BIT32 693 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 694 #endif 695 696 #ifndef BIT32_TO_BEBIT32 697 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 698 #endif 699 700 #elif defined(SA_CPU_BIG_ENDIAN) 701 702 #ifndef LEBIT16_TO_BIT16 703 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 704 #endif 705 706 #ifndef BIT16_TO_LEBIT16 707 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 708 #endif 709 710 #ifndef BIT16_TO_BEBIT16 711 #define BIT16_TO_BEBIT16(_x) (_x) 712 #endif 713 714 #ifndef BEBIT16_TO_BIT16 715 #define BEBIT16_TO_BIT16(_x) (_x) 716 #endif 717 718 #ifndef LEBIT32_TO_BIT32 719 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 720 #endif 721 722 #ifndef BIT32_TO_LEBIT32 723 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 724 #endif 725 726 #ifndef BEBIT32_TO_BIT32 727 #define BEBIT32_TO_BIT32(_x) (_x) 728 #endif 729 730 #ifndef BIT32_TO_BEBIT32 731 #define BIT32_TO_BEBIT32(_x) (_x) 732 #endif 733 734 #else 735 736 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 737 738 #endif 739 740 741 /* 742 * Task Management task used in tiINITaskManagement() 743 * 744 * 1 SM_ABORT TASK - aborts the task identified by the Referenced Task Tag field. 745 * 2 SM_ABORT TASK SET - aborts all Tasks issued by this initiator on the Logical Unit 746 * 3 SM_CLEAR ACA - clears the Auto Contingent Allegiance condition. 747 * 4 SM_CLEAR TASK SET - Aborts all Tasks (from all initiators) for the Logical Unit. 748 * 5 SM_LOGICAL UNIT RESET 749 * 6 SM_TARGET WARM RESET - iSCSI only 750 * 7 SM_TARGET_COLD_RESET - iSCSI only 751 * 8 SM_TASK_REASSIGN - iSCSI only 752 * 9 SM_QUERY_TASK - SAS only 753 */ 754 755 #define SM_ABORT_TASK 1 756 #define SM_ABORT_TASK_SET 2 757 #define SM_CLEAR_ACA 3 758 #define SM_CLEAR_TASK_SET 4 759 #define SM_LOGICAL_UNIT_RESET 5 760 #define SM_TARGET_WARM_RESET 6 /* iSCSI only */ 761 #define SM_TARGET_COLD_RESET 7 /* iSCSI only */ 762 #define SM_TASK_REASSIGN 8 /* iSCSI only */ 763 #define SM_QUERY_TASK 9 /* SAS only */ 764 765 /* SMP PHY CONTROL OPERATION */ 766 #define SMP_PHY_CONTROL_NOP 0x00 767 #define SMP_PHY_CONTROL_LINK_RESET 0x01 768 #define SMP_PHY_CONTROL_HARD_RESET 0x02 769 #define SMP_PHY_CONTROL_DISABLE 0x03 770 #define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05 771 #define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06 772 #define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07 773 774 /**************************************************************** 775 * Phy Control request 776 ****************************************************************/ 777 typedef struct smpReqPhyControl_s 778 { 779 bit8 reserved1[4]; 780 bit8 reserved2; 781 bit8 phyIdentifier; 782 bit8 phyOperation; 783 bit8 updatePartialPathwayTOValue; 784 /* b7-1 : reserved */ 785 /* b0 : update partial pathway timeout value */ 786 bit8 reserved3[20]; 787 bit8 programmedMinPhysicalLinkRate; 788 /* b7-4 : programmed Minimum Physical Link Rate*/ 789 /* b3-0 : reserved */ 790 bit8 programmedMaxPhysicalLinkRate; 791 /* b7-4 : programmed Maximum Physical Link Rate*/ 792 /* b3-0 : reserved */ 793 bit8 reserved4[2]; 794 bit8 partialPathwayTOValue; 795 /* b7-4 : reserved */ 796 /* b3-0 : partial Pathway TO Value */ 797 bit8 reserved5[3]; 798 } smpReqPhyControl_t; 799 800 801 typedef struct smSMPFrameHeader_s 802 { 803 bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */ 804 bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */ 805 bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */ 806 bit8 smpReserved; /* reserved */ 807 } smSMPFrameHeader_t; 808 809 /* SMP direct payload size limit: IOMB direct payload size = 48 */ 810 #define SMP_DIRECT_PAYLOAD_LIMIT 44 811 812 #define SMP_REQUEST 0x40 813 #define SMP_RESPONSE 0x41 814 815 #define SMP_PHY_CONTROL 0x91 816 817 /* SMP function results */ 818 #define SMP_FUNCTION_ACCEPTED 0x00 819 820 /* bit8 array[4] -> bit32 */ 821 #define SM_GET_SAS_ADDRESSLO(sasAddressLo) \ 822 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo) 823 824 #define SM_GET_SAS_ADDRESSHI(sasAddressHi) \ 825 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi) 826 827 /* SATA sector size 512 bytes = 0x200 bytes */ 828 #define SATA_SECTOR_SIZE 0x200 829 /* TL limit in sector */ 830 /* for SAT_READ/WRITE_DMA and SAT_READ/WRITE_SECTORS ATA command */ 831 #define NON_BIT48_ADDRESS_TL_LIMIT 0x100 832 /* for SAT_READ/WRITE_DMA_EXT and SAT_READ/WRITE_SECTORS_EXT and SAT_READ/WRITE_FPDMA_QUEUEDATA command */ 833 #define BIT48_ADDRESS_TL_LIMIT 0xFFFF 834 835 #define VEN_DEV_SPC 0x800111f8 836 #define VEN_DEV_SPCv 0x800811f8 837 #define VEN_DEV_SPCve 0x800911f8 838 #define VEN_DEV_SPCvplus 0x801811f8 839 #define VEN_DEV_SPCveplus 0x801911f8 840 841 #define SMIsSPC(agr) (VEN_DEV_SPC == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPC */ 842 #define SMIsSPCv(agr) (VEN_DEV_SPCv == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv */ 843 #define SMIsSPCve(agr) (VEN_DEV_SPCve == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve */ 844 #define SMIsSPCvplus(agr) (VEN_DEV_SPCvplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv+ */ 845 #define SMIsSPCveplus(agr) (VEN_DEV_SPCveplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve+ */ 846 847 #define DEFAULT_KEY_BUFFER_SIZE 64 848 849 850 #endif /* __SMDEFS_H__ */ 851 852