1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 /*! \file sampidefs.h 25 * \brief The file defines the constants used by SAS/SATA LL layer 26 * 27 */ 28 29 /*******************************************************************************/ 30 31 #ifndef __SAMPIDEFS_H__ 32 33 #define __SAMPIDEFS_H__ 34 35 /* for Request Opcode of IOMB */ 36 #define OPC_INB_ECHO 0x001 /* */ 37 38 #define OPC_INB_PHYSTART 0x004 /* */ 39 #define OPC_INB_PHYSTOP 0x005 /* */ 40 #define OPC_INB_SSPINIIOSTART 0x006 /* */ 41 #define OPC_INB_SSPINITMSTART 0x007 /* */ 42 #define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */ 43 #define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */ 44 #define OPC_INB_SSPTGTIOSTART 0x00a /* */ 45 #define OPC_INB_SSPTGTRSPSTART 0x00b /* */ 46 #define OPC_INB_SSP_ABORT 0x00f /* */ 47 #define OPC_INB_DEREG_DEV_HANDLE 0x010 /* 16 */ 48 #define OPC_INB_GET_DEV_HANDLE 0x011 /* 17 */ 49 #define OPC_INB_SMP_REQUEST 0x012 /* 18 */ 50 51 #define OPC_INB_SMP_ABORT 0x014 /* 20 */ 52 53 #define OPC_INB_SPC_REG_DEV 0x016 /* 22 V reserved */ 54 #define OPC_INB_SATA_HOST_OPSTART 0x017 /* 23 */ 55 #define OPC_INB_SATA_ABORT 0x018 /* 24 */ 56 #define OPC_INB_LOCAL_PHY_CONTROL 0x019 /* 25 */ 57 #define OPC_INB_SPC_GET_DEV_INFO 0x01a /* 26 V reserved */ 58 59 #define OPC_INB_FW_FLASH_UPDATE 0x020 /* 32 */ 60 61 #define OPC_INB_GPIO 0x022 /* 34 */ 62 #define OPC_INB_SAS_DIAG_MODE_START_END 0x023 /* 35 */ 63 #define OPC_INB_SAS_DIAG_EXECUTE 0x024 /* 36 */ 64 #define OPC_INB_SPC_SAS_HW_EVENT_ACK 0x025 /* 37 V reserved */ 65 #define OPC_INB_GET_TIME_STAMP 0x026 /* 38 */ 66 #define OPC_INB_PORT_CONTROL 0x027 /* 39 */ 67 #define OPC_INB_GET_NVMD_DATA 0x028 /* 40 */ 68 #define OPC_INB_SET_NVMD_DATA 0x029 /* 41 */ 69 #define OPC_INB_SET_DEVICE_STATE 0x02a /* 42 */ 70 #define OPC_INB_GET_DEVICE_STATE 0x02b /* 43 */ 71 #define OPC_INB_SET_DEV_INFO 0x02c /* 44 */ 72 #define OPC_INB_SAS_RE_INITIALIZE 0x02d /* 45 V reserved */ 73 #define OPC_INB_SGPIO 0x02e /* 46 */ 74 #define OPC_INB_PCIE_DIAG_EXECUTE 0x02f /* 47 */ 75 76 #define OPC_INB_SET_CONTROLLER_CONFIG 0x030 /* 48 */ 77 #define OPC_INB_GET_CONTROLLER_CONFIG 0x031 /* 49 */ 78 79 #define OPC_INB_REG_DEV 0x032 /* 50 SPCV */ 80 #define OPC_INB_SAS_HW_EVENT_ACK 0x033 /* 51 SPCV */ 81 #define OPC_INB_GET_DEV_INFO 0x034 /* 52 SPCV */ 82 #define OPC_INB_GET_PHY_PROFILE 0x035 /* 53 SPCV */ 83 #define OPC_INB_FLASH_OP_EXT 0x036 /* 54 SPCV */ 84 #define OPC_INB_SET_PHY_PROFILE 0x037 /* 55 SPCV */ 85 #define OPC_INB_GET_DFE_DATA 0x038 /* 56 SPCV */ 86 #define OPC_INB_GET_VHIST_CAP 0x039 /* 57 SPCV12g */ 87 88 89 #define OPC_INB_KEK_MANAGEMENT 0x100 /* 256 SPCV */ 90 #define OPC_INB_DEK_MANAGEMENT 0x101 /* 257 SPCV */ 91 #define OPC_INB_SSP_DIF_ENC_OPSTART 0x102 /* 258 SPCV */ 92 #define OPC_INB_SATA_DIF_ENC_OPSTART 0x103 /* 259 SPCV */ 93 #define OPC_INB_OPR_MGMT 0x104 /* 260 SPCV */ 94 #define OPC_INB_ENC_TEST_EXECUTE 0x105 /* 261 SPCV */ 95 #define OPC_INB_SET_OPERATOR 0x106 /* 262 SPCV */ 96 #define OPC_INB_GET_OPERATOR 0x107 /* 263 SPCV */ 97 #define OPC_INB_DIF_ENC_OFFLOAD_CMD 0x110 /* 272 SPCV */ 98 99 #define OPC_INB_FW_PROFILE 0x888 /* 2184 SPCV */ 100 101 /* for Response Opcode of IOMB */ 102 #define OPC_OUB_ECHO 0x001 /* 1 */ 103 104 #define OPC_OUB_SPC_HW_EVENT 0x004 /* 4 V reserved Now OPC_OUB_HW_EVENT */ 105 #define OPC_OUB_SSP_COMP 0x005 /* 5 */ 106 #define OPC_OUB_SMP_COMP 0x006 /* 6 */ 107 #define OPC_OUB_LOCAL_PHY_CNTRL 0x007 /* 7 */ 108 109 #define OPC_OUB_SPC_DEV_REGIST 0x00a /* 10 V reserved Now OPC_OUB_DEV_REGIST */ 110 #define OPC_OUB_DEREG_DEV 0x00b /* 11 */ 111 #define OPC_OUB_GET_DEV_HANDLE 0x00c /* 12 */ 112 #define OPC_OUB_SATA_COMP 0x00d /* 13 */ 113 #define OPC_OUB_SATA_EVENT 0x00e /* 14 */ 114 #define OPC_OUB_SSP_EVENT 0x00f /* 15 */ 115 116 #define OPC_OUB_SPC_DEV_HANDLE_ARRIV 0x010 /* 16 V reserved Now OPC_OUB_DEV_HANDLE_ARRIV */ 117 118 #define OPC_OUB_SSP_RECV_EVENT 0x012 /* 18 */ 119 #define OPC_OUB_SPC_DEV_INFO 0x013 /* 19 V reserved Now OPC_OUB_DEV_INFO*/ 120 #define OPC_OUB_FW_FLASH_UPDATE 0x014 /* 20 */ 121 122 #define OPC_OUB_GPIO_RESPONSE 0x016 /* 22 */ 123 #define OPC_OUB_GPIO_EVENT 0x017 /* 23 */ 124 #define OPC_OUB_GENERAL_EVENT 0x018 /* 24 */ 125 126 #define OPC_OUB_SSP_ABORT_RSP 0x01a /* 26 */ 127 #define OPC_OUB_SATA_ABORT_RSP 0x01b /* 27 */ 128 #define OPC_OUB_SAS_DIAG_MODE_START_END 0x01c /* 28 */ 129 #define OPC_OUB_SAS_DIAG_EXECUTE 0x01d /* 29 */ 130 #define OPC_OUB_GET_TIME_STAMP 0x01e /* 30 */ 131 #define OPC_OUB_SPC_SAS_HW_EVENT_ACK 0x01f /* 31 V reserved Now OPC_OUB_SAS_HW_EVENT_ACK*/ 132 #define OPC_OUB_PORT_CONTROL 0x020 /* 32 */ 133 #define OPC_OUB_SKIP_ENTRY 0x021 /* 33 */ 134 #define OPC_OUB_SMP_ABORT_RSP 0x022 /* 34 */ 135 #define OPC_OUB_GET_NVMD_DATA 0x023 /* 35 */ 136 #define OPC_OUB_SET_NVMD_DATA 0x024 /* 36 */ 137 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 0x025 /* 37 */ 138 #define OPC_OUB_SET_DEVICE_STATE 0x026 /* 38 */ 139 #define OPC_OUB_GET_DEVICE_STATE 0x027 /* 39 */ 140 #define OPC_OUB_SET_DEV_INFO 0x028 /* 40 */ 141 #define OPC_OUB_SAS_RE_INITIALIZE 0x029 /* 41 V reserved not replaced */ 142 143 #define OPC_OUB_HW_EVENT 0x700 /* 1792 SPCV Was OPC_OUB_SPC_HW_EVENT*/ 144 #define OPC_OUB_DEV_HANDLE_ARRIV 0x720 /* 1824 SPCV Was OPC_OUB_SPC_DEV_HANDLE_ARRIV*/ 145 146 #define OPC_OUB_PHY_START_RESPONSE 0x804 /* 2052 SPCV */ 147 #define OPC_OUB_PHY_STOP_RESPONSE 0x805 /* 2053 SPCV */ 148 #define OPC_OUB_SGPIO_RESPONSE 0x82E /* 2094 SPCV */ 149 #define OPC_OUB_PCIE_DIAG_EXECUTE 0x82F /* 2095 SPCV */ 150 151 #define OPC_OUB_SET_CONTROLLER_CONFIG 0x830 /* 2096 SPCV */ 152 #define OPC_OUB_GET_CONTROLLER_CONFIG 0x831 /* 2097 SPCV */ 153 #define OPC_OUB_DEV_REGIST 0x832 /* 2098 SPCV */ 154 #define OPC_OUB_SAS_HW_EVENT_ACK 0x833 /* 2099 SPCV */ 155 #define OPC_OUB_DEV_INFO 0x834 /* 2100 SPCV */ 156 #define OPC_OUB_GET_PHY_PROFILE_RSP 0x835 /* 2101 SPCV */ 157 #define OPC_OUB_FLASH_OP_EXT_RSP 0x836 /* 2102 SPCV */ 158 #define OPC_OUB_SET_PHY_PROFILE_RSP 0x837 /* 2103 SPCV */ 159 #define OPC_OUB_GET_DFE_DATA_RSP 0x838 /* 2104 SPCV */ 160 #define OPC_OUB_GET_VIST_CAP_RSP 0x839 /* Can be 2104 for SPCV12g */ 161 162 #define OPC_OUB_FW_PROFILE 0x888 /* 2184 */ 163 164 #define OPC_OUB_KEK_MANAGEMENT 0x900 /* 2304 SPCV */ 165 #define OPC_OUB_DEK_MANAGEMENT 0x901 /* 2305 SPCV */ 166 #define OPC_OUB_COMBINED_SSP_COMP 0x902 /* 2306 SPCV */ 167 #define OPC_OUB_COMBINED_SATA_COMP 0x903 /* 2307 SPCV */ 168 #define OPC_OUB_OPR_MGMT 0x904 /* 2308 SPCV */ 169 #define OPC_OUB_ENC_TEST_EXECUTE 0x905 /* 2309 SPCV */ 170 #define OPC_OUB_SET_OPERATOR 0x906 /* 2310 SPCV */ 171 #define OPC_OUB_GET_OPERATOR 0x907 /* 2311 SPCV */ 172 #define OPC_OUB_DIF_ENC_OFFLOAD_RSP 0x910 /* 2320 SPCV */ 173 174 /* Definitions for encryption key management */ 175 #define KEK_MGMT_SUBOP_INVALIDATE 0x1 176 #define KEK_MGMT_SUBOP_UPDATE 0x2 177 #define KEK_MGMT_SUBOP_KEYCARDINVALIDATE 0x3 178 #define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4 179 180 #define DEK_MGMT_SUBOP_INVALIDATE 0x1 181 #define DEK_MGMT_SUBOP_UPDATE 0x2 182 183 /*************************************************** 184 * typedef for IOMB structure 185 ***************************************************/ 186 /** \brief the data structure of Echo Command 187 * 188 * use to describe MPI Echo Command (64 bytes) 189 * 190 */ 191 typedef struct agsaEchoCmd_s { 192 bit32 tag; 193 bit32 payload[14]; 194 } agsaEchoCmd_t; 195 196 /** \brief the data structure of PHY Start Command 197 * 198 * use to describe MPI PHY Start Command (64 bytes) 199 * 200 */ 201 typedef struct agsaPhyStartCmd_s { 202 bit32 tag; 203 bit32 SscdAseSHLmMlrPhyId; 204 agsaSASIdentify_t sasIdentify; 205 bit32 analogSetupIdx; 206 bit32 SAWT_DAWT; 207 bit32 reserved[5]; 208 } agsaPhyStartCmd_t; 209 210 #define SPINHOLD_DISABLE (0x00 << 14) 211 #define SPINHOLD_ENABLE (0x01 << 14) 212 #define LINKMODE_SAS (0x01 << 12) 213 #define LINKMODE_DSATA (0x02 << 12) 214 #define LINKMODE_AUTO (0x03 << 12) 215 #define LINKRATE_15 (0x01 << 8) 216 #define LINKRATE_30 (0x02 << 8) 217 #define LINKRATE_60 (0x04 << 8) 218 #define LINKRATE_12 (0x08 << 8) 219 220 /** \brief the data structure of PHY Stop Command 221 * 222 * use to describe MPI PHY Start Command (64 bytes) 223 * 224 */ 225 typedef struct agsaPhyStopCmd_s { 226 bit32 tag; 227 bit32 phyId; 228 bit32 reserved[13]; 229 } agsaPhyStopCmd_t; 230 231 /** \brief the data structure of SSP INI IO Start Command 232 * 233 * use to describe MPI SSP INI IO Start Command (64 bytes) 234 * 235 */ 236 typedef struct agsaSSPIniIOStartCmd_s { 237 bit32 tag; 238 bit32 deviceId; 239 bit32 dataLen; 240 bit32 dirMTlr; 241 agsaSSPCmdInfoUnit_t SSPInfoUnit; 242 bit32 AddrLow0; 243 bit32 AddrHi0; 244 bit32 Len0; 245 bit32 E0; 246 } agsaSSPIniIOStartCmd_t; 247 248 /** \brief the data structure of SSP INI TM Start Command 249 * 250 * use to describe MPI SSP INI TM Start Command (64 bytes) 251 * 252 */ 253 typedef struct agsaSSPIniTMStartCmd_s { 254 bit32 tag; 255 bit32 deviceId; 256 bit32 relatedTag; 257 bit32 TMfunction; 258 bit8 lun[8]; 259 bit32 dsAdsMReport; 260 bit32 reserved[8]; 261 } agsaSSPIniTMStartCmd_t; 262 263 /** \brief the data structure of SSP INI Extended IO Start Command 264 * 265 * use to describe MPI SSP INI Extended CDB Start Command (96 bytes to support 32 CDB) 266 * 267 */ 268 typedef struct agsaSSPIniExtIOStartCmd_s { 269 bit32 tag; 270 bit32 deviceId; 271 bit32 dataLen; 272 bit32 SSPIuLendirMTlr; 273 bit8 SSPIu[1]; 274 /* variable lengh */ 275 /* bit32 AddrLow0; */ 276 /* bit32 AddrHi0; */ 277 /* bit32 Len0; */ 278 /* bit32 E0; */ 279 } agsaSSPIniExtIOStartCmd_t; 280 281 typedef struct agsaSSPIniEncryptIOStartCmd_s 282 { 283 bit32 tag; /* 1 */ 284 bit32 deviceId; /* 2 */ 285 bit32 dataLen; /* 3 */ 286 bit32 dirMTlr; /* 4 */ 287 bit32 sspiu_0_3_indcdbalL; /* 5 */ 288 bit32 sspiu_4_7_indcdbalH; /* 6 */ 289 bit32 sspiu_8_11; /* 7 */ 290 bit32 sspiu_12_15; /* 8 */ 291 bit32 sspiu_16_19; /* 9 */ 292 bit32 sspiu_19_23; /* 10 */ 293 bit32 sspiu_24_27; /* 11 */ 294 bit32 epl_descL; /* 12 */ 295 bit32 dpl_descL; /* 13 */ 296 bit32 edpl_descH; /* 14 */ 297 bit32 DIF_flags; /* 15 */ 298 bit32 udt; /* 16 0x10 */ 299 bit32 udtReplacementLo; /* 17 */ 300 bit32 udtReplacementHi; /* 18 */ 301 bit32 DIF_seed; /* 19 */ 302 bit32 encryptFlagsLo; /* 20 0x14 */ 303 bit32 encryptFlagsHi; /* 21 */ 304 bit32 keyTag_W0; /* 22 */ 305 bit32 keyTag_W1; /* 23 */ 306 bit32 tweakVal_W0; /* 24 0x18 */ 307 bit32 tweakVal_W1; /* 25 */ 308 bit32 tweakVal_W2; /* 26 */ 309 bit32 tweakVal_W3; /* 27 */ 310 bit32 AddrLow0; /* 28 0x1C */ 311 bit32 AddrHi0; /* 29 */ 312 bit32 Len0; /* 30 */ 313 bit32 E0; /* 31 */ 314 } agsaSSPIniEncryptIOStartCmd_t; 315 316 /** \brief the data structure of SSP Abort Command 317 * 318 * use to describe MPI SSP Abort Command (64 bytes) 319 * 320 */ 321 typedef struct agsaSSPAbortCmd_s { 322 bit32 tag; 323 bit32 deviceId; 324 bit32 HTagAbort; 325 bit32 abortAll; 326 bit32 reserved[11]; 327 } agsaSSPAbortCmd_t; 328 329 /** \brief the data structure of Register Device Command 330 * 331 * use to describe MPI DEVICE REGISTER Command (64 bytes) 332 * 333 */ 334 typedef struct agsaRegDevCmd_s { 335 bit32 tag; 336 bit32 phyIdportId; 337 bit32 dTypeLRateAwtHa; 338 bit32 ITNexusTimeOut; 339 bit32 sasAddrHi; 340 bit32 sasAddrLo; 341 bit32 DeviceId; 342 bit32 reserved[8]; 343 } agsaRegDevCmd_t; 344 345 /** \brief the data structure of Deregister Device Handle Command 346 * 347 * use to describe MPI DEREGISTER DEVIDE HANDLE Command (64 bytes) 348 * 349 */ 350 typedef struct agsaDeregDevHandleCmd_s { 351 bit32 tag; 352 bit32 deviceId; 353 bit32 portId; 354 bit32 reserved[12]; 355 } agsaDeregDevHandleCmd_t; 356 357 /** \brief the data structure of Get Device Handle Command 358 * 359 * use to describe MPI GET DEVIDE HANDLE Command (64 bytes) 360 * 361 */ 362 typedef struct agsaGetDevHandleCmd_s { 363 bit32 tag; 364 bit32 DevADevTMaxDIDportId; 365 bit32 skipCount; 366 bit32 reserved[12]; 367 } agsaGetDevHandleCmd_t; 368 369 /** \brief the data structure of SMP Request Command 370 * 371 * use to describe MPI SMP REQUEST Command (64 bytes) 372 * 373 */ 374 375 typedef struct agsaSMPCmd_s { 376 bit32 tag; 377 bit32 deviceId; 378 bit32 IR_IP_OV_res_phyId_DPdLen_res; 379 /* Bits [0] - IR */ 380 /* Bits [1] - IP */ 381 /* Bits [15:2] - Reserved */ 382 /* Bits [23:16] - Len */ 383 /* Bits [31:24] - Reserved */ 384 bit32 SMPCmd[12]; 385 } agsaSMPCmd_t; 386 387 388 typedef struct agsaSMPCmd_V_s { 389 bit32 tag; /* 1 */ 390 bit32 deviceId; /* 2 */ 391 bit32 IR_IP_OV_res_phyId_DPdLen_res;/* 3 */ 392 /* Bits [0] - IR */ 393 /* Bits [1] - IP */ 394 /* Bits [15:2] - Reserved */ 395 /* Bits [23:16] - Len */ 396 /* Bits [31:24] - Reserved */ 397 bit32 SMPHDR; /* 4 */ 398 bit32 SMP3_0; /* 5 */ 399 bit32 SMP7_4; /* 6 */ 400 bit32 SMP11_8; /* 7 */ 401 bit32 IndirL_SMPRF15_12; /* 8 */ 402 bit32 IndirH_or_SMPRF19_16; /* 9 */ 403 bit32 IndirLen_or_SMPRF23_20; /* 10 */ 404 bit32 R_or_SMPRF27_24; /* 11 */ 405 bit32 ISRAL_or_SMPRF31_28; /* 12 */ 406 bit32 ISRAH_or_SMPRF35_32; /* 13 */ 407 bit32 ISRL_or_SMPRF39_36; /* 14 */ 408 bit32 R_or_SMPRF43_40; /* 15 */ 409 } agsaSMPCmd_V_t; 410 411 /** \brief the data structure of SMP Abort Command 412 * 413 * use to describe MPI SMP Abort Command (64 bytes) 414 * 415 */ 416 typedef struct agsaSMPAbortCmd_s { 417 bit32 tag; 418 bit32 deviceId; 419 bit32 HTagAbort; 420 bit32 Scp; 421 bit32 reserved[11]; 422 } agsaSMPAbortCmd_t; 423 424 /** \brief the data structure of SATA Start Command 425 * 426 * use to describe MPI SATA Start Command (64 bytes) 427 * 428 */ 429 typedef struct agsaSATAStartCmd_s { 430 bit32 tag; /* 1 */ 431 bit32 deviceId; /* 2 */ 432 bit32 dataLen; /* 3 */ 433 bit32 optNCQTagataProt; /* 4 */ 434 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ 435 bit32 reserved1; /* 10 */ 436 bit32 reserved2; /* 11 */ 437 bit32 AddrLow0; /* 12 */ 438 bit32 AddrHi0; /* 13 */ 439 bit32 Len0; /* 14 */ 440 bit32 E0; /* 15 */ 441 bit32 ATAPICDB[4]; /* 16-19 */ 442 } agsaSATAStartCmd_t; 443 444 typedef struct agsaSATAEncryptStartCmd_s 445 { 446 bit32 tag; /* 1 */ 447 bit32 IniDeviceId; /* 2 */ 448 bit32 dataLen; /* 3 */ 449 bit32 optNCQTagataProt; /* 4 */ 450 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ 451 bit32 reserved1; /* 10 */ 452 bit32 Res_EPL_DESCL; /* 11 */ 453 bit32 resSKIPBYTES; /* 12 */ 454 bit32 Res_DPL_DESCL_NDPLR; /* 13 DIF per LA Address lo if DPLE is 1 */ 455 bit32 Res_EDPL_DESCH; /* 14 DIF per LA Address hi if DPLE is 1 */ 456 bit32 DIF_flags; /* 15 */ 457 bit32 udt; /* 16 */ 458 bit32 udtReplacementLo; /* 17 */ 459 bit32 udtReplacementHi; /* 18 */ 460 bit32 DIF_seed; /* 19 */ 461 bit32 encryptFlagsLo; /* 20 */ 462 bit32 encryptFlagsHi; /* 21 */ 463 bit32 keyTagLo; /* 22 */ 464 bit32 keyTagHi; /* 23 */ 465 bit32 tweakVal_W0; /* 24 */ 466 bit32 tweakVal_W1; /* 25 */ 467 bit32 tweakVal_W2; /* 26 */ 468 bit32 tweakVal_W3; /* 27 */ 469 bit32 AddrLow0; /* 28 */ 470 bit32 AddrHi0; /* 29 */ 471 bit32 Len0; /* 30 */ 472 bit32 E0; /* 31 */ 473 } agsaSATAEncryptStartCmd_t; 474 475 /** \brief the data structure of SATA Abort Command 476 * 477 * use to describe MPI SATA Abort Command (64 bytes) 478 * 479 */ 480 typedef struct agsaSATAAbortCmd_s { 481 bit32 tag; 482 bit32 deviceId; 483 bit32 HTagAbort; 484 bit32 abortAll; 485 bit32 reserved[11]; 486 } agsaSATAAbortCmd_t; 487 488 /** \brief the data structure of Local PHY Control Command 489 * 490 * use to describe MPI LOCAL PHY CONTROL Command (64 bytes) 491 * 492 */ 493 typedef struct agsaLocalPhyCntrlCmd_s { 494 bit32 tag; 495 bit32 phyOpPhyId; 496 bit32 reserved1[14]; 497 } agsaLocalPhyCntrlCmd_t; 498 499 /** \brief the data structure of Get Device Info Command 500 * 501 * use to describe MPI GET DEVIDE INFO Command (64 bytes) 502 * 503 */ 504 typedef struct agsaGetDevInfoCmd_s { 505 bit32 tag; 506 bit32 DeviceId; 507 bit32 reserved[13]; 508 } agsaGetDevInfoCmd_t; 509 510 /** \brief the data structure of HW Reset Command 511 * 512 * use to describe MPI HW Reset Command (64 bytes) 513 * 514 */ 515 typedef struct agsaHWResetCmd_s { 516 bit32 option; 517 bit32 reserved[14]; 518 } agsaHWResetCmd_t; 519 520 /** \brief the data structure of Firmware download 521 * 522 * use to describe MPI FW DOWNLOAD Command (64 bytes) 523 */ 524 typedef struct agsaFwFlashUpdate_s { 525 bit32 tag; 526 bit32 curImageOffset; 527 bit32 curImageLen; 528 bit32 totalImageLen; 529 bit32 reserved0[7]; 530 bit32 SGLAL; 531 bit32 SGLAH; 532 bit32 Len; 533 bit32 extReserved; 534 } agsaFwFlashUpdate_t; 535 536 537 /** \brief the data structure EXT Flash Op 538 * 539 * use to describe Extented Flash Operation Command (128 bytes) 540 */ 541 typedef struct agsaFwFlashOpExt_s { 542 bit32 tag; 543 bit32 Command; 544 bit32 PartOffset; 545 bit32 DataLength; 546 bit32 Reserved0[7]; 547 bit32 SGLAL; 548 bit32 SGLAH; 549 bit32 Len; 550 bit32 E_sgl; 551 bit32 Reserved[15]; 552 } agsaFwFlashOpExt_t; 553 554 /** \brief the data structure EXT Flash Op 555 * 556 * use to describe Extented Flash Operation Command (64 bytes) 557 */ 558 typedef struct agsaFwFlashOpExtRsp_s { 559 bit32 tag; 560 bit32 Command; 561 bit32 Status; 562 bit32 Epart_Size; 563 bit32 EpartSectSize; 564 bit32 Reserved[10]; 565 } agsaFwFlashOpExtRsp_t; 566 567 568 #define FWFLASH_IOMB_RESERVED_LEN 0x07 569 570 #ifdef SPC_ENABLE_PROFILE 571 typedef struct agsaFwProfileIOMB_s { 572 bit32 tag; 573 bit32 tcid_processor_cmd; 574 bit32 codeStartAdd; 575 bit32 codeEndAdd; 576 bit32 reserved0[7]; 577 bit32 SGLAL; 578 bit32 SGLAH; 579 bit32 Len; 580 bit32 extReserved; 581 } agsaFwProfileIOMB_t; 582 #define FWPROFILE_IOMB_RESERVED_LEN 0x07 583 #endif 584 /** \brief the data structure of GPIO Commannd 585 * 586 * use to describe MPI GPIO Command (64 bytes) 587 */ 588 typedef struct agsaGPIOCmd_s { 589 bit32 tag; 590 bit32 eOBIDGeGsGrGw; 591 bit32 GpioWrMsk; 592 bit32 GpioWrVal; 593 bit32 GpioIe; 594 bit32 OT11_0; 595 bit32 OT19_12; /* reserved for SPCv controller */ 596 bit32 GPIEVChange; 597 bit32 GPIEVRise; 598 bit32 GPIEVFall; 599 bit32 reserved[5]; 600 } agsaGPIOCmd_t; 601 602 603 #define GPIO_GW_BIT 0x1 604 #define GPIO_GR_BIT 0x2 605 #define GPIO_GS_BIT 0x4 606 #define GPIO_GE_BIT 0x8 607 608 /** \brief the data structure of SAS Diagnostic Start/End Command 609 * 610 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) 611 */ 612 typedef struct agsaSASDiagStartEndCmd_s { 613 bit32 tag; 614 bit32 OperationPhyId; 615 bit32 reserved[13]; 616 } agsaSASDiagStartEndCmd_t; 617 618 /** \brief the data structure of SAS Diagnostic Execute Command 619 * 620 * use to describe MPI SAS Diagnostic Execute Command for SPCv (128 bytes) 621 */ 622 typedef struct agsaSASDiagExecuteCmd_s { 623 bit32 tag; /* 1 */ 624 bit32 CmdTypeDescPhyId;/* 2 */ 625 bit32 Pat1Pat2; /* 3 */ 626 bit32 Threshold; /* 4 */ 627 bit32 CodePatErrMsk; /* 5 */ 628 bit32 Pmon; /* 6 */ 629 bit32 PERF1CTL; /* 7 */ 630 bit32 THRSHLD1; /* 8 */ 631 bit32 reserved[23]; /* 9 31 */ 632 } agsaSASDiagExecuteCmd_t; 633 634 635 /** \brief the data structure of SAS Diagnostic Execute Command 636 * 637 * use to describe MPI SAS Diagnostic Execute Command for SPC (64 bytes) 638 */ 639 typedef struct agsa_SPC_SASDiagExecuteCmd_s { 640 bit32 tag; /* 1 */ 641 bit32 CmdTypeDescPhyId;/* 2 */ 642 bit32 Pat1Pat2; /* 3 */ 643 bit32 Threshold; /* 4 */ 644 bit32 CodePatErrMsk; /* 5 */ 645 bit32 Pmon; /* 6 */ 646 bit32 PERF1CTL; /* 7 */ 647 bit32 reserved[8]; /* 8 15 */ 648 } agsa_SPC_SASDiagExecuteCmd_t; 649 #define SAS_DIAG_PARAM_BYTES 24 650 651 652 /** \brief the data structure of SSP TGT IO Start Command 653 * 654 * use to describe MPI SSP TGT IO Start Command (64 bytes) 655 * 656 */ 657 typedef struct agsaSSPTgtIOStartCmd_s { 658 bit32 tag; /* 1 */ 659 bit32 deviceId; /* 2 */ 660 bit32 dataLen; /* 3 */ 661 bit32 dataOffset; /* 4 */ 662 bit32 INITagAgrDir; /* 5 */ 663 bit32 reserved; /* 6 */ 664 bit32 DIF_flags; /* 7 */ 665 bit32 udt; /* 8 */ 666 bit32 udtReplacementLo; /* 9 */ 667 bit32 udtReplacementHi; /* 10 */ 668 bit32 DIF_seed; /* 11 */ 669 bit32 AddrLow0; /* 12 */ 670 bit32 AddrHi0; /* 13 */ 671 bit32 Len0; /* 14 */ 672 bit32 E0; /* 15 */ 673 } agsaSSPTgtIOStartCmd_t; 674 675 /** \brief the data structure of SSP TGT Response Start Command 676 * 677 * use to describe MPI SSP TGT Response Start Command (64 bytes) 678 * 679 */ 680 typedef struct agsaSSPTgtRspStartCmd_s { 681 bit32 tag; 682 bit32 deviceId; 683 bit32 RspLen; 684 bit32 INITag_IP_AN; 685 bit32 reserved[7]; 686 bit32 AddrLow0; 687 bit32 AddrHi0; 688 bit32 Len0; 689 bit32 E0; 690 } agsaSSPTgtRspStartCmd_t; 691 692 /** \brief the data structure of Device Handle Accept Command 693 * 694 * use to describe MPI Device Handle Accept Command (64 bytes) 695 * 696 */ 697 typedef struct agsaDevHandleAcceptCmd_s { 698 bit32 tag; 699 bit32 Ctag; 700 bit32 deviceId; 701 bit32 DevA_MCN_R_R_HA_ITNT; 702 bit32 reserved[11]; 703 } agsaDevHandleAcceptCmd_t; 704 705 /** \brief the data structure of SAS HW Event Ack Command 706 * 707 * use to describe MPI SAS HW Event Ack Command (64 bytes) 708 * 709 */ 710 typedef struct agsaSASHwEventAckCmd_s { 711 bit32 tag; 712 bit32 sEaPhyIdPortId; 713 bit32 Param0; 714 bit32 Param1; 715 bit32 reserved[11]; 716 } agsaSASHwEventAckCmd_t; 717 718 /** \brief the data structure of Get Time Stamp Command 719 * 720 * use to describe MPI Get Time Stamp Command (64 bytes) 721 * 722 */ 723 typedef struct agsaGetTimeStampCmd_s { 724 bit32 tag; 725 bit32 reserved[14]; 726 } agsaGetTimeStampCmd_t; 727 728 /** \brief the data structure of Port Control Command 729 * 730 * use to describe MPI Port Control Command (64 bytes) 731 * 732 */ 733 typedef struct agsaPortControlCmd_s { 734 bit32 tag; 735 bit32 portOPPortId; 736 bit32 Param0; 737 bit32 Param1; 738 bit32 reserved[11]; 739 } agsaPortControlCmd_t; 740 741 /** \brief the data structure of Set NVM Data Command 742 * 743 * use to describe MPI Set NVM Data Command (64 bytes) 744 * 745 */ 746 typedef struct agNVMIndirect_s { 747 bit32 signature; 748 bit32 reserved[7]; 749 bit32 ISglAL; 750 bit32 ISglAH; 751 bit32 ILen; 752 bit32 reserved1; 753 } agNVMIndirect_t; 754 755 typedef union agsaSetNVMData_s { 756 bit32 NVMData[12]; 757 agNVMIndirect_t indirectData; 758 } agsaSetNVMData_t; 759 760 typedef struct agsaSetNVMDataCmd_s { 761 bit32 tag; 762 bit32 LEN_IR_VPDD; 763 bit32 VPDOffset; 764 agsaSetNVMData_t Data; 765 } agsaSetNVMDataCmd_t; 766 767 /** \brief the data structure of Get NVM Data Command 768 * 769 * use to describe MPI Get NVM Data Command (64 bytes) 770 * 771 */ 772 typedef struct agsaGetNVMDataCmd_s { 773 bit32 tag; 774 bit32 LEN_IR_VPDD; 775 bit32 VPDOffset; 776 bit32 reserved[8]; 777 bit32 respAddrLo; 778 bit32 respAddrHi; 779 bit32 respLen; 780 bit32 reserved1; 781 } agsaGetNVMDataCmd_t; 782 783 #define TWI_DEVICE 0x0 784 #define C_SEEPROM 0x1 785 #define VPD_FLASH 0x4 786 #define AAP1_RDUMP 0x5 787 #define IOP_RDUMP 0x6 788 #define EXPAN_ROM 0x7 789 790 #define DIRECT_MODE 0x0 791 #define INDIRECT_MODE 0x1 792 793 #define IRMode 0x80000000 794 #define IPMode 0x80000000 795 #define NVMD_TYPE 0x0000000F 796 #define NVMD_STAT 0x0000FFFF 797 #define NVMD_LEN 0xFF000000 798 799 #define TWI_DEVICE 0x0 800 #define SEEPROM 0x1 801 802 /** \brief the data structure of Set Device State Command 803 * 804 * use to describe MPI Set Device State Command (64 bytes) 805 * 806 */ 807 typedef struct agsaSetDeviceStateCmd_s { 808 bit32 tag; 809 bit32 deviceId; 810 bit32 NDS; 811 bit32 reserved[12]; 812 } agsaSetDeviceStateCmd_t; 813 814 #define DS_OPERATIONAL 0x01 815 #define DS_IN_RECOVERY 0x03 816 #define DS_IN_ERROR 0x04 817 #define DS_NON_OPERATIONAL 0x07 818 819 /** \brief the data structure of Get Device State Command 820 * 821 * use to describe MPI Get Device State Command (64 bytes) 822 * 823 */ 824 typedef struct agsaGetDeviceStateCmd_s { 825 bit32 tag; 826 bit32 deviceId; 827 bit32 reserved[13]; 828 } agsaGetDeviceStateCmd_t; 829 830 /** \brief the data structure of Set Device Info Command 831 * 832 * use to describe MPI OPC_INB_SET_DEV_INFO (0x02c) Command (64 bytes) 833 * 834 */ 835 typedef struct agsaSetDevInfoCmd_s { 836 bit32 tag; 837 bit32 deviceId; 838 bit32 SA_SR_SI; 839 bit32 DEVA_MCN_R_ITNT; 840 bit32 reserved[11]; 841 } agsaSetDevInfoCmd_t; 842 843 #define SET_DEV_INFO_V_DW3_MASK 0x0000003F 844 #define SET_DEV_INFO_V_DW4_MASK 0xFF07FFFF 845 #define SET_DEV_INFO_SPC_DW3_MASK 0x7 846 #define SET_DEV_INFO_SPC_DW4_MASK 0x003FFFF 847 848 #define SET_DEV_INFO_V_DW3_SM_SHIFT 3 849 #define SET_DEV_INFO_V_DW3_SA_SHIFT 2 850 #define SET_DEV_INFO_V_DW3_SR_SHIFT 1 851 #define SET_DEV_INFO_V_DW3_SI_SHIFT 0 852 853 #define SET_DEV_INFO_V_DW4_MCN_SHIFT 24 854 #define SET_DEV_INFO_V_DW4_AWT_SHIFT 17 855 #define SET_DEV_INFO_V_DW4_RETRY_SHIFT 16 856 #define SET_DEV_INFO_V_DW4_ITNEXUS_SHIFT 0 857 858 /** \brief the data structure of SAS Re_Initialize Command 859 * 860 * use to describe MPI SAS RE_INITIALIZE Command (64 bytes) 861 * 862 */ 863 typedef struct agsaSasReInitializeCmd_s { 864 bit32 tag; 865 bit32 setFlags; 866 bit32 MaxPorts; 867 bit32 openRejReCmdData; 868 bit32 sataHOLTMO; 869 bit32 reserved[10]; 870 } agsaSasReInitializeCmd_t; 871 872 873 /** \brief the data structure of SGPIO Command 874 * 875 * use to describe MPI serial GPIO Command (64 bytes) 876 * 877 */ 878 typedef struct agsaSGpioCmd_s { 879 bit32 tag; 880 bit32 regIndexRegTypeFunctionFrameType; 881 bit32 regCount; 882 bit32 writeData[OSSA_SGPIO_MAX_WRITE_DATA_COUNT]; 883 } agsaSGpioCmd_t; 884 885 /** \brief the data structure of PCIE Diagnostic Command 886 * 887 * use to describe MPI PCIE Diagnostic Command for SPCv (128 bytes) 888 * 889 */ 890 typedef struct agsaPCIeDiagExecuteCmd_s { 891 bit32 tag; /* 1 */ 892 bit32 CmdTypeDesc; /* 2 */ 893 bit32 UUM_EDA; /* 3 */ 894 bit32 UDTR1_UDT0; /* 4 */ 895 bit32 UDT5_UDT2; /* 5 */ 896 bit32 UDTR5_UDTR2; /* 6 */ 897 bit32 Res_IOS; /* 7 */ 898 bit32 rdAddrLower; /* 8 */ 899 bit32 rdAddrUpper; /* 9 */ 900 bit32 wrAddrLower; /* 10 */ 901 bit32 wrAddrUpper; /* 11 */ 902 bit32 len; /* 12 */ 903 bit32 pattern; /* 13 */ 904 bit32 reserved2[2]; /* 14 15 */ 905 bit32 reserved3[16]; /* 15 31 */ 906 } agsaPCIeDiagExecuteCmd_t; 907 908 909 /** \brief the data structure of PCI Diagnostic Command for SPC 910 * 911 * use to describe MPI PCI Diagnostic Command for SPC (64 bytes) 912 * 913 */ 914 typedef struct agsa_SPC_PCIDiagExecuteCmd_s { 915 bit32 tag; 916 bit32 CmdTypeDesc; 917 bit32 reserved1[5]; 918 bit32 rdAddrLower; 919 bit32 rdAddrUpper; 920 bit32 wrAddrLower; 921 bit32 wrAddrUpper; 922 bit32 len; 923 bit32 pattern; 924 bit32 reserved2[2]; 925 } agsa_SPC_PCIDiagExecuteCmd_t; 926 927 /** \brief the data structure of GET DFE Data Command 928 * 929 * use to describe GET DFE Data Command for SPCv (128 bytes) 930 * 931 */ 932 typedef struct agsaGetDDEFDataCmd_s { 933 bit32 tag; /* 1 */ 934 bit32 reserved_In_Ln;/* 2 */ 935 bit32 MCNT; /* 3 */ 936 bit32 reserved1[3]; /* 4 - 6 */ 937 bit32 Buf_AddrL; /* 7 */ 938 bit32 Buf_AddrH; /* 8 */ 939 bit32 Buf_Len; /* 9 */ 940 bit32 E_reserved; /* 10 */ 941 bit32 reserved2[21]; /* 11 - 31 */ 942 } agsaGetDDEFDataCmd_t; 943 944 945 /*********************************************** 946 * outbound IOMBs 947 ***********************************************/ 948 /** \brief the data structure of Echo Response 949 * 950 * use to describe MPI Echo Response (64 bytes) 951 * 952 */ 953 typedef struct agsaEchoRsp_s { 954 bit32 tag; 955 bit32 payload[14]; 956 } agsaEchoRsp_t; 957 958 /** \brief the data structure of HW Event from Outbound 959 * 960 * use to describe MPI HW Event (64 bytes) 961 * 962 */ 963 typedef struct agsaHWEvent_SPC_OUB_s { 964 bit32 LRStatusEventPhyIdPortId; 965 bit32 EVParam; 966 bit32 NpipPortState; 967 agsaSASIdentify_t sasIdentify; 968 agsaFisRegDeviceToHost_t sataFis; 969 } agsaHWEvent_SPC_OUB_t; 970 971 #define PHY_ID_BITS 0x000000F0 972 #define LINK_RATE_MASK 0xF0000000 973 #define STATUS_BITS 0x0F000000 974 #define HW_EVENT_BITS 0x00FFFF00 975 976 typedef struct agsaHWEvent_Phy_OUB_s { 977 bit32 tag; 978 bit32 Status; 979 bit32 ReservedPhyId; 980 } agsaHWEvent_Phy_OUB_t; 981 982 /** \brief the data structure of HW Event from Outbound 983 * 984 * use to describe MPI HW Event (64 bytes) 985 * 986 */ 987 typedef struct agsaHWEvent_V_OUB_s { 988 bit32 LRStatEventPortId; 989 bit32 EVParam; 990 bit32 RsvPhyIdNpipRsvPortState; 991 agsaSASIdentify_t sasIdentify; 992 agsaFisRegDeviceToHost_t sataFis; 993 } agsaHWEvent_V_OUB_t; 994 995 #define PHY_ID_V_BITS 0x00FF0000 996 #define NIPP_V_BITS 0x0000FF00 997 998 999 1000 /** \brief the data structure of SSP Completion Response 1001 * 1002 * use to describe MPI SSP Completion Response (1024 bytes) 1003 * 1004 */ 1005 typedef struct agsaSSPCompletionRsp_s { 1006 bit32 tag; 1007 bit32 status; 1008 bit32 param; 1009 bit32 SSPTag; 1010 agsaSSPResponseInfoUnit_t SSPrsp; 1011 bit32 respData; 1012 bit32 senseData[5]; 1013 bit32 respData1[239]; 1014 } agsaSSPCompletionRsp_t; 1015 1016 1017 /** \brief the data structure of SSP Completion DIF Response 1018 * 1019 * use to describe MPI SSP Completion DIF Response (1024 bytes) 1020 * 1021 */ 1022 typedef struct agsaSSPCompletionDifRsp_s { 1023 bit32 tag; 1024 bit32 status; 1025 bit32 param; 1026 bit32 SSPTag; 1027 bit32 Device_Id; 1028 bit32 UpperLBA; 1029 bit32 LowerLBA; 1030 bit32 sasAddressHi; 1031 bit32 sasAddressLo; 1032 bit32 ExpectedCRCUDT01; 1033 bit32 ExpectedUDT2345; 1034 bit32 ActualCRCUDT01; 1035 bit32 ActualUDT2345; 1036 bit32 DIFErrDevID; 1037 bit32 ErrBoffsetEDataLen; 1038 bit32 EDATA_FRM; 1039 1040 } agsaSSPCompletionDifRsp_t; 1041 1042 1043 /* SSPTag bit fields Bits [31:16] */ 1044 #define SSP_RESCV_BIT 0x00010000 /* Bits [16] */ 1045 #define SSP_RESCV_PAD 0x00060000 /* Bits [18:17] */ 1046 #define SSP_RESCV_PAD_SHIFT 17 1047 #define SSP_AGR_S_BIT (1 << 19) /* Bits [19] */ 1048 1049 /** \brief the data structure of SMP Completion Response 1050 * 1051 * use to describe MPI SMP Completion Response (1024 bytes) 1052 * 1053 */ 1054 typedef struct agsaSMPCompletionRsp_s { 1055 bit32 tag; 1056 bit32 status; 1057 bit32 param; 1058 bit32 SMPrsp[252]; 1059 } agsaSMPCompletionRsp_t; 1060 1061 /** \brief the data structure of Deregister Device Response 1062 * 1063 * use to describe MPI Deregister Device Response (64 bytes) 1064 * 1065 */ 1066 typedef struct agsaDeregDevHandleRsp_s { 1067 bit32 tag; 1068 bit32 status; 1069 bit32 deviceId; 1070 bit32 reserved[12]; 1071 } agsaDeregDevHandleRsp_t; 1072 1073 /** \brief the data structure of Get Device Handle Response 1074 * 1075 * use to describe MPI Get Device Handle Response (64 bytes) 1076 * 1077 */ 1078 typedef struct agsaGetDevHandleRsp_s { 1079 bit32 tag; 1080 bit32 DeviceIdcPortId; 1081 bit32 deviceId[13]; 1082 } agsaGetDevHandleRsp_t; 1083 1084 #define DEVICE_IDC_BITS 0x00FFFF00 1085 #define DEVICE_ID_BITS 0x00000FFF 1086 1087 /** \brief the data structure of Local Phy Control Response 1088 * 1089 * use to describe MPI Local Phy Control Response (64 bytes) 1090 * 1091 */ 1092 typedef struct agsaLocalPhyCntrlRsp_s { 1093 bit32 tag; 1094 bit32 phyOpId; 1095 bit32 status; 1096 bit32 reserved[12]; 1097 } agsaLocalPhyCntrlRsp_t; 1098 1099 #define LOCAL_PHY_OP_BITS 0x0000FF00 1100 #define LOCAL_PHY_PHYID 0x000000FF 1101 1102 /** \brief the data structure of DEVICE_REGISTRATION Response 1103 * 1104 * use to describe device registration response (64 bytes) 1105 * 1106 */ 1107 typedef struct agsaDeviceRegistrationRsp_s { 1108 bit32 tag; 1109 bit32 status; 1110 bit32 deviceId; 1111 bit32 reserved[12]; 1112 } agsaDeviceRegistrationRsp_t; 1113 1114 1115 #define FAILURE_OUT_OF_RESOURCE 0x01 /* The device registration failed because the SPC 8x6G is running out of device handle resources. The parameter DEVICE_ID is not used. */ 1116 #define FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /* The device registration failed because the SPC 8x6G detected an existing device handle with a similar SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ 1117 #define FAILURE_INVALID_PHY_ID 0x03 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an invalid (out-of-range) PHY ID. */ 1118 #define FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an already -registered PHY ID for a directly attached SATA drive. */ 1119 #define FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /* PORT_ID specified in the REGISTER_DEVICE Command is out-of range (0-7). */ 1120 #define FAILURE_PORT_NOT_VALID_STATE 0x06 /* The PORT_ID specified in the REGISTER_DEVICE Command is not in PORT_VALID state. */ 1121 #define FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /* The device type, specified in the �S field in the REGISTER_DEVICE Command is not valid. */ 1122 1123 #define MPI_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 /* The device registration failed because the SPCv controller is running out of device handle resources. The parameter DEVICE_ID is not used. */ 1124 #define MPI_ERR_DEVICE_ALREADY_REGISTERED 0x1021 /* The device registration failed because the SPCv controller detected an existing device handle with the same SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ 1125 #define MPI_ERR_DEVICE_TYPE_NOT_VALID 0x1022 /* The device type, specified in the �S field in the REGISTER_DEVICE_HANDLE Command (page 274) is not valid. */ 1126 #define MPI_ERR_PORT_INVALID_PORT_ID 0x1041 /* specified in the REGISTER_DEVICE_HANDLE Command (page 274) is invalid. i.e Out of supported range */ 1127 #define MPI_ERR_PORT_STATE_NOT_VALID 0x1042 /* The PORT_ID specified in the REGISTER_DEVICE_HANDLE Command (page 274) is not in PORT_VALID state. */ 1128 #define MPI_ERR_PORT_STATE_NOT_IN_USE 0x1043 1129 #define MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 1130 #define MPI_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 1131 #define MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /*MPI_ERR_DEVICE_ACCEPT_PENDING*/ 1132 1133 1134 #define MPI_ERR_PHY_ID_INVALID 0x1061 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an invalid (out-of-range) PHY ID. */ 1135 #define MPI_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an alreadyregistered PHY ID for a directly-attached SATA drive. */ 1136 1137 1138 1139 1140 /** \brief the data structure of SATA Completion Response 1141 * 1142 * use to describe MPI SATA Completion Response (64 bytes) 1143 * 1144 */ 1145 typedef struct agsaSATACompletionRsp_s { 1146 bit32 tag; 1147 bit32 status; 1148 bit32 param; 1149 bit32 FSATArsp; 1150 bit32 respData[11]; 1151 } agsaSATACompletionRsp_t; 1152 1153 /** \brief the data structure of SATA Event Response 1154 * 1155 * use to describe MPI SATA Event Response (64 bytes) 1156 * 1157 */ 1158 typedef struct agsaSATAEventRsp_s { 1159 bit32 tag; 1160 bit32 event; 1161 bit32 portId; 1162 bit32 deviceId; 1163 bit32 reserved[11]; 1164 } agsaSATAEventRsp_t; 1165 1166 /** \brief the data structure of SSP Event Response 1167 * 1168 * use to describe MPI SSP Event Response (64 bytes) 1169 * 1170 */ 1171 typedef struct agsaSSPEventRsp_s { 1172 bit32 tag; 1173 bit32 event; 1174 bit32 portId; 1175 bit32 deviceId; 1176 bit32 SSPTag; 1177 bit32 EVT_PARAM0_or_LBAH; 1178 bit32 EVT_PARAM1_or_LBAL; 1179 bit32 SAS_ADDRH; 1180 bit32 SAS_ADDRL; 1181 bit32 UDT1_E_UDT0_E_CRC_E; 1182 bit32 UDT5_E_UDT4_E_UDT3_E_UDT2_E; 1183 bit32 UDT1_A_UDT0_A_CRC_A; 1184 bit32 UDT5_A_UDT4_A_UDT3_A_UDT2_A; 1185 bit32 HW_DEVID_Reserved_DIF_ERR; 1186 bit32 EDATA_LEN_ERR_BOFF; 1187 bit32 EDATA_FRM; 1188 } agsaSSPEventRsp_t; 1189 1190 #define SSPTAG_BITS 0x0000FFFF 1191 1192 /** \brief the data structure of Get Device Info Response 1193 * 1194 * use to describe MPI Get Device Info Response (64 bytes) 1195 * 1196 */ 1197 typedef struct agsaGetDevInfoRspSpc_s { 1198 bit32 tag; 1199 bit32 status; 1200 bit32 deviceId; 1201 bit32 dTypeSrateSMPTOArPortID; 1202 bit32 FirstBurstSizeITNexusTimeOut; 1203 bit8 sasAddrHi[4]; 1204 bit8 sasAddrLow[4]; 1205 bit32 reserved[8]; 1206 } agsaGetDevInfoRsp_t; 1207 1208 #define SMPTO_BITS 0xFFFF 1209 #define NEXUSTO_BITS 0xFFFF 1210 #define FIRST_BURST 0xFFFF 1211 #define FLAG_BITS 0x3 1212 #define LINK_RATE_BITS 0xFF 1213 #define DEV_TYPE_BITS 0x30000000 1214 1215 /** \brief the data structure of Get Device Info Response V 1216 * 1217 * use to describe MPI Get Device Info Response (64 bytes) 1218 * 1219 */ 1220 typedef struct agsaGetDevInfoRspV_s { 1221 bit32 tag; 1222 bit32 status; 1223 bit32 deviceId; 1224 bit32 ARSrateSMPTimeOutPortID; 1225 bit32 IRMcnITNexusTimeOut; 1226 bit8 sasAddrHi[4]; 1227 bit8 sasAddrLow[4]; 1228 bit32 reserved[8]; 1229 } agsaGetDevInfoRspV_t; 1230 1231 #define SMPTO_VBITS 0xFFFF 1232 #define NEXUSTO_VBITS 0xFFFF 1233 #define FIRST_BURST_MCN 0xF 1234 #define FLAG_VBITS 0x3 1235 #define LINK_RATE_VBITS 0xFF 1236 #define DEV_TYPE_VBITS 0x10000000 1237 1238 1239 /** \brief the data structure of Get Phy Profile Command IOMB V 1240 * 1241 */ 1242 typedef struct agsaGetPhyProfileCmd_V_s { 1243 bit32 tag; 1244 bit32 Reserved_Ppc_SOP_PHYID; 1245 bit32 reserved[29]; 1246 } agsaGetPhyProfileCmd_V_t; 1247 1248 1249 /** \brief the data structure of Get Phy Profile Response IOMB V 1250 * 1251 */ 1252 typedef struct agsaGetPhyProfileRspV_s { 1253 bit32 tag; 1254 bit32 status; 1255 bit32 Reserved_Ppc_SOP_PHYID; 1256 bit32 PageSpecificArea[12]; 1257 } agsaGetPhyProfileRspV_t; 1258 1259 /** \brief the data structure of Set Phy Profile Command IOMB V 1260 * 1261 */ 1262 typedef struct agsaSetPhyProfileCmd_V_s { 1263 bit32 tag; 1264 bit32 Reserved_Ppc_SOP_PHYID; 1265 bit32 PageSpecificArea[29]; 1266 } agsaSetPhyProfileCmd_V_t; 1267 1268 /** \brief the data structure of GetVis Command IOMB V 1269 * OPC_OUB_GET_VIST_CAP_RSP 1270 */ 1271 typedef struct agsaGetVHistCap_V_s { 1272 bit32 tag; 1273 bit32 Channel; 1274 bit32 NumBitLo; 1275 bit32 NumBitHi; 1276 bit32 reserved0; 1277 bit32 reserved1; 1278 bit32 PcieAddrLo; 1279 bit32 PcieAddrHi; 1280 bit32 ByteCount; 1281 bit32 reserved2[22]; 1282 } agsaGetVHistCap_V_t; 1283 1284 /** \brief the data structure of Set Phy Profile Response IOMB V 1285 * 1286 */ 1287 typedef struct agsaSetPhyProfileRspV_s { 1288 bit32 tag; 1289 bit32 status; 1290 bit32 Reserved_Ppc_PHYID; 1291 bit32 PageSpecificArea[12]; 1292 } agsaSetPhyProfileRspV_t; 1293 1294 typedef struct agsaGetPhyInfoV_s { 1295 bit32 tag; 1296 bit32 Reserved_SOP_PHYID; 1297 bit32 reserved[28]; 1298 } agsaGetPhyInfoV_t; 1299 1300 1301 #define SPC_GET_SAS_PHY_ERR_COUNTERS 1 1302 #define SPC_GET_SAS_PHY_ERR_COUNTERS_CLR 2 1303 #define SPC_GET_SAS_PHY_BW_COUNTERS 3 1304 1305 1306 /** \brief the data structure of FW_FLASH_UPDATE Response 1307 * 1308 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) 1309 * 1310 */ 1311 typedef struct agsaFwFlashUpdateRsp_s { 1312 bit32 tag; 1313 bit32 status; 1314 bit32 reserved[13]; 1315 } agsaFwFlashUpdateRsp_t; 1316 1317 #ifdef SPC_ENABLE_PROFILE 1318 typedef struct agsaFwProfileRsp_s { 1319 bit32 tag; 1320 bit32 status; 1321 bit32 len; 1322 bit32 reserved[12]; 1323 } agsaFwProfileRsp_t; 1324 #endif 1325 /** \brief the data structure of GPIO Response 1326 * 1327 * use to describe MPI GPIO Response (64 bytes) 1328 */ 1329 typedef struct agsaGPIORsp_s { 1330 bit32 tag; 1331 bit32 reserved[2]; 1332 bit32 GpioRdVal; 1333 bit32 GpioIe; 1334 bit32 OT11_0; 1335 bit32 OT19_12; 1336 bit32 GPIEVChange; 1337 bit32 GPIEVRise; 1338 bit32 GPIEVFall; 1339 bit32 reserved1[5]; 1340 } agsaGPIORsp_t; 1341 1342 /** \brief the data structure of GPIO Event 1343 * 1344 * use to describe MPI GPIO Event Response (64 bytes) 1345 */ 1346 typedef struct agsaGPIOEvent_s { 1347 bit32 GpioEvent; 1348 bit32 reserved[14]; 1349 } agsaGPIOEvent_t; 1350 1351 /** \brief the data structure of GENERAL_EVENT Response 1352 * 1353 * use to describe MPI GENERNAL_EVENT Notification (64 bytes) 1354 * 1355 */ 1356 typedef struct agsaGenernalEventRsp_s { 1357 bit32 status; 1358 bit32 inboundIOMB[14]; 1359 } agsaGenernalEventRsp_t; 1360 1361 /** \brief the data structure of SSP_ABORT Response 1362 * 1363 * use to describe MPI SSP_ABORT (64 bytes) 1364 * 1365 */ 1366 typedef struct agsaSSPAbortRsp_s { 1367 bit32 tag; 1368 bit32 status; 1369 bit32 scp; 1370 bit32 reserved[12]; 1371 } agsaSSPAbortRsp_t; 1372 1373 /** \brief the data structure of SATA_ABORT Response 1374 * 1375 * use to describe MPI SATA_ABORT (64 bytes) 1376 * 1377 */ 1378 typedef struct agsaSATAAbortRsp_s { 1379 bit32 tag; 1380 bit32 status; 1381 bit32 scp; 1382 bit32 reserved[12]; 1383 } agsaSATAAbortRsp_t; 1384 1385 /** \brief the data structure of SAS Diagnostic Start/End Response 1386 * 1387 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) 1388 * 1389 */ 1390 typedef struct agsaSASDiagStartEndRsp_s { 1391 bit32 tag; 1392 bit32 Status; 1393 bit32 reserved[13]; 1394 } agsaSASDiagStartEndRsp_t; 1395 1396 /** \brief the data structure of SAS Diagnostic Execute Response 1397 * 1398 * use to describe MPI SAS Diagnostic Execute Response (64 bytes) 1399 * 1400 */ 1401 typedef struct agsaSASDiagExecuteRsp_s { 1402 bit32 tag; 1403 bit32 CmdTypeDescPhyId; 1404 bit32 Status; 1405 bit32 ReportData; 1406 bit32 reserved[11]; 1407 } agsaSASDiagExecuteRsp_t; 1408 1409 /** \brief the data structure of General Event Notification Response 1410 * 1411 * use to describe MPI General Event Notification Response (64 bytes) 1412 * 1413 */ 1414 typedef struct agsaGeneralEventRsp_s { 1415 bit32 status; 1416 bit32 inbIOMBpayload[14]; 1417 } agsaGeneralEventRsp_t; 1418 1419 #define GENERAL_EVENT_PAYLOAD 14 1420 #define OPCODE_BITS 0x00000fff 1421 1422 /* 1423 Table 171 GENERAL_EVENT Notification Status Field Codes 1424 Value Name Description 1425 */ 1426 #define GEN_EVENT_IOMB_V_BIT_NOT_SET 0x01 /* INBOUND_ Inbound IOMB is received with the V bit in the IOMB header not set. */ 1427 #define GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED 0x02 /* Inbound IOMB is received with an unsupported OPC. */ 1428 #define GEN_EVENT_IOMB_INVALID_OBID 0x03 /* INBOUND Inbound IOMB is received with an invalid OBID. */ 1429 #define GEN_EVENT_DS_IN_NON_OPERATIONAL 0x39 /* DEVICE_HANDLE_ACCEPT command failed due to the device being in DS_NON_OPERATIONAL state. */ 1430 #define GEN_EVENT_DS_IN_RECOVERY 0x3A /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_IN_RECOVERY state. */ 1431 #define GEN_EVENT_DS_INVALID 0x49 /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_INVALID state. */ 1432 1433 #define GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x50 /* Indicates the PCIe Read Request to fetch one or more inbound IOMBs received 1434 a failed completion response. The first and second Dwords of the 1435 INBOUND IOMB field ( Dwords 2 and 3) contains information to identifying 1436 the location in the inbound queue where the error occurred. 1437 Dword 2 bits[15:0] contains the inbound queue number. 1438 Dword 2 bits[31:16] specifies how many consecutive IOMBs were affected 1439 by the failed DMA. 1440 Dword 3 specifies the Consumer Index [CI] of the inbound queue where 1441 the DMA operation failed.*/ 1442 1443 /** \brief the data structure of SSP Request Received Notification 1444 * 1445 * use to describe MPI SSP Request Received Notification ( 1024 bytes) 1446 * 1447 */ 1448 typedef struct agsaSSPReqReceivedNotify_s { 1449 bit32 deviceId; 1450 bit32 iniTagSSPIul; 1451 bit32 frameTypeHssa; 1452 bit32 TlrHdsa; 1453 bit32 SSPIu[251]; 1454 } agsaSSPReqReceivedNotify_t; 1455 1456 #define SSPIUL_BITS 0x0000FFFF 1457 #define INITTAG_BITS 0x0000FFFF 1458 #define FRAME_TYPE 0x000000FF 1459 #define TLR_BITS 0x00000300 1460 1461 /** \brief the data structure of Device Handle Arrived Notification 1462 * 1463 * use to describe MPI Device Handle Arrived Notification ( 64 bytes) 1464 * 1465 */ 1466 typedef struct agsaDeviceHandleArrivedNotify_s { 1467 bit32 CTag; 1468 bit32 HostAssignedIdFwdDeviceId; 1469 bit32 ProtConrPortId; 1470 bit8 sasAddrHi[4]; 1471 bit8 sasAddrLow[4]; 1472 bit32 reserved[10]; 1473 1474 } agsaDeviceHandleArrivedNotify_t; 1475 1476 1477 #define Conrate_V_MASK 0x0000F000 1478 #define Conrate_V_SHIFT 12 1479 #define Conrate_SPC_MASK 0x0000F000 1480 #define Conrate_SPC_SHIFT 4 1481 1482 #define Protocol_SPC_MASK 0x00000700 1483 #define Protocol_SPC_SHIFT 8 1484 #define Protocol_SPC_MASK 0x00000700 1485 #define Protocol_SPC_SHIFT 8 1486 1487 #define PortId_V_MASK 0xFF 1488 #define PortId_SPC_MASK 0x0F 1489 1490 #define PROTOCOL_BITS 0x00000700 1491 #define PROTOCOL_SHIFT 8 1492 1493 #define SHIFT_REG_64K_MASK 0xffff0000 1494 #define SHIFT_REG_BIT_SHIFT 8 1495 #define SPC_GSM_SM_OFFSET 0x400000 1496 #define SPCV_GSM_SM_OFFSET 0x0 1497 1498 /** \brief the data structure of Get Time Stamp Response 1499 * 1500 * use to describe MPI Get TIme Stamp Response ( 64 bytes) 1501 * 1502 */ 1503 typedef struct agsaGetTimeStampRsp_s { 1504 bit32 tag; 1505 bit32 timeStampLower; 1506 bit32 timeStampUpper; 1507 bit32 reserved[12]; 1508 } agsaGetTimeStampRsp_t; 1509 1510 /** \brief the data structure of SAS HW Event Ack Response 1511 * 1512 * use to describe SAS HW Event Ack Response ( 64 bytes) 1513 * 1514 */ 1515 typedef struct agsaSASHwEventAckRsp_s { 1516 bit32 tag; 1517 bit32 status; 1518 bit32 reserved[13]; 1519 } agsaSASHwEventAckRsp_t; 1520 1521 /** \brief the data structure of Port Control Response 1522 * 1523 * use to describe Port Control Response ( 64 bytes) 1524 * 1525 */ 1526 typedef struct agsaPortControlRsp_s { 1527 bit32 tag; 1528 bit32 portOPPortId; 1529 bit32 status; 1530 bit32 rsvdPortState; 1531 bit32 reserved[11]; 1532 } agsaPortControlRsp_t; 1533 1534 /** \brief the data structure of SMP Abort Response 1535 * 1536 * use to describe SMP Abort Response ( 64 bytes) 1537 * 1538 */ 1539 typedef struct agsaSMPAbortRsp_s { 1540 bit32 tag; 1541 bit32 status; 1542 bit32 scp; 1543 bit32 reserved[12]; 1544 } agsaSMPAbortRsp_t; 1545 1546 /** \brief the data structure of Get NVMD Data Response 1547 * 1548 * use to describe MPI Get NVMD Data Response (64 bytes) 1549 * 1550 */ 1551 typedef struct agsaGetNVMDataRsp_s { 1552 bit32 tag; 1553 bit32 iRTdaBnDpsAsNvm; 1554 bit32 DlenStatus; 1555 bit32 NVMData[12]; 1556 } agsaGetNVMDataRsp_t; 1557 1558 /** \brief the data structure of Set NVMD Data Response 1559 * 1560 * use to describe MPI Set NVMD Data Response (64 bytes) 1561 * 1562 */ 1563 typedef struct agsaSetNVMDataRsp_s { 1564 bit32 tag; 1565 bit32 iPTdaBnDpsAsNvm; 1566 bit32 status; 1567 bit32 reserved[12]; 1568 } agsaSetNVMDataRsp_t; 1569 1570 /** \brief the data structure of Device Handle Removal 1571 * 1572 * use to describe MPI Device Handle Removel Notification (64 bytes) 1573 * 1574 */ 1575 typedef struct agsaDeviceHandleRemoval_s { 1576 bit32 portId; 1577 bit32 deviceId; 1578 bit32 reserved[13]; 1579 } agsaDeviceHandleRemoval_t; 1580 1581 /** \brief the data structure of Set Device State Response 1582 * 1583 * use to describe MPI Set Device State Response (64 bytes) 1584 * 1585 */ 1586 typedef struct agsaSetDeviceStateRsp_s { 1587 bit32 tag; 1588 bit32 status; 1589 bit32 deviceId; 1590 bit32 pds_nds; 1591 bit32 reserved[11]; 1592 } agsaSetDeviceStateRsp_t; 1593 1594 #define NDS_BITS 0x0F 1595 #define PDS_BITS 0xF0 1596 1597 /** \brief the data structure of Get Device State Response 1598 * 1599 * use to describe MPI Get Device State Response (64 bytes) 1600 * 1601 */ 1602 typedef struct agsaGetDeviceStateRsp_s { 1603 bit32 tag; 1604 bit32 status; 1605 bit32 deviceId; 1606 bit32 ds; 1607 bit32 reserved[11]; 1608 } agsaGetDeviceStateRsp_t; 1609 1610 /** \brief the data structure of Set Device Info Response 1611 * 1612 * use to describe MPI Set Device Info Response (64 bytes) 1613 * 1614 */ 1615 typedef struct agsaSetDeviceInfoRsp_s { 1616 bit32 tag; 1617 bit32 status; 1618 bit32 deviceId; 1619 bit32 SA_SR_SI; 1620 bit32 A_R_ITNT; 1621 bit32 reserved[10]; 1622 } agsaSetDeviceInfoRsp_t; 1623 1624 /** \brief the data structure of SAS Re_Initialize Response 1625 * 1626 * use to describe MPI SAS RE_INITIALIZE Response (64 bytes) 1627 * 1628 */ 1629 typedef struct agsaSasReInitializeRsp_s { 1630 bit32 tag; 1631 bit32 status; 1632 bit32 setFlags; 1633 bit32 MaxPorts; 1634 bit32 openRejReCmdData; 1635 bit32 sataHOLTMO; 1636 bit32 reserved[9]; 1637 } agsaSasReInitializeRsp_t; 1638 1639 /** \brief the data structure of SGPIO Response 1640 * 1641 * use to describe MPI serial GPIO Response IOMB (64 bytes) 1642 * 1643 */ 1644 typedef struct agsaSGpioRsp_s { 1645 bit32 tag; 1646 bit32 resultFunctionFrameType; 1647 bit32 readData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; 1648 } agsaSGpioRsp_t; 1649 1650 1651 /** \brief the data structure of PCIe diag response 1652 * 1653 * use to describe PCIe diag response IOMB (64 bytes) 1654 * 1655 */ 1656 1657 typedef struct agsaPCIeDiagExecuteRsp_s { 1658 bit32 tag; /* 1 */ 1659 bit32 CmdTypeDesc; /* 2 */ 1660 bit32 Status; /* 3 */ 1661 bit32 reservedDW4; /* 4 */ 1662 bit32 reservedDW5; /* 5 */ 1663 bit32 ERR_BLKH; /* 6 */ 1664 bit32 ERR_BLKL; /* 7 */ 1665 bit32 DWord8; /* 8 */ 1666 bit32 DWord9; /* 9 */ 1667 bit32 DWord10; /* 10 */ 1668 bit32 DWord11; /* 11 */ 1669 bit32 DIF_ERR; /* 12 */ 1670 bit32 reservedDW13; /* 13 */ 1671 bit32 reservedDW14; /* 14 */ 1672 bit32 reservedDW15; /* 15 */ 1673 } agsaPCIeDiagExecuteRsp_t; 1674 1675 /** \brief the data structure of PCI diag response 1676 * 1677 * use to describe PCI diag response IOMB for SPC (64 bytes) 1678 * 1679 */ 1680 1681 typedef struct agsa_SPC_PCIeDiagExecuteRsp_s { 1682 bit32 tag; /* 1 */ 1683 bit32 CmdTypeDesc; /* 2 */ 1684 bit32 Status; /* 3 */ 1685 bit32 reserved[12]; /* 4 15 */ 1686 } agsa_SPC_PCIeDiagExecuteRsp_t; 1687 1688 /** \brief the data structure of GET DFE Data Response 1689 * 1690 * use to describe GET DFE Data Response for SPCv (64 bytes) 1691 * 1692 */ 1693 typedef struct agsaGetDDEFDataRsp_s { 1694 bit32 tag; /* 1 */ 1695 bit32 status; /* 2 */ 1696 bit32 reserved_In_Ln;/* 3 */ 1697 bit32 MCNT; /* 4 */ 1698 bit32 NBT; /* 5 */ 1699 bit32 reserved[10]; /* 6 - 15 */ 1700 } agsaGetDDEFDataRsp_t; 1701 1702 /** \brief the data structure of GET Vis Data Response 1703 * 1704 * use to describe GET Vis Data Response for SPCv (64 bytes) 1705 * 1706 */ 1707 typedef struct agsaGetVHistCapRsp_s { 1708 bit32 tag; /* 1 */ 1709 bit32 status; /* 2 */ 1710 bit32 channel; /* 3 */ 1711 bit32 BistLo; /* 4 */ 1712 bit32 BistHi; /* 5 */ 1713 bit32 BytesXfered; /* 6 */ 1714 bit32 PciLo; /* 7 */ 1715 bit32 PciHi; /* 8 */ 1716 bit32 PciBytecount; /* 9 */ 1717 bit32 reserved[5]; /* 10 - 15 */ 1718 } agsaGetVHistCapRsp_t; 1719 1720 typedef struct agsaSetControllerConfigCmd_s { 1721 bit32 tag; 1722 bit32 pageCode; 1723 bit32 configPage[13]; /* Page code specific fields */ 1724 } agsaSetControllerConfigCmd_t; 1725 1726 1727 typedef struct agsaSetControllerConfigRsp_s { 1728 bit32 tag; 1729 bit32 status; 1730 bit32 errorQualifierPage; 1731 bit32 reserved[12]; 1732 } agsaSetControllerConfigRsp_t; 1733 1734 typedef struct agsaGetControllerConfigCmd_s { 1735 bit32 tag; 1736 bit32 pageCode; 1737 bit32 INT_VEC_MSK0; 1738 bit32 INT_VEC_MSK1; 1739 bit32 reserved[11]; 1740 } agsaGetControllerConfigCmd_t; 1741 1742 typedef struct agsaGetControllerConfigRsp_s { 1743 bit32 tag; 1744 bit32 status; 1745 bit32 errorQualifier; 1746 bit32 configPage[12]; /* Page code specific fields */ 1747 } agsaGetControllerConfigRsp_t; 1748 1749 typedef struct agsaDekManagementCmd_s { 1750 bit32 tag; 1751 bit32 KEKIDX_Reserved_TBLS_DSOP; 1752 bit32 dekIndex; 1753 bit32 tableAddrLo; 1754 bit32 tableAddrHi; 1755 bit32 tableEntries; 1756 bit32 Reserved_DBF_TBL_SIZE; 1757 } agsaDekManagementCmd_t; 1758 1759 typedef struct agsaDekManagementRsp_s { 1760 bit32 tag; 1761 bit32 status; 1762 bit32 flags; 1763 bit32 dekIndex; 1764 bit32 errorQualifier; 1765 bit32 reserved[12]; 1766 } agsaDekManagementRsp_t; 1767 1768 typedef struct agsaKekManagementCmd_s { 1769 bit32 tag; 1770 bit32 NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP; 1771 bit32 reserved; 1772 bit32 kekBlob[12]; 1773 } agsaKekManagementCmd_t; 1774 1775 typedef struct agsaKekManagementRsp_s { 1776 bit32 tag; 1777 bit32 status; 1778 bit32 flags; 1779 bit32 errorQualifier; 1780 bit32 reserved[12]; 1781 } agsaKekManagementRsp_t; 1782 1783 1784 typedef struct agsaCoalSspComplCxt_s { 1785 bit32 tag; 1786 bit16 SSPTag; 1787 bit16 reserved; 1788 } agsaCoalSspComplCxt_t; 1789 1790 /** \brief the data structure of SSP Completion Response 1791 * 1792 * use to describe MPI SSP Completion Response (1024 bytes) 1793 * 1794 */ 1795 typedef struct agsaSSPCoalescedCompletionRsp_s { 1796 bit32 coalescedCount; 1797 agsaCoalSspComplCxt_t sspComplCxt[1]; /* Open ended array */ 1798 } agsaSSPCoalescedCompletionRsp_t; 1799 1800 1801 /** \brief the data structure of SATA Completion Response 1802 * 1803 * use to describe MPI SATA Completion Response (1024 bytes) 1804 * 1805 */ 1806 typedef struct agsaCoalStpComplCxt_s { 1807 bit32 tag; 1808 bit16 reserved; 1809 } agsaCoalStpComplCxt_t; 1810 1811 typedef struct agsaSATACoalescedCompletionRsp_s { 1812 bit32 coalescedCount; 1813 agsaCoalStpComplCxt_t stpComplCxt[1]; /* Open ended array */ 1814 } agsaSATACoalescedCompletionRsp_t; 1815 1816 1817 /** \brief the data structure of Operator Mangement Command 1818 * 1819 * use to describe OPR_MGMT Command (128 bytes) 1820 * 1821 */ 1822 typedef struct agsaOperatorMangmentCmd_s{ 1823 bit32 tag; /* 1 */ 1824 bit32 OPRIDX_AUTIDX_R_KBF_PKT_OMO;/* 2 */ 1825 bit8 IDString_Role[32]; /* 3 10 */ 1826 #ifndef HAILEAH_HOST_6G_COMPITIBILITY_FLAG 1827 agsaEncryptKekBlob_t Kblob; /* 11 22 */ 1828 #endif 1829 bit32 reserved[8]; /* 23 31 */ 1830 } agsaOperatorMangmentCmd_t; 1831 1832 1833 /* 1834 * 1835 * use to describe OPR_MGMT Response (64 bytes) 1836 * 1837 */ 1838 typedef struct agsaOperatorMangmentRsp_s { 1839 bit32 tag; /* 1 */ 1840 bit32 status; /* 2 */ 1841 bit32 OPRIDX_AUTIDX_R_OMO; /* 3 */ 1842 bit32 errorQualifier; /* 4 */ 1843 bit32 reserved[10]; /* 5 15 */ 1844 } agsaOperatorMangmenRsp_t; 1845 1846 /** \brief the data structure of Set Operator Command 1847 * 1848 * use to describe Set Operator Command (64 bytes) 1849 * 1850 */ 1851 typedef struct agsaSetOperatorCmd_s{ 1852 bit32 tag; /* 1 */ 1853 bit32 OPRIDX_PIN_ACS; /* 2 */ 1854 bit32 cert[10]; /* 3 12 */ 1855 bit32 reserved[3]; /* 13 15 */ 1856 } agsaSetOperatorCmd_t; 1857 1858 /* 1859 * 1860 * use to describe Set Operator Response (64 bytes) 1861 * 1862 */ 1863 typedef struct agsaSetOperatorRsp_s { 1864 bit32 tag; /* 1 */ 1865 bit32 status; /* 2 */ 1866 bit32 ERR_QLFR_OPRIDX_PIN_ACS;/* 3 */ 1867 bit32 reserved[12]; /* 4 15 */ 1868 } agsaSetOperatorRsp_t; 1869 1870 /** \brief the data structure of Get Operator Command 1871 * 1872 * use to describe Get Operator Command (64 bytes) 1873 * 1874 */ 1875 typedef struct agsaGetOperatorCmd_s{ 1876 bit32 tag; /* 1 */ 1877 bit32 option; /* 2 */ 1878 bit32 OprBufAddrLo; /* 3 */ 1879 bit32 OprBufAddrHi; /* 4*/ 1880 bit32 reserved[11]; /*5 15*/ 1881 } agsaGetOperatorCmd_t; 1882 1883 /* 1884 * 1885 * use to describe Get Operator Response (64 bytes) 1886 * 1887 */ 1888 typedef struct agsaGetOperatorRsp_s { 1889 bit32 tag; /* 1 */ 1890 bit32 status; /* 2 */ 1891 bit32 Num_Option; /* 3 */ 1892 bit32 IDString[8]; /* 4 11*/ 1893 bit32 reserved[4]; /* 12 15*/ 1894 } agsaGetOperatorRsp_t; 1895 1896 /* 1897 * 1898 * use to start Encryption BIST (128 bytes) 1899 * 0x105 1900 */ 1901 typedef struct agsaEncryptBist_s { 1902 bit32 tag; /* 1 */ 1903 bit32 r_subop; /* 2 */ 1904 bit32 testDiscption[28]; /* 3 31 */ 1905 } agsaEncryptBist_t; 1906 1907 /* 1908 * 1909 * use to describe Encryption BIST Response (64 bytes) 1910 * 0x905 1911 */ 1912 1913 typedef struct agsaEncryptBistRsp_s { 1914 bit32 tag; /* 1 */ 1915 bit32 status; /* 2 */ 1916 bit32 subop; /* 3 */ 1917 bit32 testResults[11]; /* 4 15 */ 1918 } agsaEncryptBistRsp_t; 1919 1920 /** \brief the data structure of DifEncOffload Command 1921 * 1922 * use to describe Set DifEncOffload Command (128 bytes) 1923 * 1924 */ 1925 typedef struct agsaDifEncOffloadCmd_s{ 1926 bit32 tag; /* 1 */ 1927 bit32 option; /* 2 */ 1928 bit32 reserved[2]; /* 3-4 */ 1929 bit32 Src_Data_Len; /* 5 */ 1930 bit32 Dst_Data_Len; /* 6 */ 1931 bit32 flags; /* 7 */ 1932 bit32 UDTR01UDT01; /* 8 */ 1933 bit32 UDT2345; /* 9 */ 1934 bit32 UDTR2345; /* 10 */ 1935 bit32 DPLR0SecCnt_IOSeed; /* 11 */ 1936 bit32 DPL_Addr_Lo; /* 12 */ 1937 bit32 DPL_Addr_Hi; /* 13 */ 1938 bit32 KeyIndex_CMode_KTS_ENT_R; /* 14 */ 1939 bit32 EPLR0SecCnt_KS_ENSS; /* 15 */ 1940 bit32 keyTag_W0; /* 16 */ 1941 bit32 keyTag_W1; /* 17 */ 1942 bit32 tweakVal_W0; /* 18 */ 1943 bit32 tweakVal_W1; /* 19 */ 1944 bit32 tweakVal_W2; /* 20 */ 1945 bit32 tweakVal_W3; /* 21 */ 1946 bit32 EPL_Addr_Lo; /* 22 */ 1947 bit32 EPL_Addr_Hi; /* 23 */ 1948 agsaSgl_t SrcSgl; /* 24-27 */ 1949 agsaSgl_t DstSgl; /* 28-31 */ 1950 } agsaDifEncOffloadCmd_t; 1951 1952 /* 1953 * 1954 * use to describe DIF/Encryption Offload Response (32 bytes) 1955 * 0x910 1956 */ 1957 typedef struct agsaDifEncOffloadRspV_s { 1958 bit32 tag; 1959 bit32 status; 1960 bit32 ExpectedCRCUDT01; 1961 bit32 ExpectedUDT2345; 1962 bit32 ActualCRCUDT01; 1963 bit32 ActualUDT2345; 1964 bit32 DIFErr; 1965 bit32 ErrBoffset; 1966 } agsaDifEncOffloadRspV_t; 1967 1968 #endif /*__SAMPIDEFS_H__ */ 1969