1 /******************************************************************************* 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3 * 4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided 5 *that the following conditions are met: 6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7 *following disclaimer. 8 *2. Redistributions in binary form must reproduce the above copyright notice, 9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided 10 *with the distribution. 11 * 12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20 * 21 * 22 ********************************************************************************/ 23 /*******************************************************************************/ 24 25 /*! \file samacro.h 26 * \brief The file defines macros used in LL sTSDK 27 */ 28 29 /*******************************************************************************/ 30 31 #ifndef __SAMACRO_H__ 32 #define __SAMACRO_H__ 33 34 #if defined(SALLSDK_DEBUG) 35 #define MPI_IBQ_IOMB_LOG_ENABLE 36 #define MPI_OBQ_IOMB_LOG_ENABLE 37 #endif 38 39 /*! \def MIN(a,b) 40 * \brief MIN macro 41 * 42 * use to find MIN of two values 43 */ 44 #ifndef MIN 45 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 46 #endif 47 48 /*! \def MAX(a,b) 49 * \brief MAX macro 50 * 51 * use to find MAX of two values 52 */ 53 #ifndef MAX 54 #define MAX(a,b) ((a) < (b) ? (b) : (a)) 55 #endif 56 57 /************************************************************************************************* 58 * define Phy status macros * 59 *************************************************************************************************/ 60 /*! \def PHY_STATUS_SET(pPhy, value) 61 * \brief PHY_STATUS_SET macro 62 * 63 * use to set phy status 64 */ 65 #define PHY_STATUS_SET(pPhy, value) ((pPhy)->status = (((pPhy)->status & 0xFFFF0000) | (value))) 66 67 /*! \def PHY_STATUS_CHECK(pPhy, value) 68 * \brief PHY_STATUS_CHECK macro 69 * 70 * use to check phy status 71 */ 72 #define PHY_STATUS_CHECK(pPhy, value) ( ((pPhy)->status & 0x0000FFFF) == (value) ) 73 74 75 /************************************************************************************ 76 * define CBUFFER operation macros * 77 ************************************************************************************/ 78 /*! \def AGSAMEM_ELEMENT_READ(pMem, index) 79 * \brief AGSAMEM_ELEMENT_READ macro 80 * 81 * use to read an element of a memory array 82 */ 83 #define AGSAMEM_ELEMENT_READ(pMem, index) (((bit8 *)(pMem)->virtPtr) + (pMem)->singleElementLength * (index)) 84 85 /************************************************************************************ 86 * define Chip ID macro * 87 ************************************************************************************/ 88 89 #define SA_TREAT_SFC_AS_SPC 90 91 #ifdef SA_TREAT_SFC_AS_SPC 92 #define SA_SFC_AS_SPC 1 93 #define SA_SFC_AS_SPCV 0 94 #else /* TREAT_SFC_AS_SPCv */ 95 #define SA_SFC_AS_SPC 0 96 #define SA_SFC_AS_SPCV 1 97 #endif /* SA_TREAT_SFC_AS_SPC */ 98 99 #define IS_SDKDATA(agr) (((agr)->sdkData != agNULL ) ? 1 : 0) /* returns true if sdkdata is available */ 100 101 #define smIsCfgSpcREV_A(agr) (8 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */ 102 #define smIsCfgSpcREV_B(agr) (4 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */ 103 #define smIsCfgSpcREV_C(agr) (5 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */ 104 105 #define smIsCfgVREV_A(agr) (4 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVA */ 106 #define smIsCfgVREV_B(agr) (5 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVB */ 107 #define smIsCfgVREV_C(agr) (6 ==( ossaHwRegReadConfig32((agr), 8 ) & 0xF) ? 1 : 0) /* returns true config space read is REVC */ 108 109 #define smIsCfg8001(agr) (VEN_DEV_SPC == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ 110 #define smIsCfg8081(agr) (VEN_DEV_HIL == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000 ) ? 1 : 0) /* returns true config space read is Hialeah */ 111 112 #define smIsCfg_V8025(agr) (VEN_DEV_SFC == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SFC */ 113 114 #define smIsCfg_V8008(agr) (VEN_DEV_SPCV == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 115 #define smIsCfg_V8009(agr) (VEN_DEV_SPCVE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 116 #define smIsCfg_V8018(agr) (VEN_DEV_SPCVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 117 #define smIsCfg_V8019(agr) (VEN_DEV_SPCVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 118 119 #define smIsCfg_V8088(agr) (VEN_DEV_ADAPVP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 120 #define smIsCfg_V8089(agr) (VEN_DEV_ADAPVEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ 121 122 #define smIsCfg_V8070(agr) (VEN_DEV_SPC12V == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 123 #define smIsCfg_V8071(agr) (VEN_DEV_SPC12VE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 124 #define smIsCfg_V8072(agr) (VEN_DEV_SPC12VP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 125 #define smIsCfg_V8073(agr) (VEN_DEV_SPC12VEP== (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 126 127 #define smIsCfg_V8074(agr) (VEN_DEV_SPC12ADP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ 128 #define smIsCfg_V8075(agr) (VEN_DEV_SPC12ADPE == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ 129 #define smIsCfg_V8076(agr) (VEN_DEV_SPC12ADPP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ 130 #define smIsCfg_V8077(agr) (VEN_DEV_SPC12ADPEP == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ 131 #define smIsCfg_V8006(agr) (VEN_DEV_SPC12SATA == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is Adaptec SPC12v */ 132 #define smIsCfg_V9015(agr) (VEN_DEV_9015 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 133 #define smIsCfg_V9060(agr) (VEN_DEV_9060 == (ossaHwRegReadConfig32((agr),0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12v */ 134 135 #define smIsCfg_SPC_ANY(agr) ((smIsCfg8001((agr)) == 1) ? 1 : \ 136 (smIsCfg8081((agr)) == 1) ? 1 : \ 137 (smIsCfg_V8025((agr)) == 1) ? SA_SFC_AS_SPC : 0) 138 139 #define smIS_SPCV8008(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCV ) ? 1 : 0) : smIsCfg_V8008((agr))) 140 #define smIS_SPCV8009(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVE) ? 1 : 0) : smIsCfg_V8009((agr))) 141 #define smIS_SPCV8018(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVP) ? 1 : 0) : smIsCfg_V8018((agr))) 142 #define smIS_SPCV8019(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPCVEP) ? 1 : 0) : smIsCfg_V8019((agr))) 143 #define smIS_ADAP8088(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVP) ? 1 : 0) : smIsCfg_V8088((agr))) 144 #define smIS_ADAP8089(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_ADAPVEP)? 1 : 0): smIsCfg_V8089((agr))) 145 146 #define smIS_SPCV8070(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12V ) ? 1 : 0) : smIsCfg_V8070((agr))) 147 #define smIS_SPCV8071(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VE) ? 1 : 0) : smIsCfg_V8071((agr))) 148 #define smIS_SPCV8072(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VP) ? 1 : 0) : smIsCfg_V8072((agr))) 149 #define smIS_SPCV8073(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12VEP)? 1 : 0) : smIsCfg_V8073((agr))) 150 151 #define smIS_SPCV8074(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADP ) ? 1 : 0) : smIsCfg_V8074((agr))) 152 #define smIS_SPCV8075(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPE) ? 1 : 0) : smIsCfg_V8075((agr))) 153 #define smIS_SPCV8076(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPP) ? 1 : 0) : smIsCfg_V8076((agr))) 154 #define smIS_SPCV8077(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12ADPEP)? 1 : 0) : smIsCfg_V8077((agr))) 155 #define smIS_SPCV8006(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC12SATA) ? 1 : 0) : smIsCfg_V8006((agr))) 156 #define smIS_SPCV9015(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9015) ? 1 : 0) : smIsCfg_V9015((agr))) 157 #define smIS_SPCV9060(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_9060) ? 1 : 0) : smIsCfg_V9060((agr))) 158 159 #define smIS_SPCV8025(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC ) ? 1 : 0) : smIsCfg_V8025((agr))) 160 161 #define smIS_SFC(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SFC ) ? 1 : 0) : smIsCfg_V8025((agr))) 162 #define smIS_spc8001(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_SPC ) ? 1 : 0) : smIsCfg8001((agr))) 163 #define smIS_spc8081(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->ChipId == VEN_DEV_HIL ) ? 1 : 0) : smIsCfg8081((agr))) 164 165 166 167 #define smIS_SFC_AS_SPC(agr) ((smIS_SFC((agr)) == 1) ? SA_SFC_AS_SPC : 0 ) 168 169 #define smIS_SFC_AS_V(agr) ((smIS_SFC((agr)) == 1 )? SA_SFC_AS_SPCV : 0 ) 170 171 /* Use 64 bit interrupts for SPCv, before getting saroot. Once saroot available only use 64bit when needed */ 172 #define smIS64bInt(agr) (IS_SDKDATA((agr)) ? ( (((agsaLLRoot_t *)((agr)->sdkData))->Use64bit) ? 1 : 0) : smIS_SPCV(agr)) 173 174 #define WHATTABLE(agr) \ 175 ( \ 176 IS_SDKDATA((agr)) ? \ 177 (smIS_SPC((agr)) ? &SPCTable[0] : (smIS_SPCV((agr)) ? &SPC_V_Table[0] : agNULL ) ) \ 178 : \ 179 (smIsCfg_SPC_ANY((agr)) ? &SPCTable[0] : (smIsCfg_V_ANY((agr)) ? &SPC_V_Table[0] : agNULL ) ) \ 180 ) \ 181 182 #if defined(SALLSDK_DEBUG) 183 /* 184 * for debugging purposes. 185 */ 186 extern bit32 gLLDebugLevel; 187 188 #define SA_DBG0(format) ossaLogDebugString(gLLDebugLevel, 0, format) 189 #define SA_DBG1(format) ossaLogDebugString(gLLDebugLevel, 1, format) 190 #define SA_DBG2(format) ossaLogDebugString(gLLDebugLevel, 2, format) 191 #define SA_DBG3(format) ossaLogDebugString(gLLDebugLevel, 3, format) 192 #define SA_DBG4(format) ossaLogDebugString(gLLDebugLevel, 4, format) 193 #define SA_DBG5(format) ossaLogDebugString(gLLDebugLevel, 5, format) 194 #define SA_DBG6(format) ossaLogDebugString(gLLDebugLevel, 6, format) 195 196 #else 197 198 #define SA_DBG0(format) 199 #define SA_DBG1(format) 200 #define SA_DBG2(format) 201 #define SA_DBG3(format) 202 #define SA_DBG4(format) 203 #define SA_DBG5(format) 204 #define SA_DBG6(format) 205 206 #endif 207 208 #define SA_ASSERT OS_ASSERT 209 210 typedef enum siPrintType_e 211 { 212 SA_8, 213 SA_16, 214 SA_32 215 } siPrintType; 216 217 #if defined(SALLSDK_DEBUG) 218 #define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) siPrintBuffer(lDebugLevel,lWidth,pHeader,pBuffer,lLength) 219 #else 220 #define SA_PRINTBUF(lDebugLevel,lWidth,pHeader,pBuffer,lLength) 221 #endif 222 223 #ifdef SALLSDK_DEBUG 224 225 #define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) siDumpSSPStartIu(agDevHandle,agRequestType,agRequestBody) 226 227 #else 228 229 #define DBG_DUMP_SSPSTART_CMDIU(agDevHandle,agRequestType,agRequestBody) 230 231 #endif 232 233 #ifdef MPI_DEBUG_TRACE_ENABLE 234 #define MPI_DEBUG_TRACE_ENTER_LOCK ossaSingleThreadedEnter(agRoot, LL_IOMB_TRACE_LOCK); 235 #define MPI_DEBUG_TRACE_LEAVE_LOCK ossaSingleThreadedLeave(agRoot, LL_IOMB_TRACE_LOCK); 236 237 #define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) \ 238 MPI_DEBUG_TRACE_ENTER_LOCK \ 239 mpiTraceAdd( (queue), (pici),(ib), (iomb), (count)); \ 240 MPI_DEBUG_TRACE_LEAVE_LOCK 241 #else 242 #define MPI_DEBUG_TRACE( queue, pici, ib,iomb,count) 243 #endif /* MPI_DEBUG_TRACE_ENABLE */ 244 245 #ifdef MPI_IBQ_IOMB_LOG_ENABLE 246 #define MPI_IBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \ 247 do \ 248 { \ 249 bit32 i; \ 250 SA_DBG3(("\n")); \ 251 SA_DBG3(("mpiMsgProduce: IBQ %d\n", (qNumber))); \ 252 for (i = 0; i < msgLength/16; i++) \ 253 { \ 254 SA_DBG3(("Inb: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \ 255 *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \ 256 *((bit32 *)msgHeader+(i*4)+3))); \ 257 } \ 258 } while(0) 259 #endif 260 #ifdef MPI_OBQ_IOMB_LOG_ENABLE 261 #define MPI_OBQ_IOMB_LOG(qNumber, msgHeader, msgLength) \ 262 do \ 263 { \ 264 bit32 i; \ 265 SA_DBG3(("\n")); \ 266 SA_DBG3(("mpiMsgConsume: OBQ %d\n", qNumber)); \ 267 for (i = 0; i < msgLength/16; i++) \ 268 { \ 269 SA_DBG3(("Out: DW %02d 0x%08x 0x%08x 0x%08x 0x%08x\n", i*4, *((bit32 *)msgHeader+(i*4)), \ 270 *((bit32 *)msgHeader+(i*4)+1), *((bit32 *)msgHeader+(i*4)+2), \ 271 *((bit32 *)msgHeader+(i*4)+3))); \ 272 } \ 273 } while(0) 274 #endif 275 276 277 /************************************************************************************ 278 * Wait X Second * 279 ************************************************************************************/ 280 281 #define WAIT_SECONDS(x) ((x) * 1000 * 1000 ) 282 #define ONE_HUNDRED_MILLISECS (100 * 1000) /* 100,000 microseconds */ 283 284 #define WAIT_INCREMENT_DEFAULT 1000 285 #define WAIT_INCREMENT (IS_SDKDATA(agRoot) ? ( ((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs ) : WAIT_INCREMENT_DEFAULT ) 286 // (((agsaLLRoot_t *)(agRoot->sdkData))->minStallusecs) 287 288 289 #define MAKE_MODULO(a,b) (((a) % (b)) ? ((a) - ((a) % (b))) : (a)) 290 291 292 #define HDA_STEP_2 1 293 #define HDA_STEP_3 1 294 #define HDA_STEP_4 1 295 #define HDA_STEP_5 1 296 #define HDA_STEP_6 1 297 #define HDA_STEP_7 1 298 #define HDA_STEP_8 1 299 300 #endif /* __SAMACRO_H__ */ 301